Revision 5a6fdd91
b/hw/pxa.h | ||
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78 | 78 |
|
79 | 79 |
/* pxa2xx_lcd.c */ |
80 | 80 |
typedef struct PXA2xxLCDState PXA2xxLCDState; |
81 |
PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
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|
82 |
qemu_irq irq); |
|
81 |
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
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82 |
target_phys_addr_t base, qemu_irq irq);
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|
83 | 83 |
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); |
84 | 84 |
void pxa2xx_lcdc_oritentation(void *opaque, int angle); |
85 | 85 |
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b/hw/pxa2xx.c | ||
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2094 | 2094 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), |
2095 | 2095 |
serial_hds[i]); |
2096 | 2096 |
|
2097 |
s->lcd = pxa2xx_lcdc_init(0x44000000, |
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2097 |
s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
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|
2098 | 2098 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
2099 | 2099 |
|
2100 | 2100 |
s->cm_base = 0x41300000; |
... | ... | |
2223 | 2223 |
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), |
2224 | 2224 |
serial_hds[i]); |
2225 | 2225 |
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2226 |
s->lcd = pxa2xx_lcdc_init(0x44000000, |
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2226 |
s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
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2227 | 2227 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
2228 | 2228 |
|
2229 | 2229 |
s->cm_base = 0x41300000; |
b/hw/pxa2xx_lcd.c | ||
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30 | 30 |
}; |
31 | 31 |
|
32 | 32 |
struct PXA2xxLCDState { |
33 |
MemoryRegion iomem; |
|
33 | 34 |
qemu_irq irq; |
34 | 35 |
int irqlevel; |
35 | 36 |
|
... | ... | |
315 | 316 |
} |
316 | 317 |
} |
317 | 318 |
|
318 |
static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) |
|
319 |
static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset, |
|
320 |
unsigned size) |
|
319 | 321 |
{ |
320 | 322 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
321 | 323 |
int ch; |
... | ... | |
408 | 410 |
return 0; |
409 | 411 |
} |
410 | 412 |
|
411 |
static void pxa2xx_lcdc_write(void *opaque, |
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target_phys_addr_t offset, uint32_t value)
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413 |
static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
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414 |
uint64_t value, unsigned size)
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|
413 | 415 |
{ |
414 | 416 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
415 | 417 |
int ch; |
... | ... | |
561 | 563 |
} |
562 | 564 |
} |
563 | 565 |
|
564 |
static CPUReadMemoryFunc * const pxa2xx_lcdc_readfn[] = { |
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565 |
pxa2xx_lcdc_read, |
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566 |
pxa2xx_lcdc_read, |
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567 |
pxa2xx_lcdc_read |
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568 |
}; |
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569 |
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570 |
static CPUWriteMemoryFunc * const pxa2xx_lcdc_writefn[] = { |
|
571 |
pxa2xx_lcdc_write, |
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572 |
pxa2xx_lcdc_write, |
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pxa2xx_lcdc_write |
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566 |
static const MemoryRegionOps pxa2xx_lcdc_ops = { |
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567 |
.read = pxa2xx_lcdc_read, |
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.write = pxa2xx_lcdc_write, |
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569 |
.endianness = DEVICE_NATIVE_ENDIAN, |
|
574 | 570 |
}; |
575 | 571 |
|
576 | 572 |
/* Load new palette for a given DMA channel, convert to internal format */ |
... | ... | |
981 | 977 |
#define BITS 32 |
982 | 978 |
#include "pxa2xx_template.h" |
983 | 979 |
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984 |
PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) |
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980 |
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, |
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981 |
target_phys_addr_t base, qemu_irq irq) |
|
985 | 982 |
{ |
986 |
int iomemtype; |
|
987 | 983 |
PXA2xxLCDState *s; |
988 | 984 |
|
989 | 985 |
s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState)); |
... | ... | |
992 | 988 |
|
993 | 989 |
pxa2xx_lcdc_orientation(s, graphic_rotate); |
994 | 990 |
|
995 |
iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn,
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996 |
pxa2xx_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
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997 |
cpu_register_physical_memory(base, 0x00100000, iomemtype);
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991 |
memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
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992 |
"pxa2xx-lcd-controller", 0x00100000);
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993 |
memory_region_add_subregion(sysmem, base, &s->iomem);
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998 | 994 |
|
999 | 995 |
s->ds = graphic_console_init(pxa2xx_update_display, |
1000 | 996 |
pxa2xx_invalidate_display, |
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