Revision 5a6fdd91 hw/pxa2xx_lcd.c
| b/hw/pxa2xx_lcd.c | ||
|---|---|---|
| 30 | 30 |
}; |
| 31 | 31 |
|
| 32 | 32 |
struct PXA2xxLCDState {
|
| 33 |
MemoryRegion iomem; |
|
| 33 | 34 |
qemu_irq irq; |
| 34 | 35 |
int irqlevel; |
| 35 | 36 |
|
| ... | ... | |
| 315 | 316 |
} |
| 316 | 317 |
} |
| 317 | 318 |
|
| 318 |
static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) |
|
| 319 |
static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset, |
|
| 320 |
unsigned size) |
|
| 319 | 321 |
{
|
| 320 | 322 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
| 321 | 323 |
int ch; |
| ... | ... | |
| 408 | 410 |
return 0; |
| 409 | 411 |
} |
| 410 | 412 |
|
| 411 |
static void pxa2xx_lcdc_write(void *opaque, |
|
| 412 |
target_phys_addr_t offset, uint32_t value)
|
|
| 413 |
static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
|
|
| 414 |
uint64_t value, unsigned size)
|
|
| 413 | 415 |
{
|
| 414 | 416 |
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
| 415 | 417 |
int ch; |
| ... | ... | |
| 561 | 563 |
} |
| 562 | 564 |
} |
| 563 | 565 |
|
| 564 |
static CPUReadMemoryFunc * const pxa2xx_lcdc_readfn[] = {
|
|
| 565 |
pxa2xx_lcdc_read, |
|
| 566 |
pxa2xx_lcdc_read, |
|
| 567 |
pxa2xx_lcdc_read |
|
| 568 |
}; |
|
| 569 |
|
|
| 570 |
static CPUWriteMemoryFunc * const pxa2xx_lcdc_writefn[] = {
|
|
| 571 |
pxa2xx_lcdc_write, |
|
| 572 |
pxa2xx_lcdc_write, |
|
| 573 |
pxa2xx_lcdc_write |
|
| 566 |
static const MemoryRegionOps pxa2xx_lcdc_ops = {
|
|
| 567 |
.read = pxa2xx_lcdc_read, |
|
| 568 |
.write = pxa2xx_lcdc_write, |
|
| 569 |
.endianness = DEVICE_NATIVE_ENDIAN, |
|
| 574 | 570 |
}; |
| 575 | 571 |
|
| 576 | 572 |
/* Load new palette for a given DMA channel, convert to internal format */ |
| ... | ... | |
| 981 | 977 |
#define BITS 32 |
| 982 | 978 |
#include "pxa2xx_template.h" |
| 983 | 979 |
|
| 984 |
PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) |
|
| 980 |
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, |
|
| 981 |
target_phys_addr_t base, qemu_irq irq) |
|
| 985 | 982 |
{
|
| 986 |
int iomemtype; |
|
| 987 | 983 |
PXA2xxLCDState *s; |
| 988 | 984 |
|
| 989 | 985 |
s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState)); |
| ... | ... | |
| 992 | 988 |
|
| 993 | 989 |
pxa2xx_lcdc_orientation(s, graphic_rotate); |
| 994 | 990 |
|
| 995 |
iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn,
|
|
| 996 |
pxa2xx_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 997 |
cpu_register_physical_memory(base, 0x00100000, iomemtype);
|
|
| 991 |
memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
|
|
| 992 |
"pxa2xx-lcd-controller", 0x00100000);
|
|
| 993 |
memory_region_add_subregion(sysmem, base, &s->iomem);
|
|
| 998 | 994 |
|
| 999 | 995 |
s->ds = graphic_console_init(pxa2xx_update_display, |
| 1000 | 996 |
pxa2xx_invalidate_display, |
Also available in: Unified diff