Revision 5a834bb4
| b/gdbstub.c | ||
|---|---|---|
| 804 | 804 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ |
| 805 | 805 |
switch (n) {
|
| 806 | 806 |
case 64: GET_REGA(env->y); |
| 807 |
case 65: GET_REGA(GET_PSR(env));
|
|
| 807 |
case 65: GET_REGA(cpu_get_psr(env));
|
|
| 808 | 808 |
case 66: GET_REGA(env->wim); |
| 809 | 809 |
case 67: GET_REGA(env->tbr); |
| 810 | 810 |
case 68: GET_REGA(env->pc); |
| ... | ... | |
| 829 | 829 |
switch (n) {
|
| 830 | 830 |
case 80: GET_REGL(env->pc); |
| 831 | 831 |
case 81: GET_REGL(env->npc); |
| 832 |
case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
|
|
| 833 |
((env->asi & 0xff) << 24) |
|
|
| 834 |
((env->pstate & 0xfff) << 8) |
|
|
| 835 |
GET_CWP64(env));
|
|
| 832 |
case 82: GET_REGL((cpu_get_ccr(env) << 32) |
|
|
| 833 |
((env->asi & 0xff) << 24) | |
|
| 834 |
((env->pstate & 0xfff) << 8) | |
|
| 835 |
cpu_get_cwp64(env));
|
|
| 836 | 836 |
case 83: GET_REGL(env->fsr); |
| 837 | 837 |
case 84: GET_REGL(env->fprs); |
| 838 | 838 |
case 85: GET_REGL(env->y); |
| ... | ... | |
| 868 | 868 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ |
| 869 | 869 |
switch (n) {
|
| 870 | 870 |
case 64: env->y = tmp; break; |
| 871 |
case 65: PUT_PSR(env, tmp); break;
|
|
| 871 |
case 65: cpu_put_psr(env, tmp); break;
|
|
| 872 | 872 |
case 66: env->wim = tmp; break; |
| 873 | 873 |
case 67: env->tbr = tmp; break; |
| 874 | 874 |
case 68: env->pc = tmp; break; |
| ... | ... | |
| 892 | 892 |
case 80: env->pc = tmp; break; |
| 893 | 893 |
case 81: env->npc = tmp; break; |
| 894 | 894 |
case 82: |
| 895 |
PUT_CCR(env, tmp >> 32);
|
|
| 895 |
cpu_put_ccr(env, tmp >> 32);
|
|
| 896 | 896 |
env->asi = (tmp >> 24) & 0xff; |
| 897 | 897 |
env->pstate = (tmp >> 8) & 0xfff; |
| 898 |
PUT_CWP64(env, tmp & 0xff);
|
|
| 898 |
cpu_put_cwp64(env, tmp & 0xff);
|
|
| 899 | 899 |
break; |
| 900 | 900 |
case 83: env->fsr = tmp; break; |
| 901 | 901 |
case 84: env->fprs = tmp; break; |
| b/linux-user/signal.c | ||
|---|---|---|
| 2111 | 2111 |
err |= __get_user(env->y, &((*grp)[MC_Y])); |
| 2112 | 2112 |
err |= __get_user(tstate, &((*grp)[MC_TSTATE])); |
| 2113 | 2113 |
env->asi = (tstate >> 24) & 0xff; |
| 2114 |
PUT_CCR(env, tstate >> 32);
|
|
| 2115 |
PUT_CWP64(env, tstate & 0x1f);
|
|
| 2114 |
cpu_put_ccr(env, tstate >> 32);
|
|
| 2115 |
cpu_put_cwp64(env, tstate & 0x1f);
|
|
| 2116 | 2116 |
err |= __get_user(env->gregs[1], (&(*grp)[MC_G1])); |
| 2117 | 2117 |
err |= __get_user(env->gregs[2], (&(*grp)[MC_G2])); |
| 2118 | 2118 |
err |= __get_user(env->gregs[3], (&(*grp)[MC_G3])); |
| b/monitor.c | ||
|---|---|---|
| 2856 | 2856 |
static target_long monitor_get_psr (const struct MonitorDef *md, int val) |
| 2857 | 2857 |
{
|
| 2858 | 2858 |
CPUState *env = mon_get_cpu(); |
| 2859 |
return GET_PSR(env); |
|
| 2859 |
|
|
| 2860 |
return cpu_get_psr(env); |
|
| 2860 | 2861 |
} |
| 2861 | 2862 |
#endif |
| 2862 | 2863 |
|
| b/target-sparc/cpu.h | ||
|---|---|---|
| 434 | 434 |
sparc_def_t *def; |
| 435 | 435 |
} CPUSPARCState; |
| 436 | 436 |
|
| 437 |
#ifndef NO_CPU_IO_DEFS |
|
| 437 | 438 |
/* helper.c */ |
| 438 | 439 |
CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
| 439 | 440 |
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
| ... | ... | |
| 453 | 454 |
/* cpu-exec.c */ |
| 454 | 455 |
int cpu_sparc_exec(CPUSPARCState *s); |
| 455 | 456 |
|
| 456 |
#if !defined (TARGET_SPARC64) |
|
| 457 |
#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \ |
|
| 458 |
(env->psref? PSR_EF : 0) | \ |
|
| 459 |
(env->psrpil << 8) | \ |
|
| 460 |
(env->psrs? PSR_S : 0) | \ |
|
| 461 |
(env->psrps? PSR_PS : 0) | \ |
|
| 462 |
(env->psret? PSR_ET : 0) | env->cwp) |
|
| 463 |
#else |
|
| 464 |
#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \ |
|
| 465 |
(env->psref? PSR_EF : 0) | \ |
|
| 466 |
(env->psrpil << 8) | \ |
|
| 467 |
(env->psrs? PSR_S : 0) | \ |
|
| 468 |
(env->psrps? PSR_PS : 0) | \ |
|
| 469 |
env->cwp) |
|
| 470 |
#endif |
|
| 471 |
|
|
| 472 |
#ifndef NO_CPU_IO_DEFS |
|
| 473 |
|
|
| 474 |
static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp) |
|
| 475 |
{
|
|
| 476 |
if (unlikely(cwp >= env1->nwindows)) |
|
| 477 |
cwp -= env1->nwindows; |
|
| 478 |
return cwp; |
|
| 479 |
} |
|
| 480 |
|
|
| 481 |
static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp) |
|
| 482 |
{
|
|
| 483 |
if (unlikely(cwp < 0)) |
|
| 484 |
cwp += env1->nwindows; |
|
| 485 |
return cwp; |
|
| 486 |
} |
|
| 457 |
/* op_helper.c */ |
|
| 458 |
target_ulong cpu_get_psr(CPUState *env1); |
|
| 459 |
void cpu_put_psr(CPUState *env1, target_ulong val); |
|
| 460 |
#ifdef TARGET_SPARC64 |
|
| 461 |
target_ulong cpu_get_ccr(CPUState *env1); |
|
| 462 |
void cpu_put_ccr(CPUState *env1, target_ulong val); |
|
| 463 |
target_ulong cpu_get_cwp64(CPUState *env1); |
|
| 464 |
void cpu_put_cwp64(CPUState *env1, int cwp); |
|
| 487 | 465 |
#endif |
| 488 |
|
|
| 489 |
static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
|
| 490 |
{
|
|
| 491 |
dst[0] = src[0]; |
|
| 492 |
dst[1] = src[1]; |
|
| 493 |
dst[2] = src[2]; |
|
| 494 |
dst[3] = src[3]; |
|
| 495 |
dst[4] = src[4]; |
|
| 496 |
dst[5] = src[5]; |
|
| 497 |
dst[6] = src[6]; |
|
| 498 |
dst[7] = src[7]; |
|
| 499 |
} |
|
| 500 |
|
|
| 501 |
static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp) |
|
| 502 |
{
|
|
| 503 |
/* put the modified wrap registers at their proper location */ |
|
| 504 |
if (env1->cwp == env1->nwindows - 1) |
|
| 505 |
memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16); |
|
| 506 |
env1->cwp = new_cwp; |
|
| 507 |
/* put the wrap registers at their temporary location */ |
|
| 508 |
if (new_cwp == env1->nwindows - 1) |
|
| 509 |
memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase); |
|
| 510 |
env1->regwptr = env1->regbase + (new_cwp * 16); |
|
| 511 |
} |
|
| 466 |
int cpu_cwp_inc(CPUState *env1, int cwp); |
|
| 467 |
int cpu_cwp_dec(CPUState *env1, int cwp); |
|
| 468 |
void cpu_set_cwp(CPUState *env1, int new_cwp); |
|
| 512 | 469 |
|
| 513 | 470 |
/* sun4m.c, sun4u.c */ |
| 514 | 471 |
void cpu_check_irqs(CPUSPARCState *env); |
| ... | ... | |
| 530 | 487 |
} |
| 531 | 488 |
|
| 532 | 489 |
#endif |
| 533 |
|
|
| 534 |
static inline void PUT_PSR(CPUSPARCState *env1, target_ulong val) |
|
| 535 |
{
|
|
| 536 |
env1->psr = val & PSR_ICC; |
|
| 537 |
env1->psref = (val & PSR_EF)? 1 : 0; |
|
| 538 |
env1->psrpil = (val & PSR_PIL) >> 8; |
|
| 539 |
#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY)) |
|
| 540 |
cpu_check_irqs(env1); |
|
| 541 |
#endif |
|
| 542 |
env1->psrs = (val & PSR_S)? 1 : 0; |
|
| 543 |
env1->psrps = (val & PSR_PS)? 1 : 0; |
|
| 544 |
#if !defined (TARGET_SPARC64) |
|
| 545 |
env1->psret = (val & PSR_ET)? 1 : 0; |
|
| 546 |
#endif |
|
| 547 |
cpu_set_cwp(env1, val & PSR_CWP); |
|
| 548 |
env1->cc_op = CC_OP_FLAGS; |
|
| 549 |
} |
|
| 550 |
|
|
| 551 |
#ifdef TARGET_SPARC64 |
|
| 552 |
#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) |
|
| 553 |
#define PUT_CCR(env, val) do { int _tmp = val; \
|
|
| 554 |
env->xcc = (_tmp >> 4) << 20; \ |
|
| 555 |
env->psr = (_tmp & 0xf) << 20; \ |
|
| 556 |
CC_OP = CC_OP_FLAGS; \ |
|
| 557 |
} while (0) |
|
| 558 |
#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp) |
|
| 559 |
|
|
| 560 |
#ifndef NO_CPU_IO_DEFS |
|
| 561 |
static inline void PUT_CWP64(CPUSPARCState *env1, int cwp) |
|
| 562 |
{
|
|
| 563 |
if (unlikely(cwp >= env1->nwindows || cwp < 0)) |
|
| 564 |
cwp %= env1->nwindows; |
|
| 565 |
cpu_set_cwp(env1, env1->nwindows - 1 - cwp); |
|
| 566 |
} |
|
| 567 |
#endif |
|
| 568 | 490 |
#endif |
| 569 | 491 |
|
| 570 | 492 |
/* cpu-exec.c */ |
| b/target-sparc/helper.c | ||
|---|---|---|
| 1490 | 1490 |
} |
| 1491 | 1491 |
#ifdef TARGET_SPARC64 |
| 1492 | 1492 |
cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, |
| 1493 |
GET_CCR(env));
|
|
| 1494 |
cpu_print_cc(f, cpu_fprintf, GET_CCR(env) << PSR_CARRY_SHIFT);
|
|
| 1493 |
cpu_get_ccr(env));
|
|
| 1494 |
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
|
|
| 1495 | 1495 |
cpu_fprintf(f, " xcc: "); |
| 1496 |
cpu_print_cc(f, cpu_fprintf, GET_CCR(env) << (PSR_CARRY_SHIFT - 4));
|
|
| 1496 |
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
|
|
| 1497 | 1497 |
cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl, |
| 1498 | 1498 |
env->psrpil); |
| 1499 | 1499 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " |
| ... | ... | |
| 1503 | 1503 |
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: " |
| 1504 | 1504 |
TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs); |
| 1505 | 1505 |
#else |
| 1506 |
cpu_fprintf(f, "psr: %08x (icc: ", GET_PSR(env));
|
|
| 1507 |
cpu_print_cc(f, cpu_fprintf, GET_PSR(env));
|
|
| 1506 |
cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
|
|
| 1507 |
cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
|
|
| 1508 | 1508 |
cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs? 'S' : '-', |
| 1509 | 1509 |
env->psrps? 'P' : '-', env->psret? 'E' : '-', |
| 1510 | 1510 |
env->wim); |
| b/target-sparc/machine.c | ||
|---|---|---|
| 33 | 33 |
qemu_put_betls(f, &env->pc); |
| 34 | 34 |
qemu_put_betls(f, &env->npc); |
| 35 | 35 |
qemu_put_betls(f, &env->y); |
| 36 |
tmp = GET_PSR(env);
|
|
| 36 |
tmp = cpu_get_psr(env);
|
|
| 37 | 37 |
qemu_put_be32(f, tmp); |
| 38 | 38 |
qemu_put_betls(f, &env->fsr); |
| 39 | 39 |
qemu_put_betls(f, &env->tbr); |
| ... | ... | |
| 130 | 130 |
tmp = qemu_get_be32(f); |
| 131 | 131 |
env->cwp = 0; /* needed to ensure that the wrapping registers are |
| 132 | 132 |
correctly updated */ |
| 133 |
PUT_PSR(env, tmp);
|
|
| 133 |
cpu_put_psr(env, tmp);
|
|
| 134 | 134 |
qemu_get_betls(f, &env->fsr); |
| 135 | 135 |
qemu_get_betls(f, &env->tbr); |
| 136 | 136 |
tmp = qemu_get_be32(f); |
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 253 | 253 |
raise_exception(tt); |
| 254 | 254 |
} |
| 255 | 255 |
|
| 256 |
static inline void set_cwp(int new_cwp) |
|
| 257 |
{
|
|
| 258 |
cpu_set_cwp(env, new_cwp); |
|
| 259 |
} |
|
| 260 |
|
|
| 261 | 256 |
void helper_check_align(target_ulong addr, uint32_t align) |
| 262 | 257 |
{
|
| 263 | 258 |
if (addr & align) {
|
| ... | ... | |
| 1295 | 1290 |
return ret; |
| 1296 | 1291 |
} |
| 1297 | 1292 |
|
| 1293 |
static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
|
| 1294 |
{
|
|
| 1295 |
dst[0] = src[0]; |
|
| 1296 |
dst[1] = src[1]; |
|
| 1297 |
dst[2] = src[2]; |
|
| 1298 |
dst[3] = src[3]; |
|
| 1299 |
dst[4] = src[4]; |
|
| 1300 |
dst[5] = src[5]; |
|
| 1301 |
dst[6] = src[6]; |
|
| 1302 |
dst[7] = src[7]; |
|
| 1303 |
} |
|
| 1304 |
|
|
| 1305 |
static void set_cwp(int new_cwp) |
|
| 1306 |
{
|
|
| 1307 |
/* put the modified wrap registers at their proper location */ |
|
| 1308 |
if (env->cwp == env->nwindows - 1) {
|
|
| 1309 |
memcpy32(env->regbase, env->regbase + env->nwindows * 16); |
|
| 1310 |
} |
|
| 1311 |
env->cwp = new_cwp; |
|
| 1312 |
|
|
| 1313 |
/* put the wrap registers at their temporary location */ |
|
| 1314 |
if (new_cwp == env->nwindows - 1) {
|
|
| 1315 |
memcpy32(env->regbase + env->nwindows * 16, env->regbase); |
|
| 1316 |
} |
|
| 1317 |
env->regwptr = env->regbase + (new_cwp * 16); |
|
| 1318 |
} |
|
| 1319 |
|
|
| 1320 |
void cpu_set_cwp(CPUState *env1, int new_cwp) |
|
| 1321 |
{
|
|
| 1322 |
CPUState *saved_env; |
|
| 1323 |
|
|
| 1324 |
saved_env = env; |
|
| 1325 |
env = env1; |
|
| 1326 |
set_cwp(new_cwp); |
|
| 1327 |
env = saved_env; |
|
| 1328 |
} |
|
| 1329 |
|
|
| 1330 |
static target_ulong get_psr(void) |
|
| 1331 |
{
|
|
| 1332 |
helper_compute_psr(); |
|
| 1333 |
|
|
| 1334 |
#if !defined (TARGET_SPARC64) |
|
| 1335 |
return env->version | (env->psr & PSR_ICC) | |
|
| 1336 |
(env->psref? PSR_EF : 0) | |
|
| 1337 |
(env->psrpil << 8) | |
|
| 1338 |
(env->psrs? PSR_S : 0) | |
|
| 1339 |
(env->psrps? PSR_PS : 0) | |
|
| 1340 |
(env->psret? PSR_ET : 0) | env->cwp; |
|
| 1341 |
#else |
|
| 1342 |
return env->version | (env->psr & PSR_ICC) | |
|
| 1343 |
(env->psref? PSR_EF : 0) | |
|
| 1344 |
(env->psrpil << 8) | |
|
| 1345 |
(env->psrs? PSR_S : 0) | |
|
| 1346 |
(env->psrps? PSR_PS : 0) | env->cwp; |
|
| 1347 |
#endif |
|
| 1348 |
} |
|
| 1349 |
|
|
| 1350 |
target_ulong cpu_get_psr(CPUState *env1) |
|
| 1351 |
{
|
|
| 1352 |
CPUState *saved_env; |
|
| 1353 |
target_ulong ret; |
|
| 1354 |
|
|
| 1355 |
saved_env = env; |
|
| 1356 |
env = env1; |
|
| 1357 |
ret = get_psr(); |
|
| 1358 |
env = saved_env; |
|
| 1359 |
return ret; |
|
| 1360 |
} |
|
| 1361 |
|
|
| 1362 |
static void put_psr(target_ulong val) |
|
| 1363 |
{
|
|
| 1364 |
env->psr = val & PSR_ICC; |
|
| 1365 |
env->psref = (val & PSR_EF)? 1 : 0; |
|
| 1366 |
env->psrpil = (val & PSR_PIL) >> 8; |
|
| 1367 |
#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY)) |
|
| 1368 |
cpu_check_irqs(env); |
|
| 1369 |
#endif |
|
| 1370 |
env->psrs = (val & PSR_S)? 1 : 0; |
|
| 1371 |
env->psrps = (val & PSR_PS)? 1 : 0; |
|
| 1372 |
#if !defined (TARGET_SPARC64) |
|
| 1373 |
env->psret = (val & PSR_ET)? 1 : 0; |
|
| 1374 |
#endif |
|
| 1375 |
set_cwp(val & PSR_CWP); |
|
| 1376 |
env->cc_op = CC_OP_FLAGS; |
|
| 1377 |
} |
|
| 1378 |
|
|
| 1379 |
void cpu_put_psr(CPUState *env1, target_ulong val) |
|
| 1380 |
{
|
|
| 1381 |
CPUState *saved_env; |
|
| 1382 |
|
|
| 1383 |
saved_env = env; |
|
| 1384 |
env = env1; |
|
| 1385 |
put_psr(val); |
|
| 1386 |
env = saved_env; |
|
| 1387 |
} |
|
| 1388 |
|
|
| 1389 |
static int cwp_inc(int cwp) |
|
| 1390 |
{
|
|
| 1391 |
if (unlikely(cwp >= env->nwindows)) {
|
|
| 1392 |
cwp -= env->nwindows; |
|
| 1393 |
} |
|
| 1394 |
return cwp; |
|
| 1395 |
} |
|
| 1396 |
|
|
| 1397 |
int cpu_cwp_inc(CPUState *env1, int cwp) |
|
| 1398 |
{
|
|
| 1399 |
CPUState *saved_env; |
|
| 1400 |
target_ulong ret; |
|
| 1401 |
|
|
| 1402 |
saved_env = env; |
|
| 1403 |
env = env1; |
|
| 1404 |
ret = cwp_inc(cwp); |
|
| 1405 |
env = saved_env; |
|
| 1406 |
return ret; |
|
| 1407 |
} |
|
| 1408 |
|
|
| 1409 |
static int cwp_dec(int cwp) |
|
| 1410 |
{
|
|
| 1411 |
if (unlikely(cwp < 0)) {
|
|
| 1412 |
cwp += env->nwindows; |
|
| 1413 |
} |
|
| 1414 |
return cwp; |
|
| 1415 |
} |
|
| 1416 |
|
|
| 1417 |
int cpu_cwp_dec(CPUState *env1, int cwp) |
|
| 1418 |
{
|
|
| 1419 |
CPUState *saved_env; |
|
| 1420 |
target_ulong ret; |
|
| 1421 |
|
|
| 1422 |
saved_env = env; |
|
| 1423 |
env = env1; |
|
| 1424 |
ret = cwp_dec(cwp); |
|
| 1425 |
env = saved_env; |
|
| 1426 |
return ret; |
|
| 1427 |
} |
|
| 1428 |
|
|
| 1298 | 1429 |
#ifdef TARGET_SPARC64 |
| 1299 | 1430 |
GEN_FCMPS(fcmps_fcc1, float32, 22, 0); |
| 1300 | 1431 |
GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
| ... | ... | |
| 3016 | 3147 |
raise_exception(TT_ILL_INSN); |
| 3017 | 3148 |
|
| 3018 | 3149 |
env->psret = 1; |
| 3019 |
cwp = cpu_cwp_inc(env, env->cwp + 1) ;
|
|
| 3150 |
cwp = cwp_inc(env->cwp + 1) ;
|
|
| 3020 | 3151 |
if (env->wim & (1 << cwp)) {
|
| 3021 | 3152 |
raise_exception(TT_WIN_UNF); |
| 3022 | 3153 |
} |
| ... | ... | |
| 3236 | 3367 |
{
|
| 3237 | 3368 |
uint32_t cwp; |
| 3238 | 3369 |
|
| 3239 |
cwp = cpu_cwp_dec(env, env->cwp - 1);
|
|
| 3370 |
cwp = cwp_dec(env->cwp - 1);
|
|
| 3240 | 3371 |
if (env->wim & (1 << cwp)) {
|
| 3241 | 3372 |
raise_exception(TT_WIN_OVF); |
| 3242 | 3373 |
} |
| ... | ... | |
| 3247 | 3378 |
{
|
| 3248 | 3379 |
uint32_t cwp; |
| 3249 | 3380 |
|
| 3250 |
cwp = cpu_cwp_inc(env, env->cwp + 1);
|
|
| 3381 |
cwp = cwp_inc(env->cwp + 1);
|
|
| 3251 | 3382 |
if (env->wim & (1 << cwp)) {
|
| 3252 | 3383 |
raise_exception(TT_WIN_UNF); |
| 3253 | 3384 |
} |
| ... | ... | |
| 3256 | 3387 |
|
| 3257 | 3388 |
void helper_wrpsr(target_ulong new_psr) |
| 3258 | 3389 |
{
|
| 3259 |
if ((new_psr & PSR_CWP) >= env->nwindows) |
|
| 3390 |
if ((new_psr & PSR_CWP) >= env->nwindows) {
|
|
| 3260 | 3391 |
raise_exception(TT_ILL_INSN); |
| 3261 |
else |
|
| 3262 |
PUT_PSR(env, new_psr); |
|
| 3392 |
} else {
|
|
| 3393 |
cpu_put_psr(env, new_psr); |
|
| 3394 |
} |
|
| 3263 | 3395 |
} |
| 3264 | 3396 |
|
| 3265 | 3397 |
target_ulong helper_rdpsr(void) |
| 3266 | 3398 |
{
|
| 3267 |
return GET_PSR(env);
|
|
| 3399 |
return get_psr();
|
|
| 3268 | 3400 |
} |
| 3269 | 3401 |
|
| 3270 | 3402 |
#else |
| ... | ... | |
| 3274 | 3406 |
{
|
| 3275 | 3407 |
uint32_t cwp; |
| 3276 | 3408 |
|
| 3277 |
cwp = cpu_cwp_dec(env, env->cwp - 1);
|
|
| 3409 |
cwp = cwp_dec(env->cwp - 1);
|
|
| 3278 | 3410 |
if (env->cansave == 0) {
|
| 3279 | 3411 |
raise_exception(TT_SPILL | (env->otherwin != 0 ? |
| 3280 | 3412 |
(TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
| ... | ... | |
| 3295 | 3427 |
{
|
| 3296 | 3428 |
uint32_t cwp; |
| 3297 | 3429 |
|
| 3298 |
cwp = cpu_cwp_inc(env, env->cwp + 1);
|
|
| 3430 |
cwp = cwp_inc(env->cwp + 1);
|
|
| 3299 | 3431 |
if (env->canrestore == 0) {
|
| 3300 | 3432 |
raise_exception(TT_FILL | (env->otherwin != 0 ? |
| 3301 | 3433 |
(TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
| ... | ... | |
| 3336 | 3468 |
env->otherwin--; |
| 3337 | 3469 |
} |
| 3338 | 3470 |
|
| 3471 |
static target_ulong get_ccr(void) |
|
| 3472 |
{
|
|
| 3473 |
target_ulong psr; |
|
| 3474 |
|
|
| 3475 |
psr = get_psr(); |
|
| 3476 |
|
|
| 3477 |
return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20); |
|
| 3478 |
} |
|
| 3479 |
|
|
| 3480 |
target_ulong cpu_get_ccr(CPUState *env1) |
|
| 3481 |
{
|
|
| 3482 |
CPUState *saved_env; |
|
| 3483 |
target_ulong ret; |
|
| 3484 |
|
|
| 3485 |
saved_env = env; |
|
| 3486 |
env = env1; |
|
| 3487 |
ret = get_ccr(); |
|
| 3488 |
env = saved_env; |
|
| 3489 |
return ret; |
|
| 3490 |
} |
|
| 3491 |
|
|
| 3492 |
static void put_ccr(target_ulong val) |
|
| 3493 |
{
|
|
| 3494 |
target_ulong tmp = val; |
|
| 3495 |
|
|
| 3496 |
env->xcc = (tmp >> 4) << 20; |
|
| 3497 |
env->psr = (tmp & 0xf) << 20; |
|
| 3498 |
CC_OP = CC_OP_FLAGS; |
|
| 3499 |
} |
|
| 3500 |
|
|
| 3501 |
void cpu_put_ccr(CPUState *env1, target_ulong val) |
|
| 3502 |
{
|
|
| 3503 |
CPUState *saved_env; |
|
| 3504 |
|
|
| 3505 |
saved_env = env; |
|
| 3506 |
env = env1; |
|
| 3507 |
put_ccr(val); |
|
| 3508 |
env = saved_env; |
|
| 3509 |
} |
|
| 3510 |
|
|
| 3511 |
static target_ulong get_cwp64(void) |
|
| 3512 |
{
|
|
| 3513 |
return env->nwindows - 1 - env->cwp; |
|
| 3514 |
} |
|
| 3515 |
|
|
| 3516 |
target_ulong cpu_get_cwp64(CPUState *env1) |
|
| 3517 |
{
|
|
| 3518 |
CPUState *saved_env; |
|
| 3519 |
target_ulong ret; |
|
| 3520 |
|
|
| 3521 |
saved_env = env; |
|
| 3522 |
env = env1; |
|
| 3523 |
ret = get_cwp64(); |
|
| 3524 |
env = saved_env; |
|
| 3525 |
return ret; |
|
| 3526 |
} |
|
| 3527 |
|
|
| 3528 |
static void put_cwp64(int cwp) |
|
| 3529 |
{
|
|
| 3530 |
if (unlikely(cwp >= env->nwindows || cwp < 0)) {
|
|
| 3531 |
cwp %= env->nwindows; |
|
| 3532 |
} |
|
| 3533 |
set_cwp(env->nwindows - 1 - cwp); |
|
| 3534 |
} |
|
| 3535 |
|
|
| 3536 |
void cpu_put_cwp64(CPUState *env1, int cwp) |
|
| 3537 |
{
|
|
| 3538 |
CPUState *saved_env; |
|
| 3539 |
|
|
| 3540 |
saved_env = env; |
|
| 3541 |
env = env1; |
|
| 3542 |
put_cwp64(cwp); |
|
| 3543 |
env = saved_env; |
|
| 3544 |
} |
|
| 3545 |
|
|
| 3339 | 3546 |
target_ulong helper_rdccr(void) |
| 3340 | 3547 |
{
|
| 3341 |
return GET_CCR(env);
|
|
| 3548 |
return get_ccr();
|
|
| 3342 | 3549 |
} |
| 3343 | 3550 |
|
| 3344 | 3551 |
void helper_wrccr(target_ulong new_ccr) |
| 3345 | 3552 |
{
|
| 3346 |
PUT_CCR(env, new_ccr);
|
|
| 3553 |
put_ccr(new_ccr);
|
|
| 3347 | 3554 |
} |
| 3348 | 3555 |
|
| 3349 | 3556 |
// CWP handling is reversed in V9, but we still use the V8 register |
| 3350 | 3557 |
// order. |
| 3351 | 3558 |
target_ulong helper_rdcwp(void) |
| 3352 | 3559 |
{
|
| 3353 |
return GET_CWP64(env);
|
|
| 3560 |
return get_cwp64();
|
|
| 3354 | 3561 |
} |
| 3355 | 3562 |
|
| 3356 | 3563 |
void helper_wrcwp(target_ulong new_cwp) |
| 3357 | 3564 |
{
|
| 3358 |
PUT_CWP64(env, new_cwp);
|
|
| 3565 |
put_cwp64(new_cwp);
|
|
| 3359 | 3566 |
} |
| 3360 | 3567 |
|
| 3361 | 3568 |
// This function uses non-native bit order |
| ... | ... | |
| 3475 | 3682 |
|
| 3476 | 3683 |
env->pc = tsptr->tnpc; |
| 3477 | 3684 |
env->npc = tsptr->tnpc + 4; |
| 3478 |
PUT_CCR(env, tsptr->tstate >> 32);
|
|
| 3685 |
put_ccr(tsptr->tstate >> 32);
|
|
| 3479 | 3686 |
env->asi = (tsptr->tstate >> 24) & 0xff; |
| 3480 | 3687 |
change_pstate((tsptr->tstate >> 8) & 0xf3f); |
| 3481 |
PUT_CWP64(env, tsptr->tstate & 0xff);
|
|
| 3688 |
put_cwp64(tsptr->tstate & 0xff);
|
|
| 3482 | 3689 |
env->tl--; |
| 3483 | 3690 |
|
| 3484 | 3691 |
DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
|
| ... | ... | |
| 3496 | 3703 |
|
| 3497 | 3704 |
env->pc = tsptr->tpc; |
| 3498 | 3705 |
env->npc = tsptr->tnpc; |
| 3499 |
PUT_CCR(env, tsptr->tstate >> 32);
|
|
| 3706 |
put_ccr(tsptr->tstate >> 32);
|
|
| 3500 | 3707 |
env->asi = (tsptr->tstate >> 24) & 0xff; |
| 3501 | 3708 |
change_pstate((tsptr->tstate >> 8) & 0xf3f); |
| 3502 |
PUT_CWP64(env, tsptr->tstate & 0xff);
|
|
| 3709 |
put_cwp64(tsptr->tstate & 0xff);
|
|
| 3503 | 3710 |
env->tl--; |
| 3504 | 3711 |
|
| 3505 | 3712 |
DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
|
| ... | ... | |
| 3650 | 3857 |
} |
| 3651 | 3858 |
tsptr = cpu_tsptr(env); |
| 3652 | 3859 |
|
| 3653 |
tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
|
|
| 3860 |
tsptr->tstate = (get_ccr() << 32) |
|
|
| 3654 | 3861 |
((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
| 3655 |
GET_CWP64(env);
|
|
| 3862 |
get_cwp64();
|
|
| 3656 | 3863 |
tsptr->tpc = env->pc; |
| 3657 | 3864 |
tsptr->tnpc = env->npc; |
| 3658 | 3865 |
tsptr->tt = intno; |
| ... | ... | |
| 3673 | 3880 |
break; |
| 3674 | 3881 |
} |
| 3675 | 3882 |
|
| 3676 |
if (intno == TT_CLRWIN) |
|
| 3677 |
cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); |
|
| 3678 |
else if ((intno & 0x1c0) == TT_SPILL) |
|
| 3679 |
cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); |
|
| 3680 |
else if ((intno & 0x1c0) == TT_FILL) |
|
| 3681 |
cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); |
|
| 3883 |
if (intno == TT_CLRWIN) {
|
|
| 3884 |
set_cwp(cwp_dec(env->cwp - 1)); |
|
| 3885 |
} else if ((intno & 0x1c0) == TT_SPILL) {
|
|
| 3886 |
set_cwp(cwp_dec(env->cwp - env->cansave - 2)); |
|
| 3887 |
} else if ((intno & 0x1c0) == TT_FILL) {
|
|
| 3888 |
set_cwp(cwp_inc(env->cwp + 1)); |
|
| 3889 |
} |
|
| 3682 | 3890 |
env->tbr &= ~0x7fffULL; |
| 3683 | 3891 |
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
| 3684 | 3892 |
env->pc = env->tbr; |
| ... | ... | |
| 3769 | 3977 |
} |
| 3770 | 3978 |
#endif |
| 3771 | 3979 |
env->psret = 0; |
| 3772 |
cwp = cpu_cwp_dec(env, env->cwp - 1);
|
|
| 3773 |
cpu_set_cwp(env, cwp);
|
|
| 3980 |
cwp = cwp_dec(env->cwp - 1);
|
|
| 3981 |
set_cwp(cwp);
|
|
| 3774 | 3982 |
env->regwptr[9] = env->pc; |
| 3775 | 3983 |
env->regwptr[10] = env->npc; |
| 3776 | 3984 |
env->psrps = env->psrs; |
Also available in: Unified diff