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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | d4e8164f | bellard | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | d4e8164f | bellard | #define GEN_FLAG_CODE32_SHIFT 0 |
22 | d4e8164f | bellard | #define GEN_FLAG_ADDSEG_SHIFT 1 |
23 | d4e8164f | bellard | #define GEN_FLAG_SS32_SHIFT 2 |
24 | d4e8164f | bellard | #define GEN_FLAG_VM_SHIFT 3 |
25 | d4e8164f | bellard | #define GEN_FLAG_ST_SHIFT 4 |
26 | cf25629d | bellard | #define GEN_FLAG_TF_SHIFT 8 /* same position as eflags */ |
27 | cf25629d | bellard | #define GEN_FLAG_CPL_SHIFT 9 |
28 | cf25629d | bellard | #define GEN_FLAG_IOPL_SHIFT 12 /* same position as eflags */ |
29 | d4e8164f | bellard | |
30 | d4e8164f | bellard | struct TranslationBlock;
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31 | d4e8164f | bellard | int cpu_x86_gen_code(uint8_t *gen_code_buf, int max_code_size, |
32 | d4e8164f | bellard | int *gen_code_size_ptr,
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33 | d4e8164f | bellard | uint8_t *pc_start, uint8_t *cs_base, int flags,
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34 | d4e8164f | bellard | int *code_size_ptr, struct TranslationBlock *tb); |
35 | d4e8164f | bellard | void cpu_x86_tblocks_init(void); |
36 | d4e8164f | bellard | void page_init(void); |
37 | d4e8164f | bellard | int page_unprotect(unsigned long address); |
38 | d4e8164f | bellard | |
39 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
40 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
41 | d4e8164f | bellard | |
42 | d4e8164f | bellard | #define CODE_GEN_HASH_BITS 15 |
43 | d4e8164f | bellard | #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) |
44 | d4e8164f | bellard | |
45 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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46 | d4e8164f | bellard | #define CODE_GEN_BUFFER_SIZE (2048 * 1024) |
47 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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48 | d4e8164f | bellard | |
49 | d4e8164f | bellard | #if defined(__powerpc__)
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50 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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51 | d4e8164f | bellard | #endif
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52 | d4e8164f | bellard | |
53 | d4e8164f | bellard | typedef struct TranslationBlock { |
54 | d4e8164f | bellard | unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
55 | d4e8164f | bellard | unsigned long cs_base; /* CS base for this block */ |
56 | d4e8164f | bellard | unsigned int flags; /* flags defining in which context the code was generated */ |
57 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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58 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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59 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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60 | d4e8164f | bellard | struct TranslationBlock *hash_next; /* next matching block */ |
61 | d4e8164f | bellard | struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */ |
62 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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63 | d4e8164f | bellard | the code of this one. */
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64 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
65 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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66 | d4e8164f | bellard | uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ |
67 | d4e8164f | bellard | #else
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68 | d4e8164f | bellard | uint8_t *tb_next[2]; /* address of jump generated code */ |
69 | d4e8164f | bellard | #endif
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70 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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71 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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72 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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73 | d4e8164f | bellard | jmp_first */
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74 | d4e8164f | bellard | struct TranslationBlock *jmp_next[2]; |
75 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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76 | d4e8164f | bellard | } TranslationBlock; |
77 | d4e8164f | bellard | |
78 | d4e8164f | bellard | static inline unsigned int tb_hash_func(unsigned long pc) |
79 | d4e8164f | bellard | { |
80 | d4e8164f | bellard | return pc & (CODE_GEN_HASH_SIZE - 1); |
81 | d4e8164f | bellard | } |
82 | d4e8164f | bellard | |
83 | d4e8164f | bellard | TranslationBlock *tb_alloc(unsigned long pc); |
84 | d4e8164f | bellard | void tb_flush(void); |
85 | d4e8164f | bellard | void tb_link(TranslationBlock *tb);
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86 | d4e8164f | bellard | |
87 | d4e8164f | bellard | extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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88 | d4e8164f | bellard | |
89 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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90 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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91 | d4e8164f | bellard | |
92 | d4e8164f | bellard | /* find a translation block in the translation cache. If not found,
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93 | d4e8164f | bellard | return NULL and the pointer to the last element of the list in pptb */
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94 | d4e8164f | bellard | static inline TranslationBlock *tb_find(TranslationBlock ***pptb, |
95 | d4e8164f | bellard | unsigned long pc, |
96 | d4e8164f | bellard | unsigned long cs_base, |
97 | d4e8164f | bellard | unsigned int flags) |
98 | d4e8164f | bellard | { |
99 | d4e8164f | bellard | TranslationBlock **ptb, *tb; |
100 | d4e8164f | bellard | unsigned int h; |
101 | d4e8164f | bellard | |
102 | d4e8164f | bellard | h = tb_hash_func(pc); |
103 | d4e8164f | bellard | ptb = &tb_hash[h]; |
104 | d4e8164f | bellard | for(;;) {
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105 | d4e8164f | bellard | tb = *ptb; |
106 | d4e8164f | bellard | if (!tb)
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107 | d4e8164f | bellard | break;
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108 | d4e8164f | bellard | if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
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109 | d4e8164f | bellard | return tb;
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110 | d4e8164f | bellard | ptb = &tb->hash_next; |
111 | d4e8164f | bellard | } |
112 | d4e8164f | bellard | *pptb = ptb; |
113 | d4e8164f | bellard | return NULL; |
114 | d4e8164f | bellard | } |
115 | d4e8164f | bellard | |
116 | d4e8164f | bellard | #if defined(__powerpc__)
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117 | d4e8164f | bellard | |
118 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
119 | d4e8164f | bellard | int n, unsigned long addr) |
120 | d4e8164f | bellard | { |
121 | d4e8164f | bellard | uint32_t val, *ptr; |
122 | d4e8164f | bellard | unsigned long offset; |
123 | d4e8164f | bellard | |
124 | d4e8164f | bellard | offset = (unsigned long)(tb->tc_ptr + tb->tb_jmp_offset[n]); |
125 | d4e8164f | bellard | |
126 | d4e8164f | bellard | /* patch the branch destination */
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127 | d4e8164f | bellard | ptr = (uint32_t *)offset; |
128 | d4e8164f | bellard | val = *ptr; |
129 | d4e8164f | bellard | val = (val & ~0x03fffffc) | ((addr - offset) & 0x03fffffc); |
130 | d4e8164f | bellard | *ptr = val; |
131 | d4e8164f | bellard | /* flush icache */
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132 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
133 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
134 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
135 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
136 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
137 | d4e8164f | bellard | } |
138 | d4e8164f | bellard | |
139 | d4e8164f | bellard | #else
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140 | d4e8164f | bellard | |
141 | d4e8164f | bellard | /* set the jump target */
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142 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
143 | d4e8164f | bellard | int n, unsigned long addr) |
144 | d4e8164f | bellard | { |
145 | d4e8164f | bellard | tb->tb_next[n] = (void *)addr;
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146 | d4e8164f | bellard | } |
147 | d4e8164f | bellard | |
148 | d4e8164f | bellard | #endif
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149 | d4e8164f | bellard | |
150 | d4e8164f | bellard | static inline void tb_add_jump(TranslationBlock *tb, int n, |
151 | d4e8164f | bellard | TranslationBlock *tb_next) |
152 | d4e8164f | bellard | { |
153 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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154 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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155 | cf25629d | bellard | /* patch the native jump address */
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156 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
157 | cf25629d | bellard | |
158 | cf25629d | bellard | /* add in TB jmp circular list */
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159 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
160 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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161 | cf25629d | bellard | } |
162 | d4e8164f | bellard | } |
163 | d4e8164f | bellard | |
164 | d4e8164f | bellard | #ifndef offsetof
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165 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
166 | d4e8164f | bellard | #endif
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167 | d4e8164f | bellard | |
168 | d4e8164f | bellard | #ifdef __powerpc__
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169 | d4e8164f | bellard | static inline int testandset (int *p) |
170 | d4e8164f | bellard | { |
171 | d4e8164f | bellard | int ret;
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172 | d4e8164f | bellard | __asm__ __volatile__ ( |
173 | d4e8164f | bellard | "0: lwarx %0,0,%1 ;"
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174 | d4e8164f | bellard | " xor. %0,%3,%0;"
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175 | d4e8164f | bellard | " bne 1f;"
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176 | d4e8164f | bellard | " stwcx. %2,0,%1;"
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177 | d4e8164f | bellard | " bne- 0b;"
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178 | d4e8164f | bellard | "1: "
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179 | d4e8164f | bellard | : "=&r" (ret)
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180 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
181 | d4e8164f | bellard | : "cr0", "memory"); |
182 | d4e8164f | bellard | return ret;
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183 | d4e8164f | bellard | } |
184 | d4e8164f | bellard | #endif
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185 | d4e8164f | bellard | |
186 | d4e8164f | bellard | #ifdef __i386__
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187 | d4e8164f | bellard | static inline int testandset (int *p) |
188 | d4e8164f | bellard | { |
189 | d4e8164f | bellard | char ret;
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190 | d4e8164f | bellard | long int readval; |
191 | d4e8164f | bellard | |
192 | d4e8164f | bellard | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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193 | d4e8164f | bellard | : "=q" (ret), "=m" (*p), "=a" (readval) |
194 | d4e8164f | bellard | : "r" (1), "m" (*p), "a" (0) |
195 | d4e8164f | bellard | : "memory");
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196 | d4e8164f | bellard | return ret;
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197 | d4e8164f | bellard | } |
198 | d4e8164f | bellard | #endif
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199 | d4e8164f | bellard | |
200 | d4e8164f | bellard | #ifdef __s390__
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201 | d4e8164f | bellard | static inline int testandset (int *p) |
202 | d4e8164f | bellard | { |
203 | d4e8164f | bellard | int ret;
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204 | d4e8164f | bellard | |
205 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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206 | d4e8164f | bellard | " jl 0b"
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207 | d4e8164f | bellard | : "=&d" (ret)
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208 | d4e8164f | bellard | : "r" (1), "a" (p), "0" (*p) |
209 | d4e8164f | bellard | : "cc", "memory" ); |
210 | d4e8164f | bellard | return ret;
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211 | d4e8164f | bellard | } |
212 | d4e8164f | bellard | #endif
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213 | d4e8164f | bellard | |
214 | d4e8164f | bellard | #ifdef __alpha__
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215 | d4e8164f | bellard | int testandset (int *p) |
216 | d4e8164f | bellard | { |
217 | d4e8164f | bellard | int ret;
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218 | d4e8164f | bellard | unsigned long one; |
219 | d4e8164f | bellard | |
220 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
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221 | d4e8164f | bellard | " ldl_l %0,%1\n"
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222 | d4e8164f | bellard | " stl_c %2,%1\n"
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223 | d4e8164f | bellard | " beq %2,1f\n"
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224 | d4e8164f | bellard | ".subsection 2\n"
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225 | d4e8164f | bellard | "1: br 0b\n"
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226 | d4e8164f | bellard | ".previous"
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227 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
228 | d4e8164f | bellard | : "m" (*p));
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229 | d4e8164f | bellard | return ret;
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230 | d4e8164f | bellard | } |
231 | d4e8164f | bellard | #endif
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232 | d4e8164f | bellard | |
233 | d4e8164f | bellard | #ifdef __sparc__
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234 | d4e8164f | bellard | static inline int testandset (int *p) |
235 | d4e8164f | bellard | { |
236 | d4e8164f | bellard | int ret;
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237 | d4e8164f | bellard | |
238 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
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239 | d4e8164f | bellard | : "=r" (ret)
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240 | d4e8164f | bellard | : "r" (p)
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241 | d4e8164f | bellard | : "memory");
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242 | d4e8164f | bellard | |
243 | d4e8164f | bellard | return (ret ? 1 : 0); |
244 | d4e8164f | bellard | } |
245 | d4e8164f | bellard | #endif
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246 | d4e8164f | bellard | |
247 | d4e8164f | bellard | typedef int spinlock_t; |
248 | d4e8164f | bellard | |
249 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
250 | d4e8164f | bellard | |
251 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
252 | d4e8164f | bellard | { |
253 | d4e8164f | bellard | while (testandset(lock));
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254 | d4e8164f | bellard | } |
255 | d4e8164f | bellard | |
256 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
257 | d4e8164f | bellard | { |
258 | d4e8164f | bellard | *lock = 0;
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259 | d4e8164f | bellard | } |
260 | d4e8164f | bellard | |
261 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
262 | d4e8164f | bellard | { |
263 | d4e8164f | bellard | return !testandset(lock);
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264 | d4e8164f | bellard | } |
265 | d4e8164f | bellard | |
266 | d4e8164f | bellard | extern spinlock_t tb_lock;
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