Revision 5ae93306 hw/highbank.c

b/hw/highbank.c
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/* Board init.  */
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static void highbank_cpu_reset(void *opaque)
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{
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    CPUState *env = opaque;
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    CPUARMState *env = opaque;
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    env->cp15.c15_config_base_address = GIC_BASE_ADDR;


  		





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}


  		





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static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)


  		





  
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static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)


  		





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{


  		





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    int n;


  		





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    uint32_t smpboot[] = {


  		





  ......




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    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);


  		





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}


  		





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static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info)


  		





  
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static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info)


  		





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{


  		





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    switch (info->nb_cpus) {


  		





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    case 4:


  		





  ......




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                     const char *kernel_filename, const char *kernel_cmdline,


  		





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                     const char *initrd_filename, const char *cpu_model)


  		





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{


  		





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    CPUState *env = NULL;


  		





  
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    CPUARMState *env = NULL;


  		





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    DeviceState *dev;


  		





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    SysBusDevice *busdev;


  		





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    qemu_irq *irqp;


  		












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