root / tcg / ppc / tcg-target.c @ 5b1c985b
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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static uint8_t *tb_ret_addr;
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#if defined _CALL_DARWIN || defined __APPLE__
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#define TCG_TARGET_CALL_DARWIN
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#endif
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#ifdef TCG_TARGET_CALL_DARWIN
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#define LINKAGE_AREA_SIZE 24 |
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#define LR_OFFSET 8 |
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#elif defined _CALL_AIX
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#define LINKAGE_AREA_SIZE 52 |
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#define LR_OFFSET 8 |
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#else
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#define LINKAGE_AREA_SIZE 8 |
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#define LR_OFFSET 4 |
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#endif
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#ifndef GUEST_BASE
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#define GUEST_BASE 0 |
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#endif
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|
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#ifdef CONFIG_USE_GUEST_BASE
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#define TCG_GUEST_BASE_REG 30 |
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#else
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#define TCG_GUEST_BASE_REG 0 |
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#endif
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|
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"r0",
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"r1",
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"r2",
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"r3",
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"r4",
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"r5",
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"r6",
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"r7",
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"r8",
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"r9",
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"r10",
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"r11",
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"r12",
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"r13",
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"r14",
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"r15",
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"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
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"r23",
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"r24",
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"r25",
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"r26",
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"r27",
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"r28",
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"r29",
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"r30",
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"r31"
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}; |
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#endif
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R16, |
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TCG_REG_R17, |
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TCG_REG_R18, |
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TCG_REG_R19, |
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TCG_REG_R20, |
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TCG_REG_R21, |
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TCG_REG_R22, |
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TCG_REG_R23, |
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TCG_REG_R28, |
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TCG_REG_R29, |
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TCG_REG_R30, |
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TCG_REG_R31, |
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#ifdef TCG_TARGET_CALL_DARWIN
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TCG_REG_R2, |
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#endif
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TCG_REG_R3, |
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TCG_REG_R4, |
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TCG_REG_R5, |
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TCG_REG_R6, |
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TCG_REG_R7, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10, |
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#ifndef TCG_TARGET_CALL_DARWIN
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TCG_REG_R11, |
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#endif
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TCG_REG_R12, |
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#ifndef _CALL_SYSV
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TCG_REG_R13, |
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#endif
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TCG_REG_R24, |
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TCG_REG_R25, |
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TCG_REG_R26, |
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TCG_REG_R27 |
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}; |
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|
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static const int tcg_target_call_iarg_regs[] = { |
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TCG_REG_R3, |
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TCG_REG_R4, |
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TCG_REG_R5, |
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TCG_REG_R6, |
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TCG_REG_R7, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10 |
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}; |
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|
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static const int tcg_target_call_oarg_regs[2] = { |
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TCG_REG_R3, |
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TCG_REG_R4 |
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}; |
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|
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static const int tcg_target_callee_save_regs[] = { |
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#ifdef TCG_TARGET_CALL_DARWIN
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TCG_REG_R11, |
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TCG_REG_R13, |
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#endif
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#ifdef _CALL_AIX
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TCG_REG_R13, |
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#endif
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R16, |
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TCG_REG_R17, |
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TCG_REG_R18, |
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TCG_REG_R19, |
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TCG_REG_R20, |
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TCG_REG_R21, |
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TCG_REG_R22, |
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TCG_REG_R23, |
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TCG_REG_R24, |
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TCG_REG_R25, |
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TCG_REG_R26, |
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TCG_REG_R27, /* currently used for the global env */
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TCG_REG_R28, |
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TCG_REG_R29, |
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TCG_REG_R30, |
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TCG_REG_R31 |
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}; |
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|
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static uint32_t reloc_pc24_val (void *pc, tcg_target_long target) |
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{
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tcg_target_long disp; |
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disp = target - (tcg_target_long) pc; |
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if ((disp << 6) >> 6 != disp) |
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tcg_abort (); |
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return disp & 0x3fffffc; |
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} |
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|
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static void reloc_pc24 (void *pc, tcg_target_long target) |
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{
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*(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
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| reloc_pc24_val (pc, target); |
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} |
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static uint16_t reloc_pc14_val (void *pc, tcg_target_long target) |
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{
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tcg_target_long disp; |
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disp = target - (tcg_target_long) pc; |
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if (disp != (int16_t) disp)
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tcg_abort (); |
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return disp & 0xfffc; |
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} |
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static void reloc_pc14 (void *pc, tcg_target_long target) |
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{
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*(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
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| reloc_pc14_val (pc, target); |
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} |
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static void patch_reloc(uint8_t *code_ptr, int type, |
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intptr_t value, intptr_t addend) |
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{
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value += addend; |
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switch (type) {
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case R_PPC_REL14:
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reloc_pc14 (code_ptr, value); |
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break;
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case R_PPC_REL24:
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reloc_pc24 (code_ptr, value); |
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break;
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default:
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tcg_abort(); |
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} |
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} |
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|
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
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{
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const char *ct_str; |
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ct_str = *pct_str; |
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switch (ct_str[0]) { |
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case 'A': case 'B': case 'C': case 'D': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A'); |
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break;
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case 'r': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
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break;
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#ifdef CONFIG_SOFTMMU
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case 'L': /* qemu_ld constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); |
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#if TARGET_LONG_BITS == 64 |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); |
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#ifdef TCG_TARGET_CALL_ALIGN_ARGS
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7); |
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#endif
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#endif
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break;
|
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case 'K': /* qemu_st[8..32] constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); |
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#if TARGET_LONG_BITS == 64 |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7); |
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#ifdef TCG_TARGET_CALL_ALIGN_ARGS
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8); |
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#endif
|
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#endif
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break;
|
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case 'M': /* qemu_st64 constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8); |
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#ifdef TCG_TARGET_CALL_ALIGN_ARGS
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9); |
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#endif
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break;
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#else
|
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case 'L': |
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case 'K': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
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break;
|
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case 'M': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); |
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break;
|
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#endif
|
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default:
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return -1; |
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} |
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ct_str++; |
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*pct_str = ct_str; |
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return 0; |
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} |
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|
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/* test if a constant matches the constraint */
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static int tcg_target_const_match(tcg_target_long val, |
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const TCGArgConstraint *arg_ct)
|
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{
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int ct;
|
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|
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ct = arg_ct->ct; |
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if (ct & TCG_CT_CONST)
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return 1; |
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return 0; |
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} |
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|
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#define OPCD(opc) ((opc)<<26) |
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#define XO31(opc) (OPCD(31)|((opc)<<1)) |
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#define XO19(opc) (OPCD(19)|((opc)<<1)) |
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|
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#define B OPCD(18) |
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#define BC OPCD(16) |
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#define LBZ OPCD(34) |
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#define LHZ OPCD(40) |
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#define LHA OPCD(42) |
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#define LWZ OPCD(32) |
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#define STB OPCD(38) |
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#define STH OPCD(44) |
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#define STW OPCD(36) |
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|
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#define ADDIC OPCD(12) |
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#define ADDI OPCD(14) |
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#define ADDIS OPCD(15) |
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#define ORI OPCD(24) |
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#define ORIS OPCD(25) |
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#define XORI OPCD(26) |
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#define XORIS OPCD(27) |
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#define ANDI OPCD(28) |
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#define ANDIS OPCD(29) |
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#define MULLI OPCD( 7) |
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#define CMPLI OPCD(10) |
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#define CMPI OPCD(11) |
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#define SUBFIC OPCD( 8) |
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|
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#define LWZU OPCD(33) |
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#define STWU OPCD(37) |
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|
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#define RLWIMI OPCD(20) |
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#define RLWINM OPCD(21) |
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#define RLWNM OPCD(23) |
| 344 |
|
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#define BCLR XO19( 16) |
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#define BCCTR XO19(528) |
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#define CRAND XO19(257) |
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#define CRANDC XO19(129) |
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#define CRNAND XO19(225) |
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#define CROR XO19(449) |
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#define CRNOR XO19( 33) |
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|
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#define EXTSB XO31(954) |
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#define EXTSH XO31(922) |
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#define ADD XO31(266) |
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#define ADDE XO31(138) |
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#define ADDC XO31( 10) |
| 358 |
#define AND XO31( 28) |
| 359 |
#define SUBF XO31( 40) |
| 360 |
#define SUBFC XO31( 8) |
| 361 |
#define SUBFE XO31(136) |
| 362 |
#define OR XO31(444) |
| 363 |
#define XOR XO31(316) |
| 364 |
#define MULLW XO31(235) |
| 365 |
#define MULHWU XO31( 11) |
| 366 |
#define DIVW XO31(491) |
| 367 |
#define DIVWU XO31(459) |
| 368 |
#define CMP XO31( 0) |
| 369 |
#define CMPL XO31( 32) |
| 370 |
#define LHBRX XO31(790) |
| 371 |
#define LWBRX XO31(534) |
| 372 |
#define STHBRX XO31(918) |
| 373 |
#define STWBRX XO31(662) |
| 374 |
#define MFSPR XO31(339) |
| 375 |
#define MTSPR XO31(467) |
| 376 |
#define SRAWI XO31(824) |
| 377 |
#define NEG XO31(104) |
| 378 |
#define MFCR XO31( 19) |
| 379 |
#define CNTLZW XO31( 26) |
| 380 |
#define NOR XO31(124) |
| 381 |
#define ANDC XO31( 60) |
| 382 |
#define ORC XO31(412) |
| 383 |
#define EQV XO31(284) |
| 384 |
#define NAND XO31(476) |
| 385 |
#define ISEL XO31( 15) |
| 386 |
|
| 387 |
#define LBZX XO31( 87) |
| 388 |
#define LHZX XO31(279) |
| 389 |
#define LHAX XO31(343) |
| 390 |
#define LWZX XO31( 23) |
| 391 |
#define STBX XO31(215) |
| 392 |
#define STHX XO31(407) |
| 393 |
#define STWX XO31(151) |
| 394 |
|
| 395 |
#define SPR(a,b) ((((a)<<5)|(b))<<11) |
| 396 |
#define LR SPR(8, 0) |
| 397 |
#define CTR SPR(9, 0) |
| 398 |
|
| 399 |
#define SLW XO31( 24) |
| 400 |
#define SRW XO31(536) |
| 401 |
#define SRAW XO31(792) |
| 402 |
|
| 403 |
#define TW XO31(4) |
| 404 |
#define TRAP (TW | TO (31)) |
| 405 |
|
| 406 |
#define RT(r) ((r)<<21) |
| 407 |
#define RS(r) ((r)<<21) |
| 408 |
#define RA(r) ((r)<<16) |
| 409 |
#define RB(r) ((r)<<11) |
| 410 |
#define TO(t) ((t)<<21) |
| 411 |
#define SH(s) ((s)<<11) |
| 412 |
#define MB(b) ((b)<<6) |
| 413 |
#define ME(e) ((e)<<1) |
| 414 |
#define BO(o) ((o)<<21) |
| 415 |
|
| 416 |
#define LK 1 |
| 417 |
|
| 418 |
#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
|
| 419 |
#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
|
| 420 |
|
| 421 |
#define BF(n) ((n)<<23) |
| 422 |
#define BI(n, c) (((c)+((n)*4))<<16) |
| 423 |
#define BT(n, c) (((c)+((n)*4))<<21) |
| 424 |
#define BA(n, c) (((c)+((n)*4))<<16) |
| 425 |
#define BB(n, c) (((c)+((n)*4))<<11) |
| 426 |
|
| 427 |
#define BO_COND_TRUE BO (12) |
| 428 |
#define BO_COND_FALSE BO (4) |
| 429 |
#define BO_ALWAYS BO (20) |
| 430 |
|
| 431 |
enum {
|
| 432 |
CR_LT, |
| 433 |
CR_GT, |
| 434 |
CR_EQ, |
| 435 |
CR_SO |
| 436 |
}; |
| 437 |
|
| 438 |
static const uint32_t tcg_to_bc[] = { |
| 439 |
[TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
|
| 440 |
[TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
|
| 441 |
[TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
|
| 442 |
[TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
|
| 443 |
[TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
|
| 444 |
[TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
|
| 445 |
[TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
|
| 446 |
[TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
|
| 447 |
[TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
|
| 448 |
[TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
|
| 449 |
}; |
| 450 |
|
| 451 |
static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) |
| 452 |
{
|
| 453 |
if (ret != arg) {
|
| 454 |
tcg_out32(s, OR | SAB(arg, ret, arg)); |
| 455 |
} |
| 456 |
} |
| 457 |
|
| 458 |
static void tcg_out_movi(TCGContext *s, TCGType type, |
| 459 |
TCGReg ret, tcg_target_long arg) |
| 460 |
{
|
| 461 |
if (arg == (int16_t) arg)
|
| 462 |
tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff)); |
| 463 |
else {
|
| 464 |
tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff)); |
| 465 |
if (arg & 0xffff) |
| 466 |
tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
|
| 467 |
} |
| 468 |
} |
| 469 |
|
| 470 |
static void tcg_out_ldst (TCGContext *s, int ret, int addr, |
| 471 |
int offset, int op1, int op2) |
| 472 |
{
|
| 473 |
if (offset == (int16_t) offset)
|
| 474 |
tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
|
| 475 |
else {
|
| 476 |
tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
|
| 477 |
tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
|
| 478 |
} |
| 479 |
} |
| 480 |
|
| 481 |
static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target) |
| 482 |
{
|
| 483 |
tcg_target_long disp; |
| 484 |
|
| 485 |
disp = target - (tcg_target_long) s->code_ptr; |
| 486 |
if ((disp << 6) >> 6 == disp) |
| 487 |
tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
|
| 488 |
else {
|
| 489 |
tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
|
| 490 |
tcg_out32 (s, MTSPR | RS (0) | CTR);
|
| 491 |
tcg_out32 (s, BCCTR | BO_ALWAYS | mask); |
| 492 |
} |
| 493 |
} |
| 494 |
|
| 495 |
static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg, |
| 496 |
int lk)
|
| 497 |
{
|
| 498 |
#ifdef _CALL_AIX
|
| 499 |
int reg;
|
| 500 |
|
| 501 |
if (const_arg) {
|
| 502 |
reg = 2;
|
| 503 |
tcg_out_movi (s, TCG_TYPE_I32, reg, arg); |
| 504 |
} |
| 505 |
else reg = arg;
|
| 506 |
|
| 507 |
tcg_out32 (s, LWZ | RT (0) | RA (reg));
|
| 508 |
tcg_out32 (s, MTSPR | RA (0) | CTR);
|
| 509 |
tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4); |
| 510 |
tcg_out32 (s, BCCTR | BO_ALWAYS | lk); |
| 511 |
#else
|
| 512 |
if (const_arg) {
|
| 513 |
tcg_out_b (s, lk, arg); |
| 514 |
} |
| 515 |
else {
|
| 516 |
tcg_out32 (s, MTSPR | RS (arg) | LR); |
| 517 |
tcg_out32 (s, BCLR | BO_ALWAYS | lk); |
| 518 |
} |
| 519 |
#endif
|
| 520 |
} |
| 521 |
|
| 522 |
#if defined(CONFIG_SOFTMMU)
|
| 523 |
|
| 524 |
static void add_qemu_ldst_label (TCGContext *s, |
| 525 |
int is_ld,
|
| 526 |
int opc,
|
| 527 |
int data_reg,
|
| 528 |
int data_reg2,
|
| 529 |
int addrlo_reg,
|
| 530 |
int addrhi_reg,
|
| 531 |
int mem_index,
|
| 532 |
uint8_t *raddr, |
| 533 |
uint8_t *label_ptr) |
| 534 |
{
|
| 535 |
int idx;
|
| 536 |
TCGLabelQemuLdst *label; |
| 537 |
|
| 538 |
if (s->nb_qemu_ldst_labels >= TCG_MAX_QEMU_LDST) {
|
| 539 |
tcg_abort(); |
| 540 |
} |
| 541 |
|
| 542 |
idx = s->nb_qemu_ldst_labels++; |
| 543 |
label = (TCGLabelQemuLdst *)&s->qemu_ldst_labels[idx]; |
| 544 |
label->is_ld = is_ld; |
| 545 |
label->opc = opc; |
| 546 |
label->datalo_reg = data_reg; |
| 547 |
label->datahi_reg = data_reg2; |
| 548 |
label->addrlo_reg = addrlo_reg; |
| 549 |
label->addrhi_reg = addrhi_reg; |
| 550 |
label->mem_index = mem_index; |
| 551 |
label->raddr = raddr; |
| 552 |
label->label_ptr[0] = label_ptr;
|
| 553 |
} |
| 554 |
|
| 555 |
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
|
| 556 |
* int mmu_idx, uintptr_t ra)
|
| 557 |
*/
|
| 558 |
static const void * const qemu_ld_helpers[4] = { |
| 559 |
helper_ret_ldub_mmu, |
| 560 |
helper_ret_lduw_mmu, |
| 561 |
helper_ret_ldul_mmu, |
| 562 |
helper_ret_ldq_mmu, |
| 563 |
}; |
| 564 |
|
| 565 |
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
|
| 566 |
* uintxx_t val, int mmu_idx, uintptr_t ra)
|
| 567 |
*/
|
| 568 |
static const void * const qemu_st_helpers[4] = { |
| 569 |
helper_ret_stb_mmu, |
| 570 |
helper_ret_stw_mmu, |
| 571 |
helper_ret_stl_mmu, |
| 572 |
helper_ret_stq_mmu, |
| 573 |
}; |
| 574 |
|
| 575 |
static void *ld_trampolines[4]; |
| 576 |
static void *st_trampolines[4]; |
| 577 |
|
| 578 |
static void tcg_out_tlb_check (TCGContext *s, int r0, int r1, int r2, |
| 579 |
int addr_reg, int addr_reg2, int s_bits, |
| 580 |
int offset1, int offset2, uint8_t **label_ptr) |
| 581 |
{
|
| 582 |
uint16_t retranst; |
| 583 |
|
| 584 |
tcg_out32 (s, (RLWINM |
| 585 |
| RA (r0) |
| 586 |
| RS (addr_reg) |
| 587 |
| SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
|
| 588 |
| MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
|
| 589 |
| ME (31 - CPU_TLB_ENTRY_BITS)
|
| 590 |
) |
| 591 |
); |
| 592 |
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0)); |
| 593 |
tcg_out32 (s, (LWZU |
| 594 |
| RT (r1) |
| 595 |
| RA (r0) |
| 596 |
| offset1 |
| 597 |
) |
| 598 |
); |
| 599 |
tcg_out32 (s, (RLWINM |
| 600 |
| RA (r2) |
| 601 |
| RS (addr_reg) |
| 602 |
| SH (0)
|
| 603 |
| MB ((32 - s_bits) & 31) |
| 604 |
| ME (31 - TARGET_PAGE_BITS)
|
| 605 |
) |
| 606 |
); |
| 607 |
|
| 608 |
tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
|
| 609 |
#if TARGET_LONG_BITS == 64 |
| 610 |
tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
|
| 611 |
tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
|
| 612 |
tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ)); |
| 613 |
#endif
|
| 614 |
|
| 615 |
/* Use a conditional branch-and-link so that we load a pointer to
|
| 616 |
somewhere within the current opcode, for passing on to the helper.
|
| 617 |
This address cannot be used for a tail call, but it's shorter
|
| 618 |
than forming an address from scratch. */
|
| 619 |
*label_ptr = s->code_ptr; |
| 620 |
retranst = ((uint16_t *) s->code_ptr)[1] & ~3; |
| 621 |
tcg_out32(s, BC | BI(7, CR_EQ) | retranst | BO_COND_FALSE | LK);
|
| 622 |
|
| 623 |
/* r0 now contains &env->tlb_table[mem_index][index].addr_x */
|
| 624 |
tcg_out32 (s, (LWZ |
| 625 |
| RT (r0) |
| 626 |
| RA (r0) |
| 627 |
| offset2 |
| 628 |
) |
| 629 |
); |
| 630 |
/* r0 = env->tlb_table[mem_index][index].addend */
|
| 631 |
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg)); |
| 632 |
/* r0 = env->tlb_table[mem_index][index].addend + addr */
|
| 633 |
|
| 634 |
} |
| 635 |
#endif
|
| 636 |
|
| 637 |
static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) |
| 638 |
{
|
| 639 |
int addr_reg, data_reg, data_reg2, r0, r1, rbase, bswap;
|
| 640 |
#ifdef CONFIG_SOFTMMU
|
| 641 |
int mem_index, s_bits, r2, addr_reg2;
|
| 642 |
uint8_t *label_ptr; |
| 643 |
#endif
|
| 644 |
|
| 645 |
data_reg = *args++; |
| 646 |
if (opc == 3) |
| 647 |
data_reg2 = *args++; |
| 648 |
else
|
| 649 |
data_reg2 = 0;
|
| 650 |
addr_reg = *args++; |
| 651 |
|
| 652 |
#ifdef CONFIG_SOFTMMU
|
| 653 |
#if TARGET_LONG_BITS == 64 |
| 654 |
addr_reg2 = *args++; |
| 655 |
#else
|
| 656 |
addr_reg2 = 0;
|
| 657 |
#endif
|
| 658 |
mem_index = *args; |
| 659 |
s_bits = opc & 3;
|
| 660 |
r0 = 3;
|
| 661 |
r1 = 4;
|
| 662 |
r2 = 0;
|
| 663 |
rbase = 0;
|
| 664 |
|
| 665 |
tcg_out_tlb_check ( |
| 666 |
s, r0, r1, r2, addr_reg, addr_reg2, s_bits, |
| 667 |
offsetof (CPUArchState, tlb_table[mem_index][0].addr_read),
|
| 668 |
offsetof (CPUTLBEntry, addend) - offsetof (CPUTLBEntry, addr_read), |
| 669 |
&label_ptr |
| 670 |
); |
| 671 |
#else /* !CONFIG_SOFTMMU */ |
| 672 |
r0 = addr_reg; |
| 673 |
r1 = 3;
|
| 674 |
rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
|
| 675 |
#endif
|
| 676 |
|
| 677 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 678 |
bswap = 0;
|
| 679 |
#else
|
| 680 |
bswap = 1;
|
| 681 |
#endif
|
| 682 |
|
| 683 |
switch (opc) {
|
| 684 |
default:
|
| 685 |
case 0: |
| 686 |
tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0)); |
| 687 |
break;
|
| 688 |
case 0|4: |
| 689 |
tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0)); |
| 690 |
tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg)); |
| 691 |
break;
|
| 692 |
case 1: |
| 693 |
if (bswap)
|
| 694 |
tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0)); |
| 695 |
else
|
| 696 |
tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0)); |
| 697 |
break;
|
| 698 |
case 1|4: |
| 699 |
if (bswap) {
|
| 700 |
tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0)); |
| 701 |
tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg)); |
| 702 |
} |
| 703 |
else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
|
| 704 |
break;
|
| 705 |
case 2: |
| 706 |
if (bswap)
|
| 707 |
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0)); |
| 708 |
else
|
| 709 |
tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0)); |
| 710 |
break;
|
| 711 |
case 3: |
| 712 |
if (bswap) {
|
| 713 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
| 714 |
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0)); |
| 715 |
tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1)); |
| 716 |
} |
| 717 |
else {
|
| 718 |
#ifdef CONFIG_USE_GUEST_BASE
|
| 719 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
| 720 |
tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0)); |
| 721 |
tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1)); |
| 722 |
#else
|
| 723 |
if (r0 == data_reg2) {
|
| 724 |
tcg_out32 (s, LWZ | RT (0) | RA (r0));
|
| 725 |
tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
|
| 726 |
tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 0);
|
| 727 |
} |
| 728 |
else {
|
| 729 |
tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0)); |
| 730 |
tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
|
| 731 |
} |
| 732 |
#endif
|
| 733 |
} |
| 734 |
break;
|
| 735 |
} |
| 736 |
#ifdef CONFIG_SOFTMMU
|
| 737 |
add_qemu_ldst_label (s, |
| 738 |
1,
|
| 739 |
opc, |
| 740 |
data_reg, |
| 741 |
data_reg2, |
| 742 |
addr_reg, |
| 743 |
addr_reg2, |
| 744 |
mem_index, |
| 745 |
s->code_ptr, |
| 746 |
label_ptr); |
| 747 |
#endif
|
| 748 |
} |
| 749 |
|
| 750 |
static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) |
| 751 |
{
|
| 752 |
int addr_reg, r0, r1, data_reg, data_reg2, bswap, rbase;
|
| 753 |
#ifdef CONFIG_SOFTMMU
|
| 754 |
int mem_index, r2, addr_reg2;
|
| 755 |
uint8_t *label_ptr; |
| 756 |
#endif
|
| 757 |
|
| 758 |
data_reg = *args++; |
| 759 |
if (opc == 3) |
| 760 |
data_reg2 = *args++; |
| 761 |
else
|
| 762 |
data_reg2 = 0;
|
| 763 |
addr_reg = *args++; |
| 764 |
|
| 765 |
#ifdef CONFIG_SOFTMMU
|
| 766 |
#if TARGET_LONG_BITS == 64 |
| 767 |
addr_reg2 = *args++; |
| 768 |
#else
|
| 769 |
addr_reg2 = 0;
|
| 770 |
#endif
|
| 771 |
mem_index = *args; |
| 772 |
r0 = 3;
|
| 773 |
r1 = 4;
|
| 774 |
r2 = 0;
|
| 775 |
rbase = 0;
|
| 776 |
|
| 777 |
tcg_out_tlb_check ( |
| 778 |
s, r0, r1, r2, addr_reg, addr_reg2, opc & 3,
|
| 779 |
offsetof (CPUArchState, tlb_table[mem_index][0].addr_write),
|
| 780 |
offsetof (CPUTLBEntry, addend) - offsetof (CPUTLBEntry, addr_write), |
| 781 |
&label_ptr |
| 782 |
); |
| 783 |
#else /* !CONFIG_SOFTMMU */ |
| 784 |
r0 = addr_reg; |
| 785 |
r1 = 3;
|
| 786 |
rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
|
| 787 |
#endif
|
| 788 |
|
| 789 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 790 |
bswap = 0;
|
| 791 |
#else
|
| 792 |
bswap = 1;
|
| 793 |
#endif
|
| 794 |
switch (opc) {
|
| 795 |
case 0: |
| 796 |
tcg_out32 (s, STBX | SAB (data_reg, rbase, r0)); |
| 797 |
break;
|
| 798 |
case 1: |
| 799 |
if (bswap)
|
| 800 |
tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0)); |
| 801 |
else
|
| 802 |
tcg_out32 (s, STHX | SAB (data_reg, rbase, r0)); |
| 803 |
break;
|
| 804 |
case 2: |
| 805 |
if (bswap)
|
| 806 |
tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0)); |
| 807 |
else
|
| 808 |
tcg_out32 (s, STWX | SAB (data_reg, rbase, r0)); |
| 809 |
break;
|
| 810 |
case 3: |
| 811 |
if (bswap) {
|
| 812 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
| 813 |
tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0)); |
| 814 |
tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1)); |
| 815 |
} |
| 816 |
else {
|
| 817 |
#ifdef CONFIG_USE_GUEST_BASE
|
| 818 |
tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0)); |
| 819 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
| 820 |
tcg_out32 (s, STWX | SAB (data_reg, rbase, r1)); |
| 821 |
#else
|
| 822 |
tcg_out32 (s, STW | RS (data_reg2) | RA (r0)); |
| 823 |
tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
|
| 824 |
#endif
|
| 825 |
} |
| 826 |
break;
|
| 827 |
} |
| 828 |
|
| 829 |
#ifdef CONFIG_SOFTMMU
|
| 830 |
add_qemu_ldst_label (s, |
| 831 |
0,
|
| 832 |
opc, |
| 833 |
data_reg, |
| 834 |
data_reg2, |
| 835 |
addr_reg, |
| 836 |
addr_reg2, |
| 837 |
mem_index, |
| 838 |
s->code_ptr, |
| 839 |
label_ptr); |
| 840 |
#endif
|
| 841 |
} |
| 842 |
|
| 843 |
#if defined(CONFIG_SOFTMMU)
|
| 844 |
static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) |
| 845 |
{
|
| 846 |
TCGReg ir, datalo, datahi; |
| 847 |
|
| 848 |
reloc_pc14 (l->label_ptr[0], (uintptr_t)s->code_ptr);
|
| 849 |
|
| 850 |
ir = TCG_REG_R4; |
| 851 |
if (TARGET_LONG_BITS == 32) { |
| 852 |
tcg_out_mov(s, TCG_TYPE_I32, ir++, l->addrlo_reg); |
| 853 |
} else {
|
| 854 |
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
|
| 855 |
ir |= 1;
|
| 856 |
#endif
|
| 857 |
tcg_out_mov(s, TCG_TYPE_I32, ir++, l->addrhi_reg); |
| 858 |
tcg_out_mov(s, TCG_TYPE_I32, ir++, l->addrlo_reg); |
| 859 |
} |
| 860 |
tcg_out_movi(s, TCG_TYPE_I32, ir++, l->mem_index); |
| 861 |
tcg_out32(s, MFSPR | RT(ir++) | LR); |
| 862 |
tcg_out_b(s, LK, (uintptr_t)ld_trampolines[l->opc & 3]);
|
| 863 |
|
| 864 |
datalo = l->datalo_reg; |
| 865 |
switch (l->opc) {
|
| 866 |
case 0|4: |
| 867 |
tcg_out32(s, EXTSB | RA(datalo) | RS(TCG_REG_R3)); |
| 868 |
break;
|
| 869 |
case 1|4: |
| 870 |
tcg_out32(s, EXTSH | RA(datalo) | RS(TCG_REG_R3)); |
| 871 |
break;
|
| 872 |
case 0: |
| 873 |
case 1: |
| 874 |
case 2: |
| 875 |
tcg_out_mov(s, TCG_TYPE_I32, datalo, TCG_REG_R3); |
| 876 |
break;
|
| 877 |
case 3: |
| 878 |
datahi = l->datahi_reg; |
| 879 |
if (datalo != TCG_REG_R3) {
|
| 880 |
tcg_out_mov(s, TCG_TYPE_I32, datalo, TCG_REG_R4); |
| 881 |
tcg_out_mov(s, TCG_TYPE_I32, datahi, TCG_REG_R3); |
| 882 |
} else if (datahi != TCG_REG_R4) { |
| 883 |
tcg_out_mov(s, TCG_TYPE_I32, datahi, TCG_REG_R3); |
| 884 |
tcg_out_mov(s, TCG_TYPE_I32, datalo, TCG_REG_R4); |
| 885 |
} else {
|
| 886 |
tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, TCG_REG_R4); |
| 887 |
tcg_out_mov(s, TCG_TYPE_I32, datahi, TCG_REG_R3); |
| 888 |
tcg_out_mov(s, TCG_TYPE_I32, datalo, TCG_REG_R0); |
| 889 |
} |
| 890 |
break;
|
| 891 |
} |
| 892 |
tcg_out_b (s, 0, (uintptr_t)l->raddr);
|
| 893 |
} |
| 894 |
|
| 895 |
static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) |
| 896 |
{
|
| 897 |
TCGReg ir, datalo; |
| 898 |
|
| 899 |
reloc_pc14 (l->label_ptr[0], (tcg_target_long) s->code_ptr);
|
| 900 |
|
| 901 |
ir = TCG_REG_R4; |
| 902 |
if (TARGET_LONG_BITS == 32) { |
| 903 |
tcg_out_mov (s, TCG_TYPE_I32, ir++, l->addrlo_reg); |
| 904 |
} else {
|
| 905 |
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
|
| 906 |
ir |= 1;
|
| 907 |
#endif
|
| 908 |
tcg_out_mov (s, TCG_TYPE_I32, ir++, l->addrhi_reg); |
| 909 |
tcg_out_mov (s, TCG_TYPE_I32, ir++, l->addrlo_reg); |
| 910 |
} |
| 911 |
|
| 912 |
datalo = l->datalo_reg; |
| 913 |
switch (l->opc) {
|
| 914 |
case 0: |
| 915 |
tcg_out32(s, (RLWINM | RA (ir) | RS (datalo) |
| 916 |
| SH (0) | MB (24) | ME (31))); |
| 917 |
break;
|
| 918 |
case 1: |
| 919 |
tcg_out32(s, (RLWINM | RA (ir) | RS (datalo) |
| 920 |
| SH (0) | MB (16) | ME (31))); |
| 921 |
break;
|
| 922 |
case 2: |
| 923 |
tcg_out_mov(s, TCG_TYPE_I32, ir, datalo); |
| 924 |
break;
|
| 925 |
case 3: |
| 926 |
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
|
| 927 |
ir |= 1;
|
| 928 |
#endif
|
| 929 |
tcg_out_mov(s, TCG_TYPE_I32, ir++, l->datahi_reg); |
| 930 |
tcg_out_mov(s, TCG_TYPE_I32, ir, datalo); |
| 931 |
break;
|
| 932 |
} |
| 933 |
ir++; |
| 934 |
|
| 935 |
tcg_out_movi(s, TCG_TYPE_I32, ir++, l->mem_index); |
| 936 |
tcg_out32(s, MFSPR | RT(ir++) | LR); |
| 937 |
tcg_out_b(s, LK, (uintptr_t)st_trampolines[l->opc]); |
| 938 |
tcg_out_b(s, 0, (uintptr_t)l->raddr);
|
| 939 |
} |
| 940 |
|
| 941 |
void tcg_out_tb_finalize(TCGContext *s)
|
| 942 |
{
|
| 943 |
int i;
|
| 944 |
TCGLabelQemuLdst *label; |
| 945 |
|
| 946 |
/* qemu_ld/st slow paths */
|
| 947 |
for (i = 0; i < s->nb_qemu_ldst_labels; i++) { |
| 948 |
label = (TCGLabelQemuLdst *) &s->qemu_ldst_labels[i]; |
| 949 |
if (label->is_ld) {
|
| 950 |
tcg_out_qemu_ld_slow_path (s, label); |
| 951 |
} |
| 952 |
else {
|
| 953 |
tcg_out_qemu_st_slow_path (s, label); |
| 954 |
} |
| 955 |
} |
| 956 |
} |
| 957 |
#endif
|
| 958 |
|
| 959 |
#ifdef CONFIG_SOFTMMU
|
| 960 |
static void emit_ldst_trampoline (TCGContext *s, const void *ptr) |
| 961 |
{
|
| 962 |
tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0);
|
| 963 |
tcg_out_call (s, (tcg_target_long) ptr, 1, 0); |
| 964 |
} |
| 965 |
#endif
|
| 966 |
|
| 967 |
static void tcg_target_qemu_prologue (TCGContext *s) |
| 968 |
{
|
| 969 |
int i, frame_size;
|
| 970 |
|
| 971 |
frame_size = 0
|
| 972 |
+ LINKAGE_AREA_SIZE |
| 973 |
+ TCG_STATIC_CALL_ARGS_SIZE |
| 974 |
+ ARRAY_SIZE (tcg_target_callee_save_regs) * 4
|
| 975 |
+ CPU_TEMP_BUF_NLONGS * sizeof(long) |
| 976 |
; |
| 977 |
frame_size = (frame_size + 15) & ~15; |
| 978 |
|
| 979 |
tcg_set_frame(s, TCG_REG_CALL_STACK, frame_size |
| 980 |
- CPU_TEMP_BUF_NLONGS * sizeof(long), |
| 981 |
CPU_TEMP_BUF_NLONGS * sizeof(long)); |
| 982 |
|
| 983 |
#ifdef _CALL_AIX
|
| 984 |
{
|
| 985 |
uint32_t addr; |
| 986 |
|
| 987 |
/* First emit adhoc function descriptor */
|
| 988 |
addr = (uint32_t) s->code_ptr + 12;
|
| 989 |
tcg_out32 (s, addr); /* entry point */
|
| 990 |
s->code_ptr += 8; /* skip TOC and environment pointer */ |
| 991 |
} |
| 992 |
#endif
|
| 993 |
tcg_out32 (s, MFSPR | RT (0) | LR);
|
| 994 |
tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff)); |
| 995 |
for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i) |
| 996 |
tcg_out32 (s, (STW |
| 997 |
| RS (tcg_target_callee_save_regs[i]) |
| 998 |
| RA (1)
|
| 999 |
| (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
|
| 1000 |
) |
| 1001 |
); |
| 1002 |
tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET)); |
| 1003 |
|
| 1004 |
#ifdef CONFIG_USE_GUEST_BASE
|
| 1005 |
if (GUEST_BASE) {
|
| 1006 |
tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE); |
| 1007 |
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); |
| 1008 |
} |
| 1009 |
#endif
|
| 1010 |
|
| 1011 |
tcg_out_mov (s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
|
| 1012 |
tcg_out32 (s, MTSPR | RS (tcg_target_call_iarg_regs[1]) | CTR);
|
| 1013 |
tcg_out32 (s, BCCTR | BO_ALWAYS); |
| 1014 |
tb_ret_addr = s->code_ptr; |
| 1015 |
|
| 1016 |
for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i) |
| 1017 |
tcg_out32 (s, (LWZ |
| 1018 |
| RT (tcg_target_callee_save_regs[i]) |
| 1019 |
| RA (1)
|
| 1020 |
| (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
|
| 1021 |
) |
| 1022 |
); |
| 1023 |
tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET)); |
| 1024 |
tcg_out32 (s, MTSPR | RS (0) | LR);
|
| 1025 |
tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size); |
| 1026 |
tcg_out32 (s, BCLR | BO_ALWAYS); |
| 1027 |
|
| 1028 |
#ifdef CONFIG_SOFTMMU
|
| 1029 |
for (i = 0; i < 4; ++i) { |
| 1030 |
ld_trampolines[i] = s->code_ptr; |
| 1031 |
emit_ldst_trampoline (s, qemu_ld_helpers[i]); |
| 1032 |
|
| 1033 |
st_trampolines[i] = s->code_ptr; |
| 1034 |
emit_ldst_trampoline (s, qemu_st_helpers[i]); |
| 1035 |
} |
| 1036 |
#endif
|
| 1037 |
} |
| 1038 |
|
| 1039 |
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, |
| 1040 |
intptr_t arg2) |
| 1041 |
{
|
| 1042 |
tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX); |
| 1043 |
} |
| 1044 |
|
| 1045 |
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, |
| 1046 |
intptr_t arg2) |
| 1047 |
{
|
| 1048 |
tcg_out_ldst (s, arg, arg1, arg2, STW, STWX); |
| 1049 |
} |
| 1050 |
|
| 1051 |
static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si) |
| 1052 |
{
|
| 1053 |
if (!si && rt == ra)
|
| 1054 |
return;
|
| 1055 |
|
| 1056 |
if (si == (int16_t) si)
|
| 1057 |
tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
|
| 1058 |
else {
|
| 1059 |
uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15); |
| 1060 |
tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h); |
| 1061 |
tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
|
| 1062 |
} |
| 1063 |
} |
| 1064 |
|
| 1065 |
static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, |
| 1066 |
int const_arg2, int cr) |
| 1067 |
{
|
| 1068 |
int imm;
|
| 1069 |
uint32_t op; |
| 1070 |
|
| 1071 |
switch (cond) {
|
| 1072 |
case TCG_COND_EQ:
|
| 1073 |
case TCG_COND_NE:
|
| 1074 |
if (const_arg2) {
|
| 1075 |
if ((int16_t) arg2 == arg2) {
|
| 1076 |
op = CMPI; |
| 1077 |
imm = 1;
|
| 1078 |
break;
|
| 1079 |
} |
| 1080 |
else if ((uint16_t) arg2 == arg2) { |
| 1081 |
op = CMPLI; |
| 1082 |
imm = 1;
|
| 1083 |
break;
|
| 1084 |
} |
| 1085 |
} |
| 1086 |
op = CMPL; |
| 1087 |
imm = 0;
|
| 1088 |
break;
|
| 1089 |
|
| 1090 |
case TCG_COND_LT:
|
| 1091 |
case TCG_COND_GE:
|
| 1092 |
case TCG_COND_LE:
|
| 1093 |
case TCG_COND_GT:
|
| 1094 |
if (const_arg2) {
|
| 1095 |
if ((int16_t) arg2 == arg2) {
|
| 1096 |
op = CMPI; |
| 1097 |
imm = 1;
|
| 1098 |
break;
|
| 1099 |
} |
| 1100 |
} |
| 1101 |
op = CMP; |
| 1102 |
imm = 0;
|
| 1103 |
break;
|
| 1104 |
|
| 1105 |
case TCG_COND_LTU:
|
| 1106 |
case TCG_COND_GEU:
|
| 1107 |
case TCG_COND_LEU:
|
| 1108 |
case TCG_COND_GTU:
|
| 1109 |
if (const_arg2) {
|
| 1110 |
if ((uint16_t) arg2 == arg2) {
|
| 1111 |
op = CMPLI; |
| 1112 |
imm = 1;
|
| 1113 |
break;
|
| 1114 |
} |
| 1115 |
} |
| 1116 |
op = CMPL; |
| 1117 |
imm = 0;
|
| 1118 |
break;
|
| 1119 |
|
| 1120 |
default:
|
| 1121 |
tcg_abort (); |
| 1122 |
} |
| 1123 |
op |= BF (cr); |
| 1124 |
|
| 1125 |
if (imm)
|
| 1126 |
tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
|
| 1127 |
else {
|
| 1128 |
if (const_arg2) {
|
| 1129 |
tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
|
| 1130 |
tcg_out32 (s, op | RA (arg1) | RB (0));
|
| 1131 |
} |
| 1132 |
else
|
| 1133 |
tcg_out32 (s, op | RA (arg1) | RB (arg2)); |
| 1134 |
} |
| 1135 |
|
| 1136 |
} |
| 1137 |
|
| 1138 |
static void tcg_out_bc (TCGContext *s, int bc, int label_index) |
| 1139 |
{
|
| 1140 |
TCGLabel *l = &s->labels[label_index]; |
| 1141 |
|
| 1142 |
if (l->has_value)
|
| 1143 |
tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value)); |
| 1144 |
else {
|
| 1145 |
uint16_t val = *(uint16_t *) &s->code_ptr[2];
|
| 1146 |
|
| 1147 |
/* Thanks to Andrzej Zaborowski */
|
| 1148 |
tcg_out32 (s, bc | (val & 0xfffc));
|
| 1149 |
tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0); |
| 1150 |
} |
| 1151 |
} |
| 1152 |
|
| 1153 |
static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args, |
| 1154 |
const int *const_args) |
| 1155 |
{
|
| 1156 |
TCGCond cond = args[4];
|
| 1157 |
int op;
|
| 1158 |
struct { int bit1; int bit2; int cond2; } bits[] = { |
| 1159 |
[TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
|
| 1160 |
[TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
|
| 1161 |
[TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
|
| 1162 |
[TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
|
| 1163 |
[TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
|
| 1164 |
[TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
|
| 1165 |
[TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
|
| 1166 |
[TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
|
| 1167 |
}, *b = &bits[cond]; |
| 1168 |
|
| 1169 |
switch (cond) {
|
| 1170 |
case TCG_COND_EQ:
|
| 1171 |
case TCG_COND_NE:
|
| 1172 |
op = (cond == TCG_COND_EQ) ? CRAND : CRNAND; |
| 1173 |
tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6); |
| 1174 |
tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7); |
| 1175 |
tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ)); |
| 1176 |
break;
|
| 1177 |
case TCG_COND_LT:
|
| 1178 |
case TCG_COND_LE:
|
| 1179 |
case TCG_COND_GT:
|
| 1180 |
case TCG_COND_GE:
|
| 1181 |
case TCG_COND_LTU:
|
| 1182 |
case TCG_COND_LEU:
|
| 1183 |
case TCG_COND_GTU:
|
| 1184 |
case TCG_COND_GEU:
|
| 1185 |
op = (b->bit1 != b->bit2) ? CRANDC : CRAND; |
| 1186 |
tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5); |
| 1187 |
tcg_out_cmp (s, tcg_unsigned_cond (cond), args[0], args[2], |
| 1188 |
const_args[2], 7); |
| 1189 |
tcg_out32 (s, op | BT (7, CR_EQ) | BA (5, CR_EQ) | BB (7, b->bit2)); |
| 1190 |
tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ)); |
| 1191 |
break;
|
| 1192 |
default:
|
| 1193 |
tcg_abort(); |
| 1194 |
} |
| 1195 |
} |
| 1196 |
|
| 1197 |
static void tcg_out_setcond (TCGContext *s, TCGCond cond, TCGArg arg0, |
| 1198 |
TCGArg arg1, TCGArg arg2, int const_arg2)
|
| 1199 |
{
|
| 1200 |
int crop, sh, arg;
|
| 1201 |
|
| 1202 |
switch (cond) {
|
| 1203 |
case TCG_COND_EQ:
|
| 1204 |
if (const_arg2) {
|
| 1205 |
if (!arg2) {
|
| 1206 |
arg = arg1; |
| 1207 |
} |
| 1208 |
else {
|
| 1209 |
arg = 0;
|
| 1210 |
if ((uint16_t) arg2 == arg2) {
|
| 1211 |
tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
|
| 1212 |
} |
| 1213 |
else {
|
| 1214 |
tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
|
| 1215 |
tcg_out32 (s, XOR | SAB (arg1, 0, 0)); |
| 1216 |
} |
| 1217 |
} |
| 1218 |
} |
| 1219 |
else {
|
| 1220 |
arg = 0;
|
| 1221 |
tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
|
| 1222 |
} |
| 1223 |
tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
|
| 1224 |
tcg_out32 (s, (RLWINM |
| 1225 |
| RA (arg0) |
| 1226 |
| RS (0)
|
| 1227 |
| SH (27)
|
| 1228 |
| MB (5)
|
| 1229 |
| ME (31)
|
| 1230 |
) |
| 1231 |
); |
| 1232 |
break;
|
| 1233 |
|
| 1234 |
case TCG_COND_NE:
|
| 1235 |
if (const_arg2) {
|
| 1236 |
if (!arg2) {
|
| 1237 |
arg = arg1; |
| 1238 |
} |
| 1239 |
else {
|
| 1240 |
arg = 0;
|
| 1241 |
if ((uint16_t) arg2 == arg2) {
|
| 1242 |
tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
|
| 1243 |
} |
| 1244 |
else {
|
| 1245 |
tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
|
| 1246 |
tcg_out32 (s, XOR | SAB (arg1, 0, 0)); |
| 1247 |
} |
| 1248 |
} |
| 1249 |
} |
| 1250 |
else {
|
| 1251 |
arg = 0;
|
| 1252 |
tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
|
| 1253 |
} |
| 1254 |
|
| 1255 |
if (arg == arg1 && arg1 == arg0) {
|
| 1256 |
tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff); |
| 1257 |
tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
|
| 1258 |
} |
| 1259 |
else {
|
| 1260 |
tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
|
| 1261 |
tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg)); |
| 1262 |
} |
| 1263 |
break;
|
| 1264 |
|
| 1265 |
case TCG_COND_GT:
|
| 1266 |
case TCG_COND_GTU:
|
| 1267 |
sh = 30;
|
| 1268 |
crop = 0;
|
| 1269 |
goto crtest;
|
| 1270 |
|
| 1271 |
case TCG_COND_LT:
|
| 1272 |
case TCG_COND_LTU:
|
| 1273 |
sh = 29;
|
| 1274 |
crop = 0;
|
| 1275 |
goto crtest;
|
| 1276 |
|
| 1277 |
case TCG_COND_GE:
|
| 1278 |
case TCG_COND_GEU:
|
| 1279 |
sh = 31;
|
| 1280 |
crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT); |
| 1281 |
goto crtest;
|
| 1282 |
|
| 1283 |
case TCG_COND_LE:
|
| 1284 |
case TCG_COND_LEU:
|
| 1285 |
sh = 31;
|
| 1286 |
crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT); |
| 1287 |
crtest:
|
| 1288 |
tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
|
| 1289 |
if (crop) tcg_out32 (s, crop);
|
| 1290 |
tcg_out32 (s, MFCR | RT (0));
|
| 1291 |
tcg_out32 (s, (RLWINM |
| 1292 |
| RA (arg0) |
| 1293 |
| RS (0)
|
| 1294 |
| SH (sh) |
| 1295 |
| MB (31)
|
| 1296 |
| ME (31)
|
| 1297 |
) |
| 1298 |
); |
| 1299 |
break;
|
| 1300 |
|
| 1301 |
default:
|
| 1302 |
tcg_abort (); |
| 1303 |
} |
| 1304 |
} |
| 1305 |
|
| 1306 |
static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args, |
| 1307 |
const int *const_args) |
| 1308 |
{
|
| 1309 |
tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1); |
| 1310 |
tcg_out32 (s, MFCR | RT (0));
|
| 1311 |
tcg_out32 (s, (RLWINM |
| 1312 |
| RA (args[0])
|
| 1313 |
| RS (0)
|
| 1314 |
| SH (31)
|
| 1315 |
| MB (31)
|
| 1316 |
| ME (31)
|
| 1317 |
) |
| 1318 |
); |
| 1319 |
} |
| 1320 |
|
| 1321 |
static void tcg_out_movcond (TCGContext *s, TCGCond cond, |
| 1322 |
TCGArg dest, |
| 1323 |
TCGArg c1, TCGArg c2, |
| 1324 |
TCGArg v1, TCGArg v2, |
| 1325 |
int const_c2)
|
| 1326 |
{
|
| 1327 |
tcg_out_cmp (s, cond, c1, c2, const_c2, 7);
|
| 1328 |
|
| 1329 |
if (1) { |
| 1330 |
/* At least here on 7747A bit twiddling hacks are outperformed
|
| 1331 |
by jumpy code (the testing was not scientific) */
|
| 1332 |
if (dest == v2) {
|
| 1333 |
cond = tcg_invert_cond (cond); |
| 1334 |
v2 = v1; |
| 1335 |
} |
| 1336 |
else {
|
| 1337 |
if (dest != v1) {
|
| 1338 |
tcg_out_mov (s, TCG_TYPE_I32, dest, v1); |
| 1339 |
} |
| 1340 |
} |
| 1341 |
/* Branch forward over one insn */
|
| 1342 |
tcg_out32 (s, tcg_to_bc[cond] | 8);
|
| 1343 |
tcg_out_mov (s, TCG_TYPE_I32, dest, v2); |
| 1344 |
} |
| 1345 |
else {
|
| 1346 |
/* isel version, "if (1)" above should be replaced once a way
|
| 1347 |
to figure out availability of isel on the underlying
|
| 1348 |
hardware is found */
|
| 1349 |
int tab, bc;
|
| 1350 |
|
| 1351 |
switch (cond) {
|
| 1352 |
case TCG_COND_EQ:
|
| 1353 |
tab = TAB (dest, v1, v2); |
| 1354 |
bc = CR_EQ; |
| 1355 |
break;
|
| 1356 |
case TCG_COND_NE:
|
| 1357 |
tab = TAB (dest, v2, v1); |
| 1358 |
bc = CR_EQ; |
| 1359 |
break;
|
| 1360 |
case TCG_COND_LTU:
|
| 1361 |
case TCG_COND_LT:
|
| 1362 |
tab = TAB (dest, v1, v2); |
| 1363 |
bc = CR_LT; |
| 1364 |
break;
|
| 1365 |
case TCG_COND_GEU:
|
| 1366 |
case TCG_COND_GE:
|
| 1367 |
tab = TAB (dest, v2, v1); |
| 1368 |
bc = CR_LT; |
| 1369 |
break;
|
| 1370 |
case TCG_COND_LEU:
|
| 1371 |
case TCG_COND_LE:
|
| 1372 |
tab = TAB (dest, v2, v1); |
| 1373 |
bc = CR_GT; |
| 1374 |
break;
|
| 1375 |
case TCG_COND_GTU:
|
| 1376 |
case TCG_COND_GT:
|
| 1377 |
tab = TAB (dest, v1, v2); |
| 1378 |
bc = CR_GT; |
| 1379 |
break;
|
| 1380 |
default:
|
| 1381 |
tcg_abort (); |
| 1382 |
} |
| 1383 |
tcg_out32 (s, ISEL | tab | ((bc + 28) << 6)); |
| 1384 |
} |
| 1385 |
} |
| 1386 |
|
| 1387 |
static void tcg_out_brcond (TCGContext *s, TCGCond cond, |
| 1388 |
TCGArg arg1, TCGArg arg2, int const_arg2,
|
| 1389 |
int label_index)
|
| 1390 |
{
|
| 1391 |
tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
|
| 1392 |
tcg_out_bc (s, tcg_to_bc[cond], label_index); |
| 1393 |
} |
| 1394 |
|
| 1395 |
/* XXX: we implement it at the target level to avoid having to
|
| 1396 |
handle cross basic blocks temporaries */
|
| 1397 |
static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, |
| 1398 |
const int *const_args) |
| 1399 |
{
|
| 1400 |
tcg_out_cr7eq_from_cond (s, args, const_args); |
| 1401 |
tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]); |
| 1402 |
} |
| 1403 |
|
| 1404 |
void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr) |
| 1405 |
{
|
| 1406 |
uint32_t *ptr; |
| 1407 |
long disp = addr - jmp_addr;
|
| 1408 |
unsigned long patch_size; |
| 1409 |
|
| 1410 |
ptr = (uint32_t *)jmp_addr; |
| 1411 |
|
| 1412 |
if ((disp << 6) >> 6 != disp) { |
| 1413 |
ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */ |
| 1414 |
ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */ |
| 1415 |
ptr[2] = 0x7c0903a6; /* mtctr 0 */ |
| 1416 |
ptr[3] = 0x4e800420; /* brctr */ |
| 1417 |
patch_size = 16;
|
| 1418 |
} else {
|
| 1419 |
/* patch the branch destination */
|
| 1420 |
if (disp != 16) { |
| 1421 |
*ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */ |
| 1422 |
patch_size = 4;
|
| 1423 |
} else {
|
| 1424 |
ptr[0] = 0x60000000; /* nop */ |
| 1425 |
ptr[1] = 0x60000000; |
| 1426 |
ptr[2] = 0x60000000; |
| 1427 |
ptr[3] = 0x60000000; |
| 1428 |
patch_size = 16;
|
| 1429 |
} |
| 1430 |
} |
| 1431 |
/* flush icache */
|
| 1432 |
flush_icache_range(jmp_addr, jmp_addr + patch_size); |
| 1433 |
} |
| 1434 |
|
| 1435 |
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, |
| 1436 |
const int *const_args) |
| 1437 |
{
|
| 1438 |
switch (opc) {
|
| 1439 |
case INDEX_op_exit_tb:
|
| 1440 |
tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
|
| 1441 |
tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
|
| 1442 |
break;
|
| 1443 |
case INDEX_op_goto_tb:
|
| 1444 |
if (s->tb_jmp_offset) {
|
| 1445 |
/* direct jump method */
|
| 1446 |
|
| 1447 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
| 1448 |
s->code_ptr += 16;
|
| 1449 |
} |
| 1450 |
else {
|
| 1451 |
tcg_abort (); |
| 1452 |
} |
| 1453 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
| 1454 |
break;
|
| 1455 |
case INDEX_op_br:
|
| 1456 |
{
|
| 1457 |
TCGLabel *l = &s->labels[args[0]];
|
| 1458 |
|
| 1459 |
if (l->has_value) {
|
| 1460 |
tcg_out_b (s, 0, l->u.value);
|
| 1461 |
} |
| 1462 |
else {
|
| 1463 |
uint32_t val = *(uint32_t *) s->code_ptr; |
| 1464 |
|
| 1465 |
/* Thanks to Andrzej Zaborowski */
|
| 1466 |
tcg_out32 (s, B | (val & 0x3fffffc));
|
| 1467 |
tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0); |
| 1468 |
} |
| 1469 |
} |
| 1470 |
break;
|
| 1471 |
case INDEX_op_call:
|
| 1472 |
tcg_out_call (s, args[0], const_args[0], LK); |
| 1473 |
break;
|
| 1474 |
case INDEX_op_movi_i32:
|
| 1475 |
tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); |
| 1476 |
break;
|
| 1477 |
case INDEX_op_ld8u_i32:
|
| 1478 |
tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX); |
| 1479 |
break;
|
| 1480 |
case INDEX_op_ld8s_i32:
|
| 1481 |
tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX); |
| 1482 |
tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0])); |
| 1483 |
break;
|
| 1484 |
case INDEX_op_ld16u_i32:
|
| 1485 |
tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX); |
| 1486 |
break;
|
| 1487 |
case INDEX_op_ld16s_i32:
|
| 1488 |
tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX); |
| 1489 |
break;
|
| 1490 |
case INDEX_op_ld_i32:
|
| 1491 |
tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX); |
| 1492 |
break;
|
| 1493 |
case INDEX_op_st8_i32:
|
| 1494 |
tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX); |
| 1495 |
break;
|
| 1496 |
case INDEX_op_st16_i32:
|
| 1497 |
tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX); |
| 1498 |
break;
|
| 1499 |
case INDEX_op_st_i32:
|
| 1500 |
tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX); |
| 1501 |
break;
|
| 1502 |
|
| 1503 |
case INDEX_op_add_i32:
|
| 1504 |
if (const_args[2]) |
| 1505 |
ppc_addi (s, args[0], args[1], args[2]); |
| 1506 |
else
|
| 1507 |
tcg_out32 (s, ADD | TAB (args[0], args[1], args[2])); |
| 1508 |
break;
|
| 1509 |
case INDEX_op_sub_i32:
|
| 1510 |
if (const_args[2]) |
| 1511 |
ppc_addi (s, args[0], args[1], -args[2]); |
| 1512 |
else
|
| 1513 |
tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1])); |
| 1514 |
break;
|
| 1515 |
|
| 1516 |
case INDEX_op_and_i32:
|
| 1517 |
if (const_args[2]) { |
| 1518 |
uint32_t c; |
| 1519 |
|
| 1520 |
c = args[2];
|
| 1521 |
|
| 1522 |
if (!c) {
|
| 1523 |
tcg_out_movi (s, TCG_TYPE_I32, args[0], 0); |
| 1524 |
break;
|
| 1525 |
} |
| 1526 |
#ifdef __PPU__
|
| 1527 |
uint32_t t, n; |
| 1528 |
int mb, me;
|
| 1529 |
|
| 1530 |
n = c ^ -(c & 1);
|
| 1531 |
t = n + (n & -n); |
| 1532 |
|
| 1533 |
if ((t & (t - 1)) == 0) { |
| 1534 |
int lzc, tzc;
|
| 1535 |
|
| 1536 |
if ((c & 0x80000001) == 0x80000001) { |
| 1537 |
lzc = clz32 (n); |
| 1538 |
tzc = ctz32 (n); |
| 1539 |
|
| 1540 |
mb = 32 - tzc;
|
| 1541 |
me = lzc - 1;
|
| 1542 |
} |
| 1543 |
else {
|
| 1544 |
lzc = clz32 (c); |
| 1545 |
tzc = ctz32 (c); |
| 1546 |
|
| 1547 |
mb = lzc; |
| 1548 |
me = 31 - tzc;
|
| 1549 |
} |
| 1550 |
|
| 1551 |
tcg_out32 (s, (RLWINM |
| 1552 |
| RA (args[0])
|
| 1553 |
| RS (args[1])
|
| 1554 |
| SH (0)
|
| 1555 |
| MB (mb) |
| 1556 |
| ME (me) |
| 1557 |
) |
| 1558 |
); |
| 1559 |
} |
| 1560 |
else
|
| 1561 |
#endif /* !__PPU__ */ |
| 1562 |
{
|
| 1563 |
if ((c & 0xffff) == c) |
| 1564 |
tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c); |
| 1565 |
else if ((c & 0xffff0000) == c) |
| 1566 |
tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0]) |
| 1567 |
| ((c >> 16) & 0xffff)); |
| 1568 |
else {
|
| 1569 |
tcg_out_movi (s, TCG_TYPE_I32, 0, c);
|
| 1570 |
tcg_out32 (s, AND | SAB (args[1], args[0], 0)); |
| 1571 |
} |
| 1572 |
} |
| 1573 |
} |
| 1574 |
else
|
| 1575 |
tcg_out32 (s, AND | SAB (args[1], args[0], args[2])); |
| 1576 |
break;
|
| 1577 |
case INDEX_op_or_i32:
|
| 1578 |
if (const_args[2]) { |
| 1579 |
if (args[2] & 0xffff) { |
| 1580 |
tcg_out32 (s, ORI | RS (args[1]) | RA (args[0]) |
| 1581 |
| (args[2] & 0xffff)); |
| 1582 |
if (args[2] >> 16) |
| 1583 |
tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0]) |
| 1584 |
| ((args[2] >> 16) & 0xffff)); |
| 1585 |
} |
| 1586 |
else {
|
| 1587 |
tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0]) |
| 1588 |
| ((args[2] >> 16) & 0xffff)); |
| 1589 |
} |
| 1590 |
} |
| 1591 |
else
|
| 1592 |
tcg_out32 (s, OR | SAB (args[1], args[0], args[2])); |
| 1593 |
break;
|
| 1594 |
case INDEX_op_xor_i32:
|
| 1595 |
if (const_args[2]) { |
| 1596 |
if ((args[2] & 0xffff) == args[2]) |
| 1597 |
tcg_out32 (s, XORI | RS (args[1]) | RA (args[0]) |
| 1598 |
| (args[2] & 0xffff)); |
| 1599 |
else if ((args[2] & 0xffff0000) == args[2]) |
| 1600 |
tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0]) |
| 1601 |
| ((args[2] >> 16) & 0xffff)); |
| 1602 |
else {
|
| 1603 |
tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]); |
| 1604 |
tcg_out32 (s, XOR | SAB (args[1], args[0], 0)); |
| 1605 |
} |
| 1606 |
} |
| 1607 |
else
|
| 1608 |
tcg_out32 (s, XOR | SAB (args[1], args[0], args[2])); |
| 1609 |
break;
|
| 1610 |
case INDEX_op_andc_i32:
|
| 1611 |
tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2])); |
| 1612 |
break;
|
| 1613 |
case INDEX_op_orc_i32:
|
| 1614 |
tcg_out32 (s, ORC | SAB (args[1], args[0], args[2])); |
| 1615 |
break;
|
| 1616 |
case INDEX_op_eqv_i32:
|
| 1617 |
tcg_out32 (s, EQV | SAB (args[1], args[0], args[2])); |
| 1618 |
break;
|
| 1619 |
case INDEX_op_nand_i32:
|
| 1620 |
tcg_out32 (s, NAND | SAB (args[1], args[0], args[2])); |
| 1621 |
break;
|
| 1622 |
case INDEX_op_nor_i32:
|
| 1623 |
tcg_out32 (s, NOR | SAB (args[1], args[0], args[2])); |
| 1624 |
break;
|
| 1625 |
|
| 1626 |
case INDEX_op_mul_i32:
|
| 1627 |
if (const_args[2]) { |
| 1628 |
if (args[2] == (int16_t) args[2]) |
| 1629 |
tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1]) |
| 1630 |
| (args[2] & 0xffff)); |
| 1631 |
else {
|
| 1632 |
tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]); |
| 1633 |
tcg_out32 (s, MULLW | TAB (args[0], args[1], 0)); |
| 1634 |
} |
| 1635 |
} |
| 1636 |
else
|
| 1637 |
tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2])); |
| 1638 |
break;
|
| 1639 |
|
| 1640 |
case INDEX_op_div_i32:
|
| 1641 |
tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2])); |
| 1642 |
break;
|
| 1643 |
|
| 1644 |
case INDEX_op_divu_i32:
|
| 1645 |
tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2])); |
| 1646 |
break;
|
| 1647 |
|
| 1648 |
case INDEX_op_mulu2_i32:
|
| 1649 |
if (args[0] == args[2] || args[0] == args[3]) { |
| 1650 |
tcg_out32 (s, MULLW | TAB (0, args[2], args[3])); |
| 1651 |
tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3])); |
| 1652 |
tcg_out_mov (s, TCG_TYPE_I32, args[0], 0); |
| 1653 |
} |
| 1654 |
else {
|
| 1655 |
tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3])); |
| 1656 |
tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3])); |
| 1657 |
} |
| 1658 |
break;
|
| 1659 |
|
| 1660 |
case INDEX_op_shl_i32:
|
| 1661 |
if (const_args[2]) { |
| 1662 |
tcg_out32 (s, (RLWINM |
| 1663 |
| RA (args[0])
|
| 1664 |
| RS (args[1])
|
| 1665 |
| SH (args[2])
|
| 1666 |
| MB (0)
|
| 1667 |
| ME (31 - args[2]) |
| 1668 |
) |
| 1669 |
); |
| 1670 |
} |
| 1671 |
else
|
| 1672 |
tcg_out32 (s, SLW | SAB (args[1], args[0], args[2])); |
| 1673 |
break;
|
| 1674 |
case INDEX_op_shr_i32:
|
| 1675 |
if (const_args[2]) { |
| 1676 |
tcg_out32 (s, (RLWINM |
| 1677 |
| RA (args[0])
|
| 1678 |
| RS (args[1])
|
| 1679 |
| SH (32 - args[2]) |
| 1680 |
| MB (args[2])
|
| 1681 |
| ME (31)
|
| 1682 |
) |
| 1683 |
); |
| 1684 |
} |
| 1685 |
else
|
| 1686 |
tcg_out32 (s, SRW | SAB (args[1], args[0], args[2])); |
| 1687 |
break;
|
| 1688 |
case INDEX_op_sar_i32:
|
| 1689 |
if (const_args[2]) |
| 1690 |
tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2])); |
| 1691 |
else
|
| 1692 |
tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2])); |
| 1693 |
break;
|
| 1694 |
case INDEX_op_rotl_i32:
|
| 1695 |
{
|
| 1696 |
int op = 0 |
| 1697 |
| RA (args[0])
|
| 1698 |
| RS (args[1])
|
| 1699 |
| MB (0)
|
| 1700 |
| ME (31)
|
| 1701 |
| (const_args[2] ? RLWINM | SH (args[2]) |
| 1702 |
: RLWNM | RB (args[2]))
|
| 1703 |
; |
| 1704 |
tcg_out32 (s, op); |
| 1705 |
} |
| 1706 |
break;
|
| 1707 |
case INDEX_op_rotr_i32:
|
| 1708 |
if (const_args[2]) { |
| 1709 |
if (!args[2]) { |
| 1710 |
tcg_out_mov (s, TCG_TYPE_I32, args[0], args[1]); |
| 1711 |
} |
| 1712 |
else {
|
| 1713 |
tcg_out32 (s, RLWINM |
| 1714 |
| RA (args[0])
|
| 1715 |
| RS (args[1])
|
| 1716 |
| SH (32 - args[2]) |
| 1717 |
| MB (0)
|
| 1718 |
| ME (31)
|
| 1719 |
); |
| 1720 |
} |
| 1721 |
} |
| 1722 |
else {
|
| 1723 |
tcg_out32 (s, SUBFIC | RT (0) | RA (args[2]) | 32); |
| 1724 |
tcg_out32 (s, RLWNM |
| 1725 |
| RA (args[0])
|
| 1726 |
| RS (args[1])
|
| 1727 |
| RB (0)
|
| 1728 |
| MB (0)
|
| 1729 |
| ME (31)
|
| 1730 |
); |
| 1731 |
} |
| 1732 |
break;
|
| 1733 |
|
| 1734 |
case INDEX_op_add2_i32:
|
| 1735 |
if (args[0] == args[3] || args[0] == args[5]) { |
| 1736 |
tcg_out32 (s, ADDC | TAB (0, args[2], args[4])); |
| 1737 |
tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5])); |
| 1738 |
tcg_out_mov (s, TCG_TYPE_I32, args[0], 0); |
| 1739 |
} |
| 1740 |
else {
|
| 1741 |
tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4])); |
| 1742 |
tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5])); |
| 1743 |
} |
| 1744 |
break;
|
| 1745 |
case INDEX_op_sub2_i32:
|
| 1746 |
if (args[0] == args[3] || args[0] == args[5]) { |
| 1747 |
tcg_out32 (s, SUBFC | TAB (0, args[4], args[2])); |
| 1748 |
tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3])); |
| 1749 |
tcg_out_mov (s, TCG_TYPE_I32, args[0], 0); |
| 1750 |
} |
| 1751 |
else {
|
| 1752 |
tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2])); |
| 1753 |
tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3])); |
| 1754 |
} |
| 1755 |
break;
|
| 1756 |
|
| 1757 |
case INDEX_op_brcond_i32:
|
| 1758 |
/*
|
| 1759 |
args[0] = r0
|
| 1760 |
args[1] = r1
|
| 1761 |
args[2] = cond
|
| 1762 |
args[3] = r1 is const
|
| 1763 |
args[4] = label_index
|
| 1764 |
*/
|
| 1765 |
tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]); |
| 1766 |
break;
|
| 1767 |
case INDEX_op_brcond2_i32:
|
| 1768 |
tcg_out_brcond2(s, args, const_args); |
| 1769 |
break;
|
| 1770 |
|
| 1771 |
case INDEX_op_neg_i32:
|
| 1772 |
tcg_out32 (s, NEG | RT (args[0]) | RA (args[1])); |
| 1773 |
break;
|
| 1774 |
|
| 1775 |
case INDEX_op_not_i32:
|
| 1776 |
tcg_out32 (s, NOR | SAB (args[1], args[0], args[1])); |
| 1777 |
break;
|
| 1778 |
|
| 1779 |
case INDEX_op_qemu_ld8u:
|
| 1780 |
tcg_out_qemu_ld(s, args, 0);
|
| 1781 |
break;
|
| 1782 |
case INDEX_op_qemu_ld8s:
|
| 1783 |
tcg_out_qemu_ld(s, args, 0 | 4); |
| 1784 |
break;
|
| 1785 |
case INDEX_op_qemu_ld16u:
|
| 1786 |
tcg_out_qemu_ld(s, args, 1);
|
| 1787 |
break;
|
| 1788 |
case INDEX_op_qemu_ld16s:
|
| 1789 |
tcg_out_qemu_ld(s, args, 1 | 4); |
| 1790 |
break;
|
| 1791 |
case INDEX_op_qemu_ld32:
|
| 1792 |
tcg_out_qemu_ld(s, args, 2);
|
| 1793 |
break;
|
| 1794 |
case INDEX_op_qemu_ld64:
|
| 1795 |
tcg_out_qemu_ld(s, args, 3);
|
| 1796 |
break;
|
| 1797 |
case INDEX_op_qemu_st8:
|
| 1798 |
tcg_out_qemu_st(s, args, 0);
|
| 1799 |
break;
|
| 1800 |
case INDEX_op_qemu_st16:
|
| 1801 |
tcg_out_qemu_st(s, args, 1);
|
| 1802 |
break;
|
| 1803 |
case INDEX_op_qemu_st32:
|
| 1804 |
tcg_out_qemu_st(s, args, 2);
|
| 1805 |
break;
|
| 1806 |
case INDEX_op_qemu_st64:
|
| 1807 |
tcg_out_qemu_st(s, args, 3);
|
| 1808 |
break;
|
| 1809 |
|
| 1810 |
case INDEX_op_ext8s_i32:
|
| 1811 |
tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0])); |
| 1812 |
break;
|
| 1813 |
case INDEX_op_ext8u_i32:
|
| 1814 |
tcg_out32 (s, RLWINM |
| 1815 |
| RA (args[0])
|
| 1816 |
| RS (args[1])
|
| 1817 |
| SH (0)
|
| 1818 |
| MB (24)
|
| 1819 |
| ME (31)
|
| 1820 |
); |
| 1821 |
break;
|
| 1822 |
case INDEX_op_ext16s_i32:
|
| 1823 |
tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0])); |
| 1824 |
break;
|
| 1825 |
case INDEX_op_ext16u_i32:
|
| 1826 |
tcg_out32 (s, RLWINM |
| 1827 |
| RA (args[0])
|
| 1828 |
| RS (args[1])
|
| 1829 |
| SH (0)
|
| 1830 |
| MB (16)
|
| 1831 |
| ME (31)
|
| 1832 |
); |
| 1833 |
break;
|
| 1834 |
|
| 1835 |
case INDEX_op_setcond_i32:
|
| 1836 |
tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]); |
| 1837 |
break;
|
| 1838 |
case INDEX_op_setcond2_i32:
|
| 1839 |
tcg_out_setcond2 (s, args, const_args); |
| 1840 |
break;
|
| 1841 |
|
| 1842 |
case INDEX_op_bswap16_i32:
|
| 1843 |
/* Stolen from gcc's builtin_bswap16 */
|
| 1844 |
|
| 1845 |
/* a1 = abcd */
|
| 1846 |
|
| 1847 |
/* r0 = (a1 << 8) & 0xff00 # 00d0 */
|
| 1848 |
tcg_out32 (s, RLWINM |
| 1849 |
| RA (0)
|
| 1850 |
| RS (args[1])
|
| 1851 |
| SH (8)
|
| 1852 |
| MB (16)
|
| 1853 |
| ME (23)
|
| 1854 |
); |
| 1855 |
|
| 1856 |
/* a0 = rotate_left (a1, 24) & 0xff # 000c */
|
| 1857 |
tcg_out32 (s, RLWINM |
| 1858 |
| RA (args[0])
|
| 1859 |
| RS (args[1])
|
| 1860 |
| SH (24)
|
| 1861 |
| MB (24)
|
| 1862 |
| ME (31)
|
| 1863 |
); |
| 1864 |
|
| 1865 |
/* a0 = a0 | r0 # 00dc */
|
| 1866 |
tcg_out32 (s, OR | SAB (0, args[0], args[0])); |
| 1867 |
break;
|
| 1868 |
|
| 1869 |
case INDEX_op_bswap32_i32:
|
| 1870 |
/* Stolen from gcc's builtin_bswap32 */
|
| 1871 |
{
|
| 1872 |
int a0 = args[0]; |
| 1873 |
|
| 1874 |
/* a1 = args[1] # abcd */
|
| 1875 |
|
| 1876 |
if (a0 == args[1]) { |
| 1877 |
a0 = 0;
|
| 1878 |
} |
| 1879 |
|
| 1880 |
/* a0 = rotate_left (a1, 8) # bcda */
|
| 1881 |
tcg_out32 (s, RLWINM |
| 1882 |
| RA (a0) |
| 1883 |
| RS (args[1])
|
| 1884 |
| SH (8)
|
| 1885 |
| MB (0)
|
| 1886 |
| ME (31)
|
| 1887 |
); |
| 1888 |
|
| 1889 |
/* a0 = (a0 & ~0xff000000) | ((a1 << 24) & 0xff000000) # dcda */
|
| 1890 |
tcg_out32 (s, RLWIMI |
| 1891 |
| RA (a0) |
| 1892 |
| RS (args[1])
|
| 1893 |
| SH (24)
|
| 1894 |
| MB (0)
|
| 1895 |
| ME (7)
|
| 1896 |
); |
| 1897 |
|
| 1898 |
/* a0 = (a0 & ~0x0000ff00) | ((a1 << 24) & 0x0000ff00) # dcba */
|
| 1899 |
tcg_out32 (s, RLWIMI |
| 1900 |
| RA (a0) |
| 1901 |
| RS (args[1])
|
| 1902 |
| SH (24)
|
| 1903 |
| MB (16)
|
| 1904 |
| ME (23)
|
| 1905 |
); |
| 1906 |
|
| 1907 |
if (!a0) {
|
| 1908 |
tcg_out_mov (s, TCG_TYPE_I32, args[0], a0);
|
| 1909 |
} |
| 1910 |
} |
| 1911 |
break;
|
| 1912 |
|
| 1913 |
case INDEX_op_deposit_i32:
|
| 1914 |
tcg_out32 (s, RLWIMI |
| 1915 |
| RA (args[0])
|
| 1916 |
| RS (args[2])
|
| 1917 |
| SH (args[3])
|
| 1918 |
| MB (32 - args[3] - args[4]) |
| 1919 |
| ME (31 - args[3]) |
| 1920 |
); |
| 1921 |
break;
|
| 1922 |
|
| 1923 |
case INDEX_op_movcond_i32:
|
| 1924 |
tcg_out_movcond (s, args[5], args[0], |
| 1925 |
args[1], args[2], |
| 1926 |
args[3], args[4], |
| 1927 |
const_args[2]);
|
| 1928 |
break;
|
| 1929 |
|
| 1930 |
default:
|
| 1931 |
tcg_dump_ops (s); |
| 1932 |
tcg_abort (); |
| 1933 |
} |
| 1934 |
} |
| 1935 |
|
| 1936 |
static const TCGTargetOpDef ppc_op_defs[] = { |
| 1937 |
{ INDEX_op_exit_tb, { } },
|
| 1938 |
{ INDEX_op_goto_tb, { } },
|
| 1939 |
{ INDEX_op_call, { "ri" } },
|
| 1940 |
{ INDEX_op_br, { } },
|
| 1941 |
|
| 1942 |
{ INDEX_op_mov_i32, { "r", "r" } },
|
| 1943 |
{ INDEX_op_movi_i32, { "r" } },
|
| 1944 |
{ INDEX_op_ld8u_i32, { "r", "r" } },
|
| 1945 |
{ INDEX_op_ld8s_i32, { "r", "r" } },
|
| 1946 |
{ INDEX_op_ld16u_i32, { "r", "r" } },
|
| 1947 |
{ INDEX_op_ld16s_i32, { "r", "r" } },
|
| 1948 |
{ INDEX_op_ld_i32, { "r", "r" } },
|
| 1949 |
{ INDEX_op_st8_i32, { "r", "r" } },
|
| 1950 |
{ INDEX_op_st16_i32, { "r", "r" } },
|
| 1951 |
{ INDEX_op_st_i32, { "r", "r" } },
|
| 1952 |
|
| 1953 |
{ INDEX_op_add_i32, { "r", "r", "ri" } },
|
| 1954 |
{ INDEX_op_mul_i32, { "r", "r", "ri" } },
|
| 1955 |
{ INDEX_op_div_i32, { "r", "r", "r" } },
|
| 1956 |
{ INDEX_op_divu_i32, { "r", "r", "r" } },
|
| 1957 |
{ INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
|
| 1958 |
{ INDEX_op_sub_i32, { "r", "r", "ri" } },
|
| 1959 |
{ INDEX_op_and_i32, { "r", "r", "ri" } },
|
| 1960 |
{ INDEX_op_or_i32, { "r", "r", "ri" } },
|
| 1961 |
{ INDEX_op_xor_i32, { "r", "r", "ri" } },
|
| 1962 |
|
| 1963 |
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
|
| 1964 |
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
|
| 1965 |
{ INDEX_op_sar_i32, { "r", "r", "ri" } },
|
| 1966 |
|
| 1967 |
{ INDEX_op_rotl_i32, { "r", "r", "ri" } },
|
| 1968 |
{ INDEX_op_rotr_i32, { "r", "r", "ri" } },
|
| 1969 |
|
| 1970 |
{ INDEX_op_brcond_i32, { "r", "ri" } },
|
| 1971 |
|
| 1972 |
{ INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
|
| 1973 |
{ INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
|
| 1974 |
{ INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
|
| 1975 |
|
| 1976 |
{ INDEX_op_neg_i32, { "r", "r" } },
|
| 1977 |
{ INDEX_op_not_i32, { "r", "r" } },
|
| 1978 |
|
| 1979 |
{ INDEX_op_andc_i32, { "r", "r", "r" } },
|
| 1980 |
{ INDEX_op_orc_i32, { "r", "r", "r" } },
|
| 1981 |
{ INDEX_op_eqv_i32, { "r", "r", "r" } },
|
| 1982 |
{ INDEX_op_nand_i32, { "r", "r", "r" } },
|
| 1983 |
{ INDEX_op_nor_i32, { "r", "r", "r" } },
|
| 1984 |
|
| 1985 |
{ INDEX_op_setcond_i32, { "r", "r", "ri" } },
|
| 1986 |
{ INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
|
| 1987 |
|
| 1988 |
{ INDEX_op_bswap16_i32, { "r", "r" } },
|
| 1989 |
{ INDEX_op_bswap32_i32, { "r", "r" } },
|
| 1990 |
|
| 1991 |
#if TARGET_LONG_BITS == 32 |
| 1992 |
{ INDEX_op_qemu_ld8u, { "r", "L" } },
|
| 1993 |
{ INDEX_op_qemu_ld8s, { "r", "L" } },
|
| 1994 |
{ INDEX_op_qemu_ld16u, { "r", "L" } },
|
| 1995 |
{ INDEX_op_qemu_ld16s, { "r", "L" } },
|
| 1996 |
{ INDEX_op_qemu_ld32, { "r", "L" } },
|
| 1997 |
{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
|
| 1998 |
|
| 1999 |
{ INDEX_op_qemu_st8, { "K", "K" } },
|
| 2000 |
{ INDEX_op_qemu_st16, { "K", "K" } },
|
| 2001 |
{ INDEX_op_qemu_st32, { "K", "K" } },
|
| 2002 |
{ INDEX_op_qemu_st64, { "M", "M", "M" } },
|
| 2003 |
#else
|
| 2004 |
{ INDEX_op_qemu_ld8u, { "r", "L", "L" } },
|
| 2005 |
{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
|
| 2006 |
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
|
| 2007 |
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
|
| 2008 |
{ INDEX_op_qemu_ld32, { "r", "L", "L" } },
|
| 2009 |
{ INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
|
| 2010 |
|
| 2011 |
{ INDEX_op_qemu_st8, { "K", "K", "K" } },
|
| 2012 |
{ INDEX_op_qemu_st16, { "K", "K", "K" } },
|
| 2013 |
{ INDEX_op_qemu_st32, { "K", "K", "K" } },
|
| 2014 |
{ INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
|
| 2015 |
#endif
|
| 2016 |
|
| 2017 |
{ INDEX_op_ext8s_i32, { "r", "r" } },
|
| 2018 |
{ INDEX_op_ext8u_i32, { "r", "r" } },
|
| 2019 |
{ INDEX_op_ext16s_i32, { "r", "r" } },
|
| 2020 |
{ INDEX_op_ext16u_i32, { "r", "r" } },
|
| 2021 |
|
| 2022 |
{ INDEX_op_deposit_i32, { "r", "0", "r" } },
|
| 2023 |
{ INDEX_op_movcond_i32, { "r", "r", "ri", "r", "r" } },
|
| 2024 |
|
| 2025 |
{ -1 },
|
| 2026 |
}; |
| 2027 |
|
| 2028 |
static void tcg_target_init(TCGContext *s) |
| 2029 |
{
|
| 2030 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
| 2031 |
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
| 2032 |
(1 << TCG_REG_R0) |
|
| 2033 |
#ifdef TCG_TARGET_CALL_DARWIN
|
| 2034 |
(1 << TCG_REG_R2) |
|
| 2035 |
#endif
|
| 2036 |
(1 << TCG_REG_R3) |
|
| 2037 |
(1 << TCG_REG_R4) |
|
| 2038 |
(1 << TCG_REG_R5) |
|
| 2039 |
(1 << TCG_REG_R6) |
|
| 2040 |
(1 << TCG_REG_R7) |
|
| 2041 |
(1 << TCG_REG_R8) |
|
| 2042 |
(1 << TCG_REG_R9) |
|
| 2043 |
(1 << TCG_REG_R10) |
|
| 2044 |
(1 << TCG_REG_R11) |
|
| 2045 |
(1 << TCG_REG_R12)
|
| 2046 |
); |
| 2047 |
|
| 2048 |
tcg_regset_clear(s->reserved_regs); |
| 2049 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); |
| 2050 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); |
| 2051 |
#ifndef TCG_TARGET_CALL_DARWIN
|
| 2052 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); |
| 2053 |
#endif
|
| 2054 |
#ifdef _CALL_SYSV
|
| 2055 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); |
| 2056 |
#endif
|
| 2057 |
|
| 2058 |
tcg_add_target_add_op_defs(ppc_op_defs); |
| 2059 |
} |