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/*
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 * Sparc64 interrupt helpers
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 *
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 *  Copyright (c) 2003-2005 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "cpu.h"
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#include "helper.h"
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#include "trace.h"
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#define DEBUG_PCALL
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#ifdef DEBUG_PCALL
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static const char * const excp_names[0x80] = {
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    [TT_TFAULT] = "Instruction Access Fault",
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    [TT_TMISS] = "Instruction Access MMU Miss",
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    [TT_CODE_ACCESS] = "Instruction Access Error",
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    [TT_ILL_INSN] = "Illegal Instruction",
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    [TT_PRIV_INSN] = "Privileged Instruction",
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    [TT_NFPU_INSN] = "FPU Disabled",
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    [TT_FP_EXCP] = "FPU Exception",
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    [TT_TOVF] = "Tag Overflow",
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    [TT_CLRWIN] = "Clean Windows",
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    [TT_DIV_ZERO] = "Division By Zero",
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    [TT_DFAULT] = "Data Access Fault",
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    [TT_DMISS] = "Data Access MMU Miss",
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    [TT_DATA_ACCESS] = "Data Access Error",
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    [TT_DPROT] = "Data Protection Error",
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    [TT_UNALIGNED] = "Unaligned Memory Access",
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    [TT_PRIV_ACT] = "Privileged Action",
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    [TT_EXTINT | 0x1] = "External Interrupt 1",
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    [TT_EXTINT | 0x2] = "External Interrupt 2",
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    [TT_EXTINT | 0x3] = "External Interrupt 3",
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    [TT_EXTINT | 0x4] = "External Interrupt 4",
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    [TT_EXTINT | 0x5] = "External Interrupt 5",
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    [TT_EXTINT | 0x6] = "External Interrupt 6",
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    [TT_EXTINT | 0x7] = "External Interrupt 7",
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    [TT_EXTINT | 0x8] = "External Interrupt 8",
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    [TT_EXTINT | 0x9] = "External Interrupt 9",
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    [TT_EXTINT | 0xa] = "External Interrupt 10",
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    [TT_EXTINT | 0xb] = "External Interrupt 11",
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    [TT_EXTINT | 0xc] = "External Interrupt 12",
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    [TT_EXTINT | 0xd] = "External Interrupt 13",
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    [TT_EXTINT | 0xe] = "External Interrupt 14",
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    [TT_EXTINT | 0xf] = "External Interrupt 15",
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};
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#endif
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void sparc_cpu_do_interrupt(CPUState *cs)
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{
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    SPARCCPU *cpu = SPARC_CPU(cs);
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    CPUSPARCState *env = &cpu->env;
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    int intno = env->exception_index;
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    trap_state *tsptr;
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    /* Compute PSR before exposing state.  */
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    if (env->cc_op != CC_OP_FLAGS) {
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        cpu_get_psr(env);
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    }
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#ifdef DEBUG_PCALL
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    if (qemu_loglevel_mask(CPU_LOG_INT)) {
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        static int count;
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        const char *name;
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        if (intno < 0 || intno >= 0x180) {
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            name = "Unknown";
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        } else if (intno >= 0x100) {
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            name = "Trap Instruction";
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        } else if (intno >= 0xc0) {
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            name = "Window Fill";
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        } else if (intno >= 0x80) {
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            name = "Window Spill";
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        } else {
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            name = excp_names[intno];
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            if (!name) {
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                name = "Unknown";
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            }
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        }
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        qemu_log("%6d: %s (v=%04x)\n", count, name, intno);
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        log_cpu_state(cs, 0);
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#if 0
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        {
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            int i;
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            uint8_t *ptr;
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            qemu_log("       code=");
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            ptr = (uint8_t *)env->pc;
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            for (i = 0; i < 16; i++) {
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                qemu_log(" %02x", ldub(ptr + i));
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            }
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            qemu_log("\n");
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        }
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#endif
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        count++;
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    }
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#endif
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#if !defined(CONFIG_USER_ONLY)
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    if (env->tl >= env->maxtl) {
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        cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
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                  " Error state", env->exception_index, env->tl, env->maxtl);
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        return;
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    }
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#endif
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    if (env->tl < env->maxtl - 1) {
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        env->tl++;
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    } else {
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        env->pstate |= PS_RED;
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        if (env->tl < env->maxtl) {
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            env->tl++;
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        }
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    }
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    tsptr = cpu_tsptr(env);
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    tsptr->tstate = (cpu_get_ccr(env) << 32) |
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        ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
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        cpu_get_cwp64(env);
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    tsptr->tpc = env->pc;
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    tsptr->tnpc = env->npc;
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    tsptr->tt = intno;
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    switch (intno) {
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    case TT_IVEC:
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        cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
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        break;
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    case TT_TFAULT:
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    case TT_DFAULT:
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    case TT_TMISS ... TT_TMISS + 3:
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    case TT_DMISS ... TT_DMISS + 3:
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    case TT_DPROT ... TT_DPROT + 3:
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        cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
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        break;
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    default:
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        cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
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        break;
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    }
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    if (intno == TT_CLRWIN) {
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        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
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    } else if ((intno & 0x1c0) == TT_SPILL) {
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        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
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    } else if ((intno & 0x1c0) == TT_FILL) {
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        cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
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    }
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    env->tbr &= ~0x7fffULL;
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    env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
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    env->pc = env->tbr;
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    env->npc = env->pc + 4;
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    env->exception_index = -1;
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}
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trap_state *cpu_tsptr(CPUSPARCState* env)
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{
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    return &env->ts[env->tl & MAXTL_MASK];
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}
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static bool do_modify_softint(CPUSPARCState *env, uint32_t value)
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{
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    if (env->softint != value) {
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        env->softint = value;
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#if !defined(CONFIG_USER_ONLY)
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        if (cpu_interrupts_enabled(env)) {
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            cpu_check_irqs(env);
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        }
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#endif
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        return true;
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    }
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    return false;
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}
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void helper_set_softint(CPUSPARCState *env, uint64_t value)
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{
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    if (do_modify_softint(env, env->softint | (uint32_t)value)) {
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        trace_int_helper_set_softint(env->softint);
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    }
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}
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void helper_clear_softint(CPUSPARCState *env, uint64_t value)
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{
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    if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
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        trace_int_helper_clear_softint(env->softint);
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    }
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}
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void helper_write_softint(CPUSPARCState *env, uint64_t value)
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{
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    if (do_modify_softint(env, (uint32_t)value)) {
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        trace_int_helper_write_softint(env->softint);
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    }
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}