root / target-arm / exec.h @ 5bc89ef6
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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM execution defines
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 2c0262af | bellard | */
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19 | 8294eba1 | ths | #include "config.h" |
20 | 2c0262af | bellard | #include "dyngen-exec.h" |
21 | 2c0262af | bellard | |
22 | 2c0262af | bellard | register struct CPUARMState *env asm(AREG0); |
23 | 2c0262af | bellard | register uint32_t T0 asm(AREG1); |
24 | 2c0262af | bellard | register uint32_t T1 asm(AREG2); |
25 | 2c0262af | bellard | |
26 | 18c9b560 | balrog | #define M0 env->iwmmxt.val
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27 | 18c9b560 | balrog | |
28 | 2c0262af | bellard | #include "cpu.h" |
29 | 2c0262af | bellard | #include "exec-all.h" |
30 | 2c0262af | bellard | |
31 | 0d1a29f9 | bellard | static inline void env_to_regs(void) |
32 | 0d1a29f9 | bellard | { |
33 | 0d1a29f9 | bellard | } |
34 | 0d1a29f9 | bellard | |
35 | 0d1a29f9 | bellard | static inline void regs_to_env(void) |
36 | 0d1a29f9 | bellard | { |
37 | 0d1a29f9 | bellard | } |
38 | b8a9e8f1 | bellard | |
39 | 6a4955a8 | aliguori | static inline int cpu_has_work(CPUState *env) |
40 | 6a4955a8 | aliguori | { |
41 | 6a4955a8 | aliguori | return (env->interrupt_request &
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42 | 6a4955a8 | aliguori | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)); |
43 | 6a4955a8 | aliguori | } |
44 | 6a4955a8 | aliguori | |
45 | bfed01fc | ths | static inline int cpu_halted(CPUState *env) { |
46 | bfed01fc | ths | if (!env->halted)
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47 | bfed01fc | ths | return 0; |
48 | bfed01fc | ths | /* An interrupt wakes the CPU even if the I and F CPSR bits are
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49 | bfed01fc | ths | set. We use EXITTB to silently wake CPU without causing an
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50 | bfed01fc | ths | actual interrupt. */
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51 | 6a4955a8 | aliguori | if (cpu_has_work(env)) {
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52 | bfed01fc | ths | env->halted = 0;
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53 | bfed01fc | ths | return 0; |
54 | bfed01fc | ths | } |
55 | bfed01fc | ths | return EXCP_HALTED;
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56 | bfed01fc | ths | } |
57 | bfed01fc | ths | |
58 | b5ff1b31 | bellard | #if !defined(CONFIG_USER_ONLY)
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59 | b5ff1b31 | bellard | #include "softmmu_exec.h" |
60 | b5ff1b31 | bellard | #endif
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61 | b5ff1b31 | bellard | |
62 | b7bcbe95 | bellard | void raise_exception(int); |