Revision 5c0e12f5
| b/hw/misc/mst_fpga.c | ||
|---|---|---|
| 35 | 35 |
#define MST_PCMCIA_CD0_IRQ 9 |
| 36 | 36 |
#define MST_PCMCIA_CD1_IRQ 13 |
| 37 | 37 |
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| 38 |
#define TYPE_MAINSTONE_FPGA "mainstone-fpga" |
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#define MAINSTONE_FPGA(obj) \ |
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OBJECT_CHECK(mst_irq_state, (obj), TYPE_MAINSTONE_FPGA) |
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| 41 |
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| 38 | 42 |
typedef struct mst_irq_state{
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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qemu_irq parent; |
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| 43 |
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uint32_t prev_level; |
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uint32_t leddat1; |
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uint32_t leddat2; |
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uint32_t ledctrl; |
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uint32_t gpswr; |
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uint32_t mscwr1; |
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uint32_t mscwr2; |
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uint32_t mscwr3; |
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uint32_t mscrd; |
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uint32_t intmskena; |
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uint32_t intsetclr; |
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uint32_t pcmcia0; |
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uint32_t pcmcia1; |
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SysBusDevice parent_obj; |
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MemoryRegion iomem; |
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qemu_irq parent; |
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| 48 |
|
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uint32_t prev_level; |
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uint32_t leddat1; |
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uint32_t leddat2; |
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uint32_t ledctrl; |
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uint32_t gpswr; |
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uint32_t mscwr1; |
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uint32_t mscwr2; |
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uint32_t mscwr3; |
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uint32_t mscrd; |
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uint32_t intmskena; |
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uint32_t intsetclr; |
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uint32_t pcmcia0; |
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uint32_t pcmcia1; |
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| 57 | 62 |
}mst_irq_state; |
| 58 | 63 |
|
| 59 | 64 |
static void |
| ... | ... | |
| 194 | 199 |
return 0; |
| 195 | 200 |
} |
| 196 | 201 |
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static int mst_fpga_init(SysBusDevice *dev)
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static int mst_fpga_init(SysBusDevice *sbd)
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| 198 | 203 |
{
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mst_irq_state *s; |
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s = FROM_SYSBUS(mst_irq_state, dev); |
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DeviceState *dev = DEVICE(sbd); |
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mst_irq_state *s = MAINSTONE_FPGA(dev); |
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| 202 | 206 |
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s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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| 205 | 209 |
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sysbus_init_irq(dev, &s->parent);
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sysbus_init_irq(sbd, &s->parent);
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| 207 | 211 |
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/* alloc the external 16 irqs */
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qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
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/* alloc the external 16 irqs */
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qdev_init_gpio_in(dev, mst_fpga_set_irq, MST_NUM_IRQS);
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| 210 | 214 |
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memory_region_init_io(&s->iomem, OBJECT(s), &mst_fpga_ops, s,
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"fpga", 0x00100000);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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memory_region_init_io(&s->iomem, OBJECT(s), &mst_fpga_ops, s,
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"fpga", 0x00100000);
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sysbus_init_mmio(sbd, &s->iomem);
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return 0;
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| 215 | 219 |
} |
| 216 | 220 |
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| 217 | 221 |
static VMStateDescription vmstate_mst_fpga_regs = {
|
| ... | ... | |
| 249 | 253 |
} |
| 250 | 254 |
|
| 251 | 255 |
static const TypeInfo mst_fpga_info = {
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.name = "mainstone-fpga",
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.name = TYPE_MAINSTONE_FPGA,
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| 253 | 257 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 254 | 258 |
.instance_size = sizeof(mst_irq_state), |
| 255 | 259 |
.class_init = mst_fpga_class_init, |
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