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/*
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* CBUS three-pin bus and the Retu / Betty / Tahvo / Vilma / Avilma /
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* Hinku / Vinku / Ahne / Pihi chips used in various Nokia platforms.
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* Based on reverse-engineering of a linux driver.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "qemu-common.h" |
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#include "irq.h" |
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#include "devices.h" |
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#include "sysemu.h" |
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//#define DEBUG
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struct cbus_slave_s;
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struct cbus_priv_s {
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struct cbus_s cbus;
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int sel;
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int dat;
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int clk;
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int bit;
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int dir;
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uint16_t val; |
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qemu_irq dat_out; |
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int addr;
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int reg;
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int rw;
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enum {
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cbus_address, |
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cbus_value, |
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} cycle; |
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|
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struct cbus_slave_s *slave[8]; |
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}; |
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struct cbus_slave_s {
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void *opaque;
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void (*io)(void *opaque, int rw, int reg, uint16_t *val); |
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int addr;
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}; |
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static void cbus_io(struct cbus_priv_s *s) |
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{
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if (s->slave[s->addr])
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s->slave[s->addr]->io(s->slave[s->addr]->opaque, |
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s->rw, s->reg, &s->val); |
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else
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cpu_abort(cpu_single_env, "%s: bad slave address %i\n",
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__FUNCTION__, s->addr); |
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} |
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static void cbus_cycle(struct cbus_priv_s *s) |
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{
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switch (s->cycle) {
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case cbus_address:
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s->addr = (s->val >> 6) & 7; |
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s->rw = (s->val >> 5) & 1; |
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s->reg = (s->val >> 0) & 0x1f; |
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s->cycle = cbus_value; |
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s->bit = 15;
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s->dir = !s->rw; |
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s->val = 0;
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if (s->rw)
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cbus_io(s); |
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break;
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case cbus_value:
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if (!s->rw)
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cbus_io(s); |
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s->cycle = cbus_address; |
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s->bit = 8;
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s->dir = 1;
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s->val = 0;
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break;
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} |
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} |
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static void cbus_clk(void *opaque, int line, int level) |
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{
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struct cbus_priv_s *s = (struct cbus_priv_s *) opaque; |
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if (!s->sel && level && !s->clk) {
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if (s->dir)
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s->val |= s->dat << (s->bit --); |
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else
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qemu_set_irq(s->dat_out, (s->val >> (s->bit --)) & 1);
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if (s->bit < 0) |
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cbus_cycle(s); |
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} |
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s->clk = level; |
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} |
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static void cbus_dat(void *opaque, int line, int level) |
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{
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struct cbus_priv_s *s = (struct cbus_priv_s *) opaque; |
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s->dat = level; |
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} |
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static void cbus_sel(void *opaque, int line, int level) |
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{
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struct cbus_priv_s *s = (struct cbus_priv_s *) opaque; |
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if (!level) {
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s->dir = 1;
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s->bit = 8;
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s->val = 0;
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} |
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s->sel = level; |
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} |
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struct cbus_s *cbus_init(qemu_irq dat)
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{
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struct cbus_priv_s *s = (struct cbus_priv_s *) qemu_mallocz(sizeof(*s)); |
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s->dat_out = dat; |
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s->cbus.clk = qemu_allocate_irqs(cbus_clk, s, 1)[0]; |
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s->cbus.dat = qemu_allocate_irqs(cbus_dat, s, 1)[0]; |
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s->cbus.sel = qemu_allocate_irqs(cbus_sel, s, 1)[0]; |
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s->sel = 1;
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s->clk = 0;
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s->dat = 0;
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return &s->cbus;
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} |
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void cbus_attach(struct cbus_s *bus, void *slave_opaque) |
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{
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struct cbus_slave_s *slave = (struct cbus_slave_s *) slave_opaque; |
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struct cbus_priv_s *s = (struct cbus_priv_s *) bus; |
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s->slave[slave->addr] = slave; |
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} |
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/* Retu/Vilma */
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struct cbus_retu_s {
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uint16_t irqst; |
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uint16_t irqen; |
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uint16_t cc[2];
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int channel;
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uint16_t result[16];
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uint16_t sample; |
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uint16_t status; |
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struct {
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uint16_t cal; |
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} rtc; |
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int is_vilma;
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qemu_irq irq; |
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struct cbus_slave_s cbus;
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}; |
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static void retu_interrupt_update(struct cbus_retu_s *s) |
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{
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qemu_set_irq(s->irq, s->irqst & ~s->irqen); |
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} |
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#define RETU_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ |
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#define RETU_REG_IDR 0x01 /* (T) Interrupt ID */ |
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#define RETU_REG_IMR 0x02 /* (RW) Interrupt mask */ |
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#define RETU_REG_RTCDSR 0x03 /* (RW) RTC seconds register */ |
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#define RETU_REG_RTCHMR 0x04 /* (RO) RTC hours and minutes reg */ |
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#define RETU_REG_RTCHMAR 0x05 /* (RW) RTC hours and minutes set reg */ |
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#define RETU_REG_RTCCALR 0x06 /* (RW) RTC calibration register */ |
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#define RETU_REG_ADCR 0x08 /* (RW) ADC result register */ |
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#define RETU_REG_ADCSCR 0x09 /* (RW) ADC sample control register */ |
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#define RETU_REG_AFCR 0x0a /* (RW) AFC register */ |
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#define RETU_REG_ANTIFR 0x0b /* (RW) AntiF register */ |
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#define RETU_REG_CALIBR 0x0c /* (RW) CalibR register*/ |
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#define RETU_REG_CCR1 0x0d /* (RW) Common control register 1 */ |
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#define RETU_REG_CCR2 0x0e /* (RW) Common control register 2 */ |
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#define RETU_REG_RCTRL_CLR 0x0f /* (T) Regulator clear register */ |
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#define RETU_REG_RCTRL_SET 0x10 /* (T) Regulator set register */ |
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#define RETU_REG_TXCR 0x11 /* (RW) TxC register */ |
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#define RETU_REG_STATUS 0x16 /* (RO) Status register */ |
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#define RETU_REG_WATCHDOG 0x17 /* (RW) Watchdog register */ |
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#define RETU_REG_AUDTXR 0x18 /* (RW) Audio Codec Tx register */ |
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#define RETU_REG_AUDPAR 0x19 /* (RW) AudioPA register */ |
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#define RETU_REG_AUDRXR1 0x1a /* (RW) Audio receive register 1 */ |
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#define RETU_REG_AUDRXR2 0x1b /* (RW) Audio receive register 2 */ |
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#define RETU_REG_SGR1 0x1c /* (RW) */ |
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#define RETU_REG_SCR1 0x1d /* (RW) */ |
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#define RETU_REG_SGR2 0x1e /* (RW) */ |
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#define RETU_REG_SCR2 0x1f /* (RW) */ |
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/* Retu Interrupt sources */
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enum {
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retu_int_pwr = 0, /* Power button */ |
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retu_int_char = 1, /* Charger */ |
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retu_int_rtcs = 2, /* Seconds */ |
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retu_int_rtcm = 3, /* Minutes */ |
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retu_int_rtcd = 4, /* Days */ |
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retu_int_rtca = 5, /* Alarm */ |
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retu_int_hook = 6, /* Hook */ |
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retu_int_head = 7, /* Headset */ |
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retu_int_adcs = 8, /* ADC sample */ |
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}; |
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/* Retu ADC channel wiring */
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enum {
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retu_adc_bsi = 1, /* BSI */ |
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retu_adc_batt_temp = 2, /* Battery temperature */ |
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retu_adc_chg_volt = 3, /* Charger voltage */ |
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retu_adc_head_det = 4, /* Headset detection */ |
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retu_adc_hook_det = 5, /* Hook detection */ |
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retu_adc_rf_gp = 6, /* RF GP */ |
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retu_adc_tx_det = 7, /* Wideband Tx detection */ |
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retu_adc_batt_volt = 8, /* Battery voltage */ |
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retu_adc_sens = 10, /* Light sensor */ |
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retu_adc_sens_temp = 11, /* Light sensor temperature */ |
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retu_adc_bbatt_volt = 12, /* Backup battery voltage */ |
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retu_adc_self_temp = 13, /* RETU temperature */ |
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}; |
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static inline uint16_t retu_read(struct cbus_retu_s *s, int reg) |
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{
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#ifdef DEBUG
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printf("RETU read at %02x\n", reg);
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#endif
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switch (reg) {
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case RETU_REG_ASICR:
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return 0x0215 | (s->is_vilma << 7); |
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case RETU_REG_IDR: /* TODO: Or is this ffs(s->irqst)? */ |
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return s->irqst;
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case RETU_REG_IMR:
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return s->irqen;
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case RETU_REG_RTCDSR:
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case RETU_REG_RTCHMR:
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case RETU_REG_RTCHMAR:
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/* TODO */
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return 0x0000; |
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case RETU_REG_RTCCALR:
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return s->rtc.cal;
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case RETU_REG_ADCR:
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return (s->channel << 10) | s->result[s->channel]; |
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case RETU_REG_ADCSCR:
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return s->sample;
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case RETU_REG_AFCR:
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case RETU_REG_ANTIFR:
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case RETU_REG_CALIBR:
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/* TODO */
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return 0x0000; |
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case RETU_REG_CCR1:
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return s->cc[0]; |
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case RETU_REG_CCR2:
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return s->cc[1]; |
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case RETU_REG_RCTRL_CLR:
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case RETU_REG_RCTRL_SET:
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case RETU_REG_TXCR:
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/* TODO */
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return 0x0000; |
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case RETU_REG_STATUS:
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return s->status;
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case RETU_REG_WATCHDOG:
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case RETU_REG_AUDTXR:
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case RETU_REG_AUDPAR:
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case RETU_REG_AUDRXR1:
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case RETU_REG_AUDRXR2:
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case RETU_REG_SGR1:
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case RETU_REG_SCR1:
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case RETU_REG_SGR2:
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case RETU_REG_SCR2:
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/* TODO */
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return 0x0000; |
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default:
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cpu_abort(cpu_single_env, "%s: bad register %02x\n",
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__FUNCTION__, reg); |
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} |
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} |
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static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val) |
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{
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#ifdef DEBUG
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printf("RETU write of %04x at %02x\n", val, reg);
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#endif
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switch (reg) {
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case RETU_REG_IDR:
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s->irqst ^= val; |
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retu_interrupt_update(s); |
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break;
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|
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case RETU_REG_IMR:
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s->irqen = val; |
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retu_interrupt_update(s); |
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break;
|
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|
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case RETU_REG_RTCDSR:
|
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case RETU_REG_RTCHMAR:
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/* TODO */
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break;
|
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|
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case RETU_REG_RTCCALR:
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s->rtc.cal = val; |
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break;
|
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|
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case RETU_REG_ADCR:
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s->channel = (val >> 10) & 0xf; |
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s->irqst |= 1 << retu_int_adcs;
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retu_interrupt_update(s); |
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break;
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case RETU_REG_ADCSCR:
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s->sample &= ~val; |
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break;
|
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|
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case RETU_REG_AFCR:
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case RETU_REG_ANTIFR:
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case RETU_REG_CALIBR:
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|
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case RETU_REG_CCR1:
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s->cc[0] = val;
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break;
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case RETU_REG_CCR2:
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s->cc[1] = val;
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break;
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|
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case RETU_REG_RCTRL_CLR:
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case RETU_REG_RCTRL_SET:
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/* TODO */
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break;
|
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|
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case RETU_REG_WATCHDOG:
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if (val == 0 && (s->cc[0] & 2)) |
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qemu_system_shutdown_request(); |
| 364 |
break;
|
| 365 |
|
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case RETU_REG_TXCR:
|
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case RETU_REG_AUDTXR:
|
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case RETU_REG_AUDPAR:
|
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case RETU_REG_AUDRXR1:
|
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case RETU_REG_AUDRXR2:
|
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case RETU_REG_SGR1:
|
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case RETU_REG_SCR1:
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case RETU_REG_SGR2:
|
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case RETU_REG_SCR2:
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/* TODO */
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break;
|
| 377 |
|
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default:
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cpu_abort(cpu_single_env, "%s: bad register %02x\n",
|
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__FUNCTION__, reg); |
| 381 |
} |
| 382 |
} |
| 383 |
|
| 384 |
static void retu_io(void *opaque, int rw, int reg, uint16_t *val) |
| 385 |
{
|
| 386 |
struct cbus_retu_s *s = (struct cbus_retu_s *) opaque; |
| 387 |
|
| 388 |
if (rw)
|
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*val = retu_read(s, reg); |
| 390 |
else
|
| 391 |
retu_write(s, reg, *val); |
| 392 |
} |
| 393 |
|
| 394 |
void *retu_init(qemu_irq irq, int vilma) |
| 395 |
{
|
| 396 |
struct cbus_retu_s *s = (struct cbus_retu_s *) qemu_mallocz(sizeof(*s)); |
| 397 |
|
| 398 |
s->irq = irq; |
| 399 |
s->irqen = 0xffff;
|
| 400 |
s->irqst = 0x0000;
|
| 401 |
s->status = 0x0020;
|
| 402 |
s->is_vilma = !!vilma; |
| 403 |
s->rtc.cal = 0x01;
|
| 404 |
s->result[retu_adc_bsi] = 0x3c2;
|
| 405 |
s->result[retu_adc_batt_temp] = 0x0fc;
|
| 406 |
s->result[retu_adc_chg_volt] = 0x165;
|
| 407 |
s->result[retu_adc_head_det] = 123;
|
| 408 |
s->result[retu_adc_hook_det] = 1023;
|
| 409 |
s->result[retu_adc_rf_gp] = 0x11;
|
| 410 |
s->result[retu_adc_tx_det] = 0x11;
|
| 411 |
s->result[retu_adc_batt_volt] = 0x250;
|
| 412 |
s->result[retu_adc_sens] = 2;
|
| 413 |
s->result[retu_adc_sens_temp] = 0x11;
|
| 414 |
s->result[retu_adc_bbatt_volt] = 0x3d0;
|
| 415 |
s->result[retu_adc_self_temp] = 0x330;
|
| 416 |
|
| 417 |
s->cbus.opaque = s; |
| 418 |
s->cbus.io = retu_io; |
| 419 |
s->cbus.addr = 1;
|
| 420 |
|
| 421 |
return &s->cbus;
|
| 422 |
} |
| 423 |
|
| 424 |
void retu_key_event(void *retu, int state) |
| 425 |
{
|
| 426 |
struct cbus_slave_s *slave = (struct cbus_slave_s *) retu; |
| 427 |
struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque; |
| 428 |
|
| 429 |
s->irqst |= 1 << retu_int_pwr;
|
| 430 |
retu_interrupt_update(s); |
| 431 |
|
| 432 |
if (state)
|
| 433 |
s->status &= ~(1 << 5); |
| 434 |
else
|
| 435 |
s->status |= 1 << 5; |
| 436 |
} |
| 437 |
|
| 438 |
#if 0
|
| 439 |
static void retu_head_event(void *retu, int state)
|
| 440 |
{
|
| 441 |
struct cbus_slave_s *slave = (struct cbus_slave_s *) retu;
|
| 442 |
struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque;
|
| 443 |
|
| 444 |
if ((s->cc[0] & 0x500) == 0x500) { /* TODO: Which bits? */
|
| 445 |
/* TODO: reissue the interrupt every 100ms or so. */
|
| 446 |
s->irqst |= 1 << retu_int_head;
|
| 447 |
retu_interrupt_update(s);
|
| 448 |
}
|
| 449 |
|
| 450 |
if (state)
|
| 451 |
s->result[retu_adc_head_det] = 50;
|
| 452 |
else
|
| 453 |
s->result[retu_adc_head_det] = 123;
|
| 454 |
}
|
| 455 |
|
| 456 |
static void retu_hook_event(void *retu, int state)
|
| 457 |
{
|
| 458 |
struct cbus_slave_s *slave = (struct cbus_slave_s *) retu;
|
| 459 |
struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque;
|
| 460 |
|
| 461 |
if ((s->cc[0] & 0x500) == 0x500) {
|
| 462 |
/* TODO: reissue the interrupt every 100ms or so. */
|
| 463 |
s->irqst |= 1 << retu_int_hook;
|
| 464 |
retu_interrupt_update(s);
|
| 465 |
}
|
| 466 |
|
| 467 |
if (state)
|
| 468 |
s->result[retu_adc_hook_det] = 50;
|
| 469 |
else
|
| 470 |
s->result[retu_adc_hook_det] = 123;
|
| 471 |
}
|
| 472 |
#endif
|
| 473 |
|
| 474 |
/* Tahvo/Betty */
|
| 475 |
struct cbus_tahvo_s {
|
| 476 |
uint16_t irqst; |
| 477 |
uint16_t irqen; |
| 478 |
uint8_t charger; |
| 479 |
uint8_t backlight; |
| 480 |
uint16_t usbr; |
| 481 |
uint16_t power; |
| 482 |
|
| 483 |
int is_betty;
|
| 484 |
qemu_irq irq; |
| 485 |
struct cbus_slave_s cbus;
|
| 486 |
}; |
| 487 |
|
| 488 |
static void tahvo_interrupt_update(struct cbus_tahvo_s *s) |
| 489 |
{
|
| 490 |
qemu_set_irq(s->irq, s->irqst & ~s->irqen); |
| 491 |
} |
| 492 |
|
| 493 |
#define TAHVO_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ |
| 494 |
#define TAHVO_REG_IDR 0x01 /* (T) Interrupt ID */ |
| 495 |
#define TAHVO_REG_IDSR 0x02 /* (RO) Interrupt status */ |
| 496 |
#define TAHVO_REG_IMR 0x03 /* (RW) Interrupt mask */ |
| 497 |
#define TAHVO_REG_CHAPWMR 0x04 /* (RW) Charger PWM */ |
| 498 |
#define TAHVO_REG_LEDPWMR 0x05 /* (RW) LED PWM */ |
| 499 |
#define TAHVO_REG_USBR 0x06 /* (RW) USB control */ |
| 500 |
#define TAHVO_REG_RCR 0x07 /* (RW) Some kind of power management */ |
| 501 |
#define TAHVO_REG_CCR1 0x08 /* (RW) Common control register 1 */ |
| 502 |
#define TAHVO_REG_CCR2 0x09 /* (RW) Common control register 2 */ |
| 503 |
#define TAHVO_REG_TESTR1 0x0a /* (RW) Test register 1 */ |
| 504 |
#define TAHVO_REG_TESTR2 0x0b /* (RW) Test register 2 */ |
| 505 |
#define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */ |
| 506 |
#define TAHVO_REG_FRR 0x0d /* (RO) FR */ |
| 507 |
|
| 508 |
static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg) |
| 509 |
{
|
| 510 |
#ifdef DEBUG
|
| 511 |
printf("TAHVO read at %02x\n", reg);
|
| 512 |
#endif
|
| 513 |
|
| 514 |
switch (reg) {
|
| 515 |
case TAHVO_REG_ASICR:
|
| 516 |
return 0x0021 | (s->is_betty ? 0x0b00 : 0x0300); /* 22 in N810 */ |
| 517 |
|
| 518 |
case TAHVO_REG_IDR:
|
| 519 |
case TAHVO_REG_IDSR: /* XXX: what does this do? */ |
| 520 |
return s->irqst;
|
| 521 |
|
| 522 |
case TAHVO_REG_IMR:
|
| 523 |
return s->irqen;
|
| 524 |
|
| 525 |
case TAHVO_REG_CHAPWMR:
|
| 526 |
return s->charger;
|
| 527 |
|
| 528 |
case TAHVO_REG_LEDPWMR:
|
| 529 |
return s->backlight;
|
| 530 |
|
| 531 |
case TAHVO_REG_USBR:
|
| 532 |
return s->usbr;
|
| 533 |
|
| 534 |
case TAHVO_REG_RCR:
|
| 535 |
return s->power;
|
| 536 |
|
| 537 |
case TAHVO_REG_CCR1:
|
| 538 |
case TAHVO_REG_CCR2:
|
| 539 |
case TAHVO_REG_TESTR1:
|
| 540 |
case TAHVO_REG_TESTR2:
|
| 541 |
case TAHVO_REG_NOPR:
|
| 542 |
case TAHVO_REG_FRR:
|
| 543 |
return 0x0000; |
| 544 |
|
| 545 |
default:
|
| 546 |
cpu_abort(cpu_single_env, "%s: bad register %02x\n",
|
| 547 |
__FUNCTION__, reg); |
| 548 |
} |
| 549 |
} |
| 550 |
|
| 551 |
static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val) |
| 552 |
{
|
| 553 |
#ifdef DEBUG
|
| 554 |
printf("TAHVO write of %04x at %02x\n", val, reg);
|
| 555 |
#endif
|
| 556 |
|
| 557 |
switch (reg) {
|
| 558 |
case TAHVO_REG_IDR:
|
| 559 |
s->irqst ^= val; |
| 560 |
tahvo_interrupt_update(s); |
| 561 |
break;
|
| 562 |
|
| 563 |
case TAHVO_REG_IMR:
|
| 564 |
s->irqen = val; |
| 565 |
tahvo_interrupt_update(s); |
| 566 |
break;
|
| 567 |
|
| 568 |
case TAHVO_REG_CHAPWMR:
|
| 569 |
s->charger = val; |
| 570 |
break;
|
| 571 |
|
| 572 |
case TAHVO_REG_LEDPWMR:
|
| 573 |
if (s->backlight != (val & 0x7f)) { |
| 574 |
s->backlight = val & 0x7f;
|
| 575 |
printf("%s: LCD backlight now at %i / 127\n",
|
| 576 |
__FUNCTION__, s->backlight); |
| 577 |
} |
| 578 |
break;
|
| 579 |
|
| 580 |
case TAHVO_REG_USBR:
|
| 581 |
s->usbr = val; |
| 582 |
break;
|
| 583 |
|
| 584 |
case TAHVO_REG_RCR:
|
| 585 |
s->power = val; |
| 586 |
break;
|
| 587 |
|
| 588 |
case TAHVO_REG_CCR1:
|
| 589 |
case TAHVO_REG_CCR2:
|
| 590 |
case TAHVO_REG_TESTR1:
|
| 591 |
case TAHVO_REG_TESTR2:
|
| 592 |
case TAHVO_REG_NOPR:
|
| 593 |
case TAHVO_REG_FRR:
|
| 594 |
break;
|
| 595 |
|
| 596 |
default:
|
| 597 |
cpu_abort(cpu_single_env, "%s: bad register %02x\n",
|
| 598 |
__FUNCTION__, reg); |
| 599 |
} |
| 600 |
} |
| 601 |
|
| 602 |
static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val) |
| 603 |
{
|
| 604 |
struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) opaque; |
| 605 |
|
| 606 |
if (rw)
|
| 607 |
*val = tahvo_read(s, reg); |
| 608 |
else
|
| 609 |
tahvo_write(s, reg, *val); |
| 610 |
} |
| 611 |
|
| 612 |
void *tahvo_init(qemu_irq irq, int betty) |
| 613 |
{
|
| 614 |
struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) qemu_mallocz(sizeof(*s)); |
| 615 |
|
| 616 |
s->irq = irq; |
| 617 |
s->irqen = 0xffff;
|
| 618 |
s->irqst = 0x0000;
|
| 619 |
s->is_betty = !!betty; |
| 620 |
|
| 621 |
s->cbus.opaque = s; |
| 622 |
s->cbus.io = tahvo_io; |
| 623 |
s->cbus.addr = 2;
|
| 624 |
|
| 625 |
return &s->cbus;
|
| 626 |
} |