Revision 5c2b87e3 hw/piix_pci.c
| b/hw/piix_pci.c | ||
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/* PIIX3 PCI to ISA bridge */ |
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PCIDevice *piix3_dev; |
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PCIDevice *piix4_dev; |
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/* just used for simpler irq handling. */ |
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#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
| ... | ... | |
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pci_conf[0xae] = 0x00; |
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} |
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static void piix4_reset(PCIDevice *d) |
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{
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uint8_t *pci_conf = d->config; |
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pci_conf[0x04] = 0x07; // master, memory and I/O |
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pci_conf[0x05] = 0x00; |
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pci_conf[0x06] = 0x00; |
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pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
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pci_conf[0x4c] = 0x4d; |
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pci_conf[0x4e] = 0x03; |
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pci_conf[0x4f] = 0x00; |
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pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 |
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pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 |
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pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 |
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pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 |
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pci_conf[0x69] = 0x02; |
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pci_conf[0x70] = 0x80; |
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pci_conf[0x76] = 0x0c; |
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pci_conf[0x77] = 0x0c; |
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pci_conf[0x78] = 0x02; |
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pci_conf[0x79] = 0x00; |
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pci_conf[0x80] = 0x00; |
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pci_conf[0x82] = 0x00; |
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pci_conf[0xa0] = 0x08; |
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pci_conf[0xa0] = 0x08; |
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pci_conf[0xa2] = 0x00; |
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pci_conf[0xa3] = 0x00; |
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pci_conf[0xa4] = 0x00; |
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pci_conf[0xa5] = 0x00; |
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pci_conf[0xa6] = 0x00; |
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pci_conf[0xa7] = 0x00; |
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pci_conf[0xa8] = 0x0f; |
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pci_conf[0xaa] = 0x00; |
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pci_conf[0xab] = 0x00; |
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pci_conf[0xac] = 0x00; |
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pci_conf[0xae] = 0x00; |
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} |
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static void piix_save(QEMUFile* f, void *opaque) |
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{
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PCIDevice *d = opaque; |
| ... | ... | |
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piix3_reset(d); |
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return d->devfn; |
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} |
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int piix4_init(PCIBus *bus, int devfn) |
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{
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PCIDevice *d; |
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uint8_t *pci_conf; |
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d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice), |
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devfn, NULL, NULL); |
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register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
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piix4_dev = d; |
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pci_conf = d->config; |
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pci_conf[0x00] = 0x86; // Intel |
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pci_conf[0x01] = 0x80; |
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pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge |
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pci_conf[0x03] = 0x71; |
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pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
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pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
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pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
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piix4_reset(d); |
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return d->devfn; |
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} |
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