root / hw / mips_mipssim.c @ 5c3234c6
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1 | f0fc6f8f | ths | /*
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2 | f0fc6f8f | ths | * QEMU/mipssim emulation
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3 | f0fc6f8f | ths | *
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4 | f0fc6f8f | ths | * Emulates a very simple machine model similiar to the one use by the
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5 | f0fc6f8f | ths | * proprietary MIPS emulator.
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6 | a79ee211 | ths | *
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7 | a79ee211 | ths | * Copyright (c) 2007 Thiemo Seufer
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8 | a79ee211 | ths | *
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9 | a79ee211 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | a79ee211 | ths | * of this software and associated documentation files (the "Software"), to deal
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11 | a79ee211 | ths | * in the Software without restriction, including without limitation the rights
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12 | a79ee211 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | a79ee211 | ths | * copies of the Software, and to permit persons to whom the Software is
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14 | a79ee211 | ths | * furnished to do so, subject to the following conditions:
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15 | a79ee211 | ths | *
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16 | a79ee211 | ths | * The above copyright notice and this permission notice shall be included in
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17 | a79ee211 | ths | * all copies or substantial portions of the Software.
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18 | a79ee211 | ths | *
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19 | a79ee211 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | a79ee211 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | a79ee211 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | a79ee211 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | a79ee211 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | a79ee211 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | a79ee211 | ths | * THE SOFTWARE.
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26 | f0fc6f8f | ths | */
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27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "mips.h" |
29 | b970ea8f | Blue Swirl | #include "mips_cpudevs.h" |
30 | 87ecb68b | pbrook | #include "pc.h" |
31 | 87ecb68b | pbrook | #include "isa.h" |
32 | 87ecb68b | pbrook | #include "net.h" |
33 | 87ecb68b | pbrook | #include "sysemu.h" |
34 | 87ecb68b | pbrook | #include "boards.h" |
35 | bba831e8 | Paul Brook | #include "mips-bios.h" |
36 | ca20cf32 | Blue Swirl | #include "loader.h" |
37 | ca20cf32 | Blue Swirl | #include "elf.h" |
38 | f0fc6f8f | ths | |
39 | 7df526e3 | ths | static struct _loaderparams { |
40 | 7df526e3 | ths | int ram_size;
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41 | 7df526e3 | ths | const char *kernel_filename; |
42 | 7df526e3 | ths | const char *kernel_cmdline; |
43 | 7df526e3 | ths | const char *initrd_filename; |
44 | 7df526e3 | ths | } loaderparams; |
45 | 7df526e3 | ths | |
46 | e16ad5b0 | Aurelien Jarno | typedef struct ResetData { |
47 | e16ad5b0 | Aurelien Jarno | CPUState *env; |
48 | e16ad5b0 | Aurelien Jarno | uint64_t vector; |
49 | e16ad5b0 | Aurelien Jarno | } ResetData; |
50 | e16ad5b0 | Aurelien Jarno | |
51 | e16ad5b0 | Aurelien Jarno | static int64_t load_kernel(void) |
52 | f0fc6f8f | ths | { |
53 | 409dbce5 | Aurelien Jarno | int64_t entry, kernel_high; |
54 | f0fc6f8f | ths | long kernel_size;
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55 | f0fc6f8f | ths | long initrd_size;
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56 | c227f099 | Anthony Liguori | ram_addr_t initrd_offset; |
57 | ca20cf32 | Blue Swirl | int big_endian;
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58 | ca20cf32 | Blue Swirl | |
59 | ca20cf32 | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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60 | ca20cf32 | Blue Swirl | big_endian = 1;
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61 | ca20cf32 | Blue Swirl | #else
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62 | ca20cf32 | Blue Swirl | big_endian = 0;
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63 | ca20cf32 | Blue Swirl | #endif
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64 | f0fc6f8f | ths | |
65 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, |
66 | 409dbce5 | Aurelien Jarno | NULL, (uint64_t *)&entry, NULL, |
67 | 409dbce5 | Aurelien Jarno | (uint64_t *)&kernel_high, big_endian, |
68 | 409dbce5 | Aurelien Jarno | ELF_MACHINE, 1);
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69 | f0fc6f8f | ths | if (kernel_size >= 0) { |
70 | f0fc6f8f | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
71 | f0fc6f8f | ths | entry = (int32_t)entry; |
72 | f0fc6f8f | ths | } else {
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73 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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74 | 7df526e3 | ths | loaderparams.kernel_filename); |
75 | f0fc6f8f | ths | exit(1);
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76 | f0fc6f8f | ths | } |
77 | f0fc6f8f | ths | |
78 | f0fc6f8f | ths | /* load initrd */
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79 | f0fc6f8f | ths | initrd_size = 0;
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80 | f0fc6f8f | ths | initrd_offset = 0;
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81 | 7df526e3 | ths | if (loaderparams.initrd_filename) {
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82 | 7df526e3 | ths | initrd_size = get_image_size (loaderparams.initrd_filename); |
83 | f0fc6f8f | ths | if (initrd_size > 0) { |
84 | f0fc6f8f | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
85 | 7df526e3 | ths | if (initrd_offset + initrd_size > loaderparams.ram_size) {
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86 | f0fc6f8f | ths | fprintf(stderr, |
87 | f0fc6f8f | ths | "qemu: memory too small for initial ram disk '%s'\n",
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88 | 7df526e3 | ths | loaderparams.initrd_filename); |
89 | f0fc6f8f | ths | exit(1);
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90 | f0fc6f8f | ths | } |
91 | dcac9679 | pbrook | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
92 | dcac9679 | pbrook | initrd_offset, loaderparams.ram_size - initrd_offset); |
93 | f0fc6f8f | ths | } |
94 | f0fc6f8f | ths | if (initrd_size == (target_ulong) -1) { |
95 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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96 | 7df526e3 | ths | loaderparams.initrd_filename); |
97 | f0fc6f8f | ths | exit(1);
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98 | f0fc6f8f | ths | } |
99 | f0fc6f8f | ths | } |
100 | e16ad5b0 | Aurelien Jarno | return entry;
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101 | f0fc6f8f | ths | } |
102 | f0fc6f8f | ths | |
103 | f0fc6f8f | ths | static void main_cpu_reset(void *opaque) |
104 | f0fc6f8f | ths | { |
105 | e16ad5b0 | Aurelien Jarno | ResetData *s = (ResetData *)opaque; |
106 | e16ad5b0 | Aurelien Jarno | CPUState *env = s->env; |
107 | f0fc6f8f | ths | |
108 | e16ad5b0 | Aurelien Jarno | cpu_reset(env); |
109 | aecf1376 | Nathan Froyd | env->active_tc.PC = s->vector & ~(target_ulong)1;
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110 | aecf1376 | Nathan Froyd | if (s->vector & 1) { |
111 | aecf1376 | Nathan Froyd | env->hflags |= MIPS_HFLAG_M16; |
112 | aecf1376 | Nathan Froyd | } |
113 | f0fc6f8f | ths | } |
114 | f0fc6f8f | ths | |
115 | f0fc6f8f | ths | static void |
116 | c227f099 | Anthony Liguori | mips_mipssim_init (ram_addr_t ram_size, |
117 | 3023f332 | aliguori | const char *boot_device, |
118 | f0fc6f8f | ths | const char *kernel_filename, const char *kernel_cmdline, |
119 | f0fc6f8f | ths | const char *initrd_filename, const char *cpu_model) |
120 | f0fc6f8f | ths | { |
121 | 5cea8590 | Paul Brook | char *filename;
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122 | c227f099 | Anthony Liguori | ram_addr_t ram_offset; |
123 | c227f099 | Anthony Liguori | ram_addr_t bios_offset; |
124 | f0fc6f8f | ths | CPUState *env; |
125 | e16ad5b0 | Aurelien Jarno | ResetData *reset_info; |
126 | b5334159 | ths | int bios_size;
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127 | f0fc6f8f | ths | |
128 | f0fc6f8f | ths | /* Init CPUs. */
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129 | f0fc6f8f | ths | if (cpu_model == NULL) { |
130 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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131 | f0fc6f8f | ths | cpu_model = "5Kf";
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132 | f0fc6f8f | ths | #else
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133 | f0fc6f8f | ths | cpu_model = "24Kf";
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134 | f0fc6f8f | ths | #endif
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135 | f0fc6f8f | ths | } |
136 | aaed909a | bellard | env = cpu_init(cpu_model); |
137 | aaed909a | bellard | if (!env) {
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138 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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139 | aaed909a | bellard | exit(1);
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140 | aaed909a | bellard | } |
141 | e16ad5b0 | Aurelien Jarno | reset_info = qemu_mallocz(sizeof(ResetData));
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142 | e16ad5b0 | Aurelien Jarno | reset_info->env = env; |
143 | e16ad5b0 | Aurelien Jarno | reset_info->vector = env->active_tc.PC; |
144 | e16ad5b0 | Aurelien Jarno | qemu_register_reset(main_cpu_reset, reset_info); |
145 | f0fc6f8f | ths | |
146 | f0fc6f8f | ths | /* Allocate RAM. */
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147 | 1724f049 | Alex Williamson | ram_offset = qemu_ram_alloc(NULL, "mips_mipssim.ram", ram_size); |
148 | 1724f049 | Alex Williamson | bios_offset = qemu_ram_alloc(NULL, "mips_mipssim.bios", BIOS_SIZE); |
149 | f0fc6f8f | ths | |
150 | dcac9679 | pbrook | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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151 | dcac9679 | pbrook | |
152 | dcac9679 | pbrook | /* Map the BIOS / boot exception handler. */
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153 | dcac9679 | pbrook | cpu_register_physical_memory(0x1fc00000LL,
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154 | dcac9679 | pbrook | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
155 | f0fc6f8f | ths | /* Load a BIOS / boot exception handler image. */
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156 | f0fc6f8f | ths | if (bios_name == NULL) |
157 | f0fc6f8f | ths | bios_name = BIOS_FILENAME; |
158 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
159 | 5cea8590 | Paul Brook | if (filename) {
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160 | 5cea8590 | Paul Brook | bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
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161 | 5cea8590 | Paul Brook | qemu_free(filename); |
162 | 5cea8590 | Paul Brook | } else {
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163 | 5cea8590 | Paul Brook | bios_size = -1;
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164 | 5cea8590 | Paul Brook | } |
165 | b5334159 | ths | if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) { |
166 | f0fc6f8f | ths | /* Bail out if we have neither a kernel image nor boot vector code. */
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167 | f0fc6f8f | ths | fprintf(stderr, |
168 | f0fc6f8f | ths | "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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169 | 5cea8590 | Paul Brook | filename); |
170 | f0fc6f8f | ths | exit(1);
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171 | f0fc6f8f | ths | } else {
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172 | b5334159 | ths | /* We have a boot vector start address. */
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173 | b5dc7732 | ths | env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
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174 | f0fc6f8f | ths | } |
175 | f0fc6f8f | ths | |
176 | f0fc6f8f | ths | if (kernel_filename) {
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177 | 7df526e3 | ths | loaderparams.ram_size = ram_size; |
178 | 7df526e3 | ths | loaderparams.kernel_filename = kernel_filename; |
179 | 7df526e3 | ths | loaderparams.kernel_cmdline = kernel_cmdline; |
180 | 7df526e3 | ths | loaderparams.initrd_filename = initrd_filename; |
181 | e16ad5b0 | Aurelien Jarno | reset_info->vector = load_kernel(); |
182 | f0fc6f8f | ths | } |
183 | f0fc6f8f | ths | |
184 | f0fc6f8f | ths | /* Init CPU internal devices. */
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185 | f0fc6f8f | ths | cpu_mips_irq_init_cpu(env); |
186 | f0fc6f8f | ths | cpu_mips_clock_init(env); |
187 | f0fc6f8f | ths | |
188 | f0fc6f8f | ths | /* Register 64 KB of ISA IO space at 0x1fd00000. */
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189 | 968d683c | Alexander Graf | isa_mmio_init(0x1fd00000, 0x00010000); |
190 | f0fc6f8f | ths | |
191 | f0fc6f8f | ths | /* A single 16450 sits at offset 0x3f8. It is attached to
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192 | f0fc6f8f | ths | MIPS CPU INT2, which is interrupt 4. */
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193 | f0fc6f8f | ths | if (serial_hds[0]) |
194 | b6cd0ea1 | aurel32 | serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]); |
195 | f0fc6f8f | ths | |
196 | 0ae18cee | aliguori | if (nd_table[0].vlan) |
197 | 0ae18cee | aliguori | /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
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198 | 0ae18cee | aliguori | mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
199 | f0fc6f8f | ths | } |
200 | f0fc6f8f | ths | |
201 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_mipssim_machine = {
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202 | eec2743e | ths | .name = "mipssim",
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203 | eec2743e | ths | .desc = "MIPS MIPSsim platform",
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204 | eec2743e | ths | .init = mips_mipssim_init, |
205 | f0fc6f8f | ths | }; |
206 | f80f9ec9 | Anthony Liguori | |
207 | f80f9ec9 | Anthony Liguori | static void mips_mipssim_machine_init(void) |
208 | f80f9ec9 | Anthony Liguori | { |
209 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_mipssim_machine); |
210 | f80f9ec9 | Anthony Liguori | } |
211 | f80f9ec9 | Anthony Liguori | |
212 | f80f9ec9 | Anthony Liguori | machine_init(mips_mipssim_machine_init); |