root / hw / serial.c @ 5c3234c6
History | View | Annotate | Download (28.9 kB)
1 |
/*
|
---|---|
2 |
* QEMU 16550A UART emulation
|
3 |
*
|
4 |
* Copyright (c) 2003-2004 Fabrice Bellard
|
5 |
* Copyright (c) 2008 Citrix Systems, Inc.
|
6 |
*
|
7 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 |
* of this software and associated documentation files (the "Software"), to deal
|
9 |
* in the Software without restriction, including without limitation the rights
|
10 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 |
* copies of the Software, and to permit persons to whom the Software is
|
12 |
* furnished to do so, subject to the following conditions:
|
13 |
*
|
14 |
* The above copyright notice and this permission notice shall be included in
|
15 |
* all copies or substantial portions of the Software.
|
16 |
*
|
17 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 |
* THE SOFTWARE.
|
24 |
*/
|
25 |
#include "hw.h" |
26 |
#include "qemu-char.h" |
27 |
#include "isa.h" |
28 |
#include "pc.h" |
29 |
#include "qemu-timer.h" |
30 |
#include "sysemu.h" |
31 |
|
32 |
//#define DEBUG_SERIAL
|
33 |
|
34 |
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
35 |
|
36 |
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
37 |
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
38 |
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
39 |
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
40 |
|
41 |
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
42 |
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
43 |
|
44 |
#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
45 |
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
46 |
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
47 |
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
48 |
#define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
49 |
|
50 |
#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ |
51 |
#define UART_IIR_FE 0xC0 /* Fifo enabled */ |
52 |
|
53 |
/*
|
54 |
* These are the definitions for the Modem Control Register
|
55 |
*/
|
56 |
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
57 |
#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
58 |
#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
59 |
#define UART_MCR_RTS 0x02 /* RTS complement */ |
60 |
#define UART_MCR_DTR 0x01 /* DTR complement */ |
61 |
|
62 |
/*
|
63 |
* These are the definitions for the Modem Status Register
|
64 |
*/
|
65 |
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
66 |
#define UART_MSR_RI 0x40 /* Ring Indicator */ |
67 |
#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
68 |
#define UART_MSR_CTS 0x10 /* Clear to Send */ |
69 |
#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
70 |
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
71 |
#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
72 |
#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
73 |
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
74 |
|
75 |
#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
76 |
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
77 |
#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
78 |
#define UART_LSR_FE 0x08 /* Frame error indicator */ |
79 |
#define UART_LSR_PE 0x04 /* Parity error indicator */ |
80 |
#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
81 |
#define UART_LSR_DR 0x01 /* Receiver data ready */ |
82 |
#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
83 |
|
84 |
/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
|
85 |
|
86 |
#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ |
87 |
#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ |
88 |
#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ |
89 |
#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ |
90 |
|
91 |
#define UART_FCR_DMS 0x08 /* DMA Mode Select */ |
92 |
#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ |
93 |
#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ |
94 |
#define UART_FCR_FE 0x01 /* FIFO Enable */ |
95 |
|
96 |
#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */ |
97 |
|
98 |
#define XMIT_FIFO 0 |
99 |
#define RECV_FIFO 1 |
100 |
#define MAX_XMIT_RETRY 4 |
101 |
|
102 |
#ifdef DEBUG_SERIAL
|
103 |
#define DPRINTF(fmt, ...) \
|
104 |
do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) |
105 |
#else
|
106 |
#define DPRINTF(fmt, ...) \
|
107 |
do {} while (0) |
108 |
#endif
|
109 |
|
110 |
typedef struct SerialFIFO { |
111 |
uint8_t data[UART_FIFO_LENGTH]; |
112 |
uint8_t count; |
113 |
uint8_t itl; /* Interrupt Trigger Level */
|
114 |
uint8_t tail; |
115 |
uint8_t head; |
116 |
} SerialFIFO; |
117 |
|
118 |
struct SerialState {
|
119 |
uint16_t divider; |
120 |
uint8_t rbr; /* receive register */
|
121 |
uint8_t thr; /* transmit holding register */
|
122 |
uint8_t tsr; /* transmit shift register */
|
123 |
uint8_t ier; |
124 |
uint8_t iir; /* read only */
|
125 |
uint8_t lcr; |
126 |
uint8_t mcr; |
127 |
uint8_t lsr; /* read only */
|
128 |
uint8_t msr; /* read only */
|
129 |
uint8_t scr; |
130 |
uint8_t fcr; |
131 |
uint8_t fcr_vmstate; /* we can't write directly this value
|
132 |
it has side effects */
|
133 |
/* NOTE: this hidden state is necessary for tx irq generation as
|
134 |
it can be reset while reading iir */
|
135 |
int thr_ipending;
|
136 |
qemu_irq irq; |
137 |
CharDriverState *chr; |
138 |
int last_break_enable;
|
139 |
int it_shift;
|
140 |
int baudbase;
|
141 |
int tsr_retry;
|
142 |
|
143 |
uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
|
144 |
SerialFIFO recv_fifo; |
145 |
SerialFIFO xmit_fifo; |
146 |
|
147 |
struct QEMUTimer *fifo_timeout_timer;
|
148 |
int timeout_ipending; /* timeout interrupt pending state */ |
149 |
struct QEMUTimer *transmit_timer;
|
150 |
|
151 |
|
152 |
uint64_t char_transmit_time; /* time to transmit a char in ticks*/
|
153 |
int poll_msl;
|
154 |
|
155 |
struct QEMUTimer *modem_status_poll;
|
156 |
}; |
157 |
|
158 |
typedef struct ISASerialState { |
159 |
ISADevice dev; |
160 |
uint32_t index; |
161 |
uint32_t iobase; |
162 |
uint32_t isairq; |
163 |
SerialState state; |
164 |
} ISASerialState; |
165 |
|
166 |
static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
167 |
|
168 |
static void fifo_clear(SerialState *s, int fifo) |
169 |
{ |
170 |
SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
171 |
memset(f->data, 0, UART_FIFO_LENGTH);
|
172 |
f->count = 0;
|
173 |
f->head = 0;
|
174 |
f->tail = 0;
|
175 |
} |
176 |
|
177 |
static int fifo_put(SerialState *s, int fifo, uint8_t chr) |
178 |
{ |
179 |
SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
180 |
|
181 |
/* Receive overruns do not overwrite FIFO contents. */
|
182 |
if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
|
183 |
|
184 |
f->data[f->head++] = chr; |
185 |
|
186 |
if (f->head == UART_FIFO_LENGTH)
|
187 |
f->head = 0;
|
188 |
} |
189 |
|
190 |
if (f->count < UART_FIFO_LENGTH)
|
191 |
f->count++; |
192 |
else if (fifo == RECV_FIFO) |
193 |
s->lsr |= UART_LSR_OE; |
194 |
|
195 |
return 1; |
196 |
} |
197 |
|
198 |
static uint8_t fifo_get(SerialState *s, int fifo) |
199 |
{ |
200 |
SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
201 |
uint8_t c; |
202 |
|
203 |
if(f->count == 0) |
204 |
return 0; |
205 |
|
206 |
c = f->data[f->tail++]; |
207 |
if (f->tail == UART_FIFO_LENGTH)
|
208 |
f->tail = 0;
|
209 |
f->count--; |
210 |
|
211 |
return c;
|
212 |
} |
213 |
|
214 |
static void serial_update_irq(SerialState *s) |
215 |
{ |
216 |
uint8_t tmp_iir = UART_IIR_NO_INT; |
217 |
|
218 |
if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
|
219 |
tmp_iir = UART_IIR_RLSI; |
220 |
} else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { |
221 |
/* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
|
222 |
* this is not in the specification but is observed on existing
|
223 |
* hardware. */
|
224 |
tmp_iir = UART_IIR_CTI; |
225 |
} else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && |
226 |
(!(s->fcr & UART_FCR_FE) || |
227 |
s->recv_fifo.count >= s->recv_fifo.itl)) { |
228 |
tmp_iir = UART_IIR_RDI; |
229 |
} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
230 |
tmp_iir = UART_IIR_THRI; |
231 |
} else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { |
232 |
tmp_iir = UART_IIR_MSI; |
233 |
} |
234 |
|
235 |
s->iir = tmp_iir | (s->iir & 0xF0);
|
236 |
|
237 |
if (tmp_iir != UART_IIR_NO_INT) {
|
238 |
qemu_irq_raise(s->irq); |
239 |
} else {
|
240 |
qemu_irq_lower(s->irq); |
241 |
} |
242 |
} |
243 |
|
244 |
static void serial_update_parameters(SerialState *s) |
245 |
{ |
246 |
int speed, parity, data_bits, stop_bits, frame_size;
|
247 |
QEMUSerialSetParams ssp; |
248 |
|
249 |
if (s->divider == 0) |
250 |
return;
|
251 |
|
252 |
/* Start bit. */
|
253 |
frame_size = 1;
|
254 |
if (s->lcr & 0x08) { |
255 |
/* Parity bit. */
|
256 |
frame_size++; |
257 |
if (s->lcr & 0x10) |
258 |
parity = 'E';
|
259 |
else
|
260 |
parity = 'O';
|
261 |
} else {
|
262 |
parity = 'N';
|
263 |
} |
264 |
if (s->lcr & 0x04) |
265 |
stop_bits = 2;
|
266 |
else
|
267 |
stop_bits = 1;
|
268 |
|
269 |
data_bits = (s->lcr & 0x03) + 5; |
270 |
frame_size += data_bits + stop_bits; |
271 |
speed = s->baudbase / s->divider; |
272 |
ssp.speed = speed; |
273 |
ssp.parity = parity; |
274 |
ssp.data_bits = data_bits; |
275 |
ssp.stop_bits = stop_bits; |
276 |
s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; |
277 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
278 |
|
279 |
DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
|
280 |
speed, parity, data_bits, stop_bits); |
281 |
} |
282 |
|
283 |
static void serial_update_msl(SerialState *s) |
284 |
{ |
285 |
uint8_t omsr; |
286 |
int flags;
|
287 |
|
288 |
qemu_del_timer(s->modem_status_poll); |
289 |
|
290 |
if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
|
291 |
s->poll_msl = -1;
|
292 |
return;
|
293 |
} |
294 |
|
295 |
omsr = s->msr; |
296 |
|
297 |
s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; |
298 |
s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; |
299 |
s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; |
300 |
s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; |
301 |
|
302 |
if (s->msr != omsr) {
|
303 |
/* Set delta bits */
|
304 |
s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); |
305 |
/* UART_MSR_TERI only if change was from 1 -> 0 */
|
306 |
if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
|
307 |
s->msr &= ~UART_MSR_TERI; |
308 |
serial_update_irq(s); |
309 |
} |
310 |
|
311 |
/* The real 16550A apparently has a 250ns response latency to line status changes.
|
312 |
We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
|
313 |
|
314 |
if (s->poll_msl)
|
315 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
|
316 |
} |
317 |
|
318 |
static void serial_xmit(void *opaque) |
319 |
{ |
320 |
SerialState *s = opaque; |
321 |
uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock); |
322 |
|
323 |
if (s->tsr_retry <= 0) { |
324 |
if (s->fcr & UART_FCR_FE) {
|
325 |
s->tsr = fifo_get(s,XMIT_FIFO); |
326 |
if (!s->xmit_fifo.count)
|
327 |
s->lsr |= UART_LSR_THRE; |
328 |
} else {
|
329 |
s->tsr = s->thr; |
330 |
s->lsr |= UART_LSR_THRE; |
331 |
} |
332 |
} |
333 |
|
334 |
if (s->mcr & UART_MCR_LOOP) {
|
335 |
/* in loopback mode, say that we just received a char */
|
336 |
serial_receive1(s, &s->tsr, 1);
|
337 |
} else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) { |
338 |
if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { |
339 |
s->tsr_retry++; |
340 |
qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time); |
341 |
return;
|
342 |
} else if (s->poll_msl < 0) { |
343 |
/* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
|
344 |
drop any further failed writes instantly, until we get one that goes through.
|
345 |
This is to prevent guests that log to unconnected pipes or pty's from stalling. */
|
346 |
s->tsr_retry = -1;
|
347 |
} |
348 |
} |
349 |
else {
|
350 |
s->tsr_retry = 0;
|
351 |
} |
352 |
|
353 |
s->last_xmit_ts = qemu_get_clock_ns(vm_clock); |
354 |
if (!(s->lsr & UART_LSR_THRE))
|
355 |
qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time); |
356 |
|
357 |
if (s->lsr & UART_LSR_THRE) {
|
358 |
s->lsr |= UART_LSR_TEMT; |
359 |
s->thr_ipending = 1;
|
360 |
serial_update_irq(s); |
361 |
} |
362 |
} |
363 |
|
364 |
|
365 |
static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
366 |
{ |
367 |
SerialState *s = opaque; |
368 |
|
369 |
addr &= 7;
|
370 |
DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val);
|
371 |
switch(addr) {
|
372 |
default:
|
373 |
case 0: |
374 |
if (s->lcr & UART_LCR_DLAB) {
|
375 |
s->divider = (s->divider & 0xff00) | val;
|
376 |
serial_update_parameters(s); |
377 |
} else {
|
378 |
s->thr = (uint8_t) val; |
379 |
if(s->fcr & UART_FCR_FE) {
|
380 |
fifo_put(s, XMIT_FIFO, s->thr); |
381 |
s->thr_ipending = 0;
|
382 |
s->lsr &= ~UART_LSR_TEMT; |
383 |
s->lsr &= ~UART_LSR_THRE; |
384 |
serial_update_irq(s); |
385 |
} else {
|
386 |
s->thr_ipending = 0;
|
387 |
s->lsr &= ~UART_LSR_THRE; |
388 |
serial_update_irq(s); |
389 |
} |
390 |
serial_xmit(s); |
391 |
} |
392 |
break;
|
393 |
case 1: |
394 |
if (s->lcr & UART_LCR_DLAB) {
|
395 |
s->divider = (s->divider & 0x00ff) | (val << 8); |
396 |
serial_update_parameters(s); |
397 |
} else {
|
398 |
s->ier = val & 0x0f;
|
399 |
/* If the backend device is a real serial port, turn polling of the modem
|
400 |
status lines on physical port on or off depending on UART_IER_MSI state */
|
401 |
if (s->poll_msl >= 0) { |
402 |
if (s->ier & UART_IER_MSI) {
|
403 |
s->poll_msl = 1;
|
404 |
serial_update_msl(s); |
405 |
} else {
|
406 |
qemu_del_timer(s->modem_status_poll); |
407 |
s->poll_msl = 0;
|
408 |
} |
409 |
} |
410 |
if (s->lsr & UART_LSR_THRE) {
|
411 |
s->thr_ipending = 1;
|
412 |
serial_update_irq(s); |
413 |
} |
414 |
} |
415 |
break;
|
416 |
case 2: |
417 |
val = val & 0xFF;
|
418 |
|
419 |
if (s->fcr == val)
|
420 |
break;
|
421 |
|
422 |
/* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
|
423 |
if ((val ^ s->fcr) & UART_FCR_FE)
|
424 |
val |= UART_FCR_XFR | UART_FCR_RFR; |
425 |
|
426 |
/* FIFO clear */
|
427 |
|
428 |
if (val & UART_FCR_RFR) {
|
429 |
qemu_del_timer(s->fifo_timeout_timer); |
430 |
s->timeout_ipending=0;
|
431 |
fifo_clear(s,RECV_FIFO); |
432 |
} |
433 |
|
434 |
if (val & UART_FCR_XFR) {
|
435 |
fifo_clear(s,XMIT_FIFO); |
436 |
} |
437 |
|
438 |
if (val & UART_FCR_FE) {
|
439 |
s->iir |= UART_IIR_FE; |
440 |
/* Set RECV_FIFO trigger Level */
|
441 |
switch (val & 0xC0) { |
442 |
case UART_FCR_ITL_1:
|
443 |
s->recv_fifo.itl = 1;
|
444 |
break;
|
445 |
case UART_FCR_ITL_2:
|
446 |
s->recv_fifo.itl = 4;
|
447 |
break;
|
448 |
case UART_FCR_ITL_3:
|
449 |
s->recv_fifo.itl = 8;
|
450 |
break;
|
451 |
case UART_FCR_ITL_4:
|
452 |
s->recv_fifo.itl = 14;
|
453 |
break;
|
454 |
} |
455 |
} else
|
456 |
s->iir &= ~UART_IIR_FE; |
457 |
|
458 |
/* Set fcr - or at least the bits in it that are supposed to "stick" */
|
459 |
s->fcr = val & 0xC9;
|
460 |
serial_update_irq(s); |
461 |
break;
|
462 |
case 3: |
463 |
{ |
464 |
int break_enable;
|
465 |
s->lcr = val; |
466 |
serial_update_parameters(s); |
467 |
break_enable = (val >> 6) & 1; |
468 |
if (break_enable != s->last_break_enable) {
|
469 |
s->last_break_enable = break_enable; |
470 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
471 |
&break_enable); |
472 |
} |
473 |
} |
474 |
break;
|
475 |
case 4: |
476 |
{ |
477 |
int flags;
|
478 |
int old_mcr = s->mcr;
|
479 |
s->mcr = val & 0x1f;
|
480 |
if (val & UART_MCR_LOOP)
|
481 |
break;
|
482 |
|
483 |
if (s->poll_msl >= 0 && old_mcr != s->mcr) { |
484 |
|
485 |
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); |
486 |
|
487 |
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); |
488 |
|
489 |
if (val & UART_MCR_RTS)
|
490 |
flags |= CHR_TIOCM_RTS; |
491 |
if (val & UART_MCR_DTR)
|
492 |
flags |= CHR_TIOCM_DTR; |
493 |
|
494 |
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
495 |
/* Update the modem status after a one-character-send wait-time, since there may be a response
|
496 |
from the device/computer at the other end of the serial line */
|
497 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time); |
498 |
} |
499 |
} |
500 |
break;
|
501 |
case 5: |
502 |
break;
|
503 |
case 6: |
504 |
break;
|
505 |
case 7: |
506 |
s->scr = val; |
507 |
break;
|
508 |
} |
509 |
} |
510 |
|
511 |
static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
512 |
{ |
513 |
SerialState *s = opaque; |
514 |
uint32_t ret; |
515 |
|
516 |
addr &= 7;
|
517 |
switch(addr) {
|
518 |
default:
|
519 |
case 0: |
520 |
if (s->lcr & UART_LCR_DLAB) {
|
521 |
ret = s->divider & 0xff;
|
522 |
} else {
|
523 |
if(s->fcr & UART_FCR_FE) {
|
524 |
ret = fifo_get(s,RECV_FIFO); |
525 |
if (s->recv_fifo.count == 0) |
526 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
527 |
else
|
528 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
|
529 |
s->timeout_ipending = 0;
|
530 |
} else {
|
531 |
ret = s->rbr; |
532 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
533 |
} |
534 |
serial_update_irq(s); |
535 |
if (!(s->mcr & UART_MCR_LOOP)) {
|
536 |
/* in loopback mode, don't receive any data */
|
537 |
qemu_chr_accept_input(s->chr); |
538 |
} |
539 |
} |
540 |
break;
|
541 |
case 1: |
542 |
if (s->lcr & UART_LCR_DLAB) {
|
543 |
ret = (s->divider >> 8) & 0xff; |
544 |
} else {
|
545 |
ret = s->ier; |
546 |
} |
547 |
break;
|
548 |
case 2: |
549 |
ret = s->iir; |
550 |
if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
|
551 |
s->thr_ipending = 0;
|
552 |
serial_update_irq(s); |
553 |
} |
554 |
break;
|
555 |
case 3: |
556 |
ret = s->lcr; |
557 |
break;
|
558 |
case 4: |
559 |
ret = s->mcr; |
560 |
break;
|
561 |
case 5: |
562 |
ret = s->lsr; |
563 |
/* Clear break and overrun interrupts */
|
564 |
if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
|
565 |
s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); |
566 |
serial_update_irq(s); |
567 |
} |
568 |
break;
|
569 |
case 6: |
570 |
if (s->mcr & UART_MCR_LOOP) {
|
571 |
/* in loopback, the modem output pins are connected to the
|
572 |
inputs */
|
573 |
ret = (s->mcr & 0x0c) << 4; |
574 |
ret |= (s->mcr & 0x02) << 3; |
575 |
ret |= (s->mcr & 0x01) << 5; |
576 |
} else {
|
577 |
if (s->poll_msl >= 0) |
578 |
serial_update_msl(s); |
579 |
ret = s->msr; |
580 |
/* Clear delta bits & msr int after read, if they were set */
|
581 |
if (s->msr & UART_MSR_ANY_DELTA) {
|
582 |
s->msr &= 0xF0;
|
583 |
serial_update_irq(s); |
584 |
} |
585 |
} |
586 |
break;
|
587 |
case 7: |
588 |
ret = s->scr; |
589 |
break;
|
590 |
} |
591 |
DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret);
|
592 |
return ret;
|
593 |
} |
594 |
|
595 |
static int serial_can_receive(SerialState *s) |
596 |
{ |
597 |
if(s->fcr & UART_FCR_FE) {
|
598 |
if(s->recv_fifo.count < UART_FIFO_LENGTH)
|
599 |
/* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
|
600 |
advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
|
601 |
effectively overriding the ITL that the guest has set. */
|
602 |
return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1; |
603 |
else
|
604 |
return 0; |
605 |
} else {
|
606 |
return !(s->lsr & UART_LSR_DR);
|
607 |
} |
608 |
} |
609 |
|
610 |
static void serial_receive_break(SerialState *s) |
611 |
{ |
612 |
s->rbr = 0;
|
613 |
/* When the LSR_DR is set a null byte is pushed into the fifo */
|
614 |
fifo_put(s, RECV_FIFO, '\0');
|
615 |
s->lsr |= UART_LSR_BI | UART_LSR_DR; |
616 |
serial_update_irq(s); |
617 |
} |
618 |
|
619 |
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
|
620 |
static void fifo_timeout_int (void *opaque) { |
621 |
SerialState *s = opaque; |
622 |
if (s->recv_fifo.count) {
|
623 |
s->timeout_ipending = 1;
|
624 |
serial_update_irq(s); |
625 |
} |
626 |
} |
627 |
|
628 |
static int serial_can_receive1(void *opaque) |
629 |
{ |
630 |
SerialState *s = opaque; |
631 |
return serial_can_receive(s);
|
632 |
} |
633 |
|
634 |
static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
635 |
{ |
636 |
SerialState *s = opaque; |
637 |
if(s->fcr & UART_FCR_FE) {
|
638 |
int i;
|
639 |
for (i = 0; i < size; i++) { |
640 |
fifo_put(s, RECV_FIFO, buf[i]); |
641 |
} |
642 |
s->lsr |= UART_LSR_DR; |
643 |
/* call the timeout receive callback in 4 char transmit time */
|
644 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
|
645 |
} else {
|
646 |
if (s->lsr & UART_LSR_DR)
|
647 |
s->lsr |= UART_LSR_OE; |
648 |
s->rbr = buf[0];
|
649 |
s->lsr |= UART_LSR_DR; |
650 |
} |
651 |
serial_update_irq(s); |
652 |
} |
653 |
|
654 |
static void serial_event(void *opaque, int event) |
655 |
{ |
656 |
SerialState *s = opaque; |
657 |
DPRINTF("event %x\n", event);
|
658 |
if (event == CHR_EVENT_BREAK)
|
659 |
serial_receive_break(s); |
660 |
} |
661 |
|
662 |
static void serial_pre_save(void *opaque) |
663 |
{ |
664 |
SerialState *s = opaque; |
665 |
s->fcr_vmstate = s->fcr; |
666 |
} |
667 |
|
668 |
static int serial_post_load(void *opaque, int version_id) |
669 |
{ |
670 |
SerialState *s = opaque; |
671 |
|
672 |
if (version_id < 3) { |
673 |
s->fcr_vmstate = 0;
|
674 |
} |
675 |
/* Initialize fcr via setter to perform essential side-effects */
|
676 |
serial_ioport_write(s, 0x02, s->fcr_vmstate);
|
677 |
serial_update_parameters(s); |
678 |
return 0; |
679 |
} |
680 |
|
681 |
static const VMStateDescription vmstate_serial = { |
682 |
.name = "serial",
|
683 |
.version_id = 3,
|
684 |
.minimum_version_id = 2,
|
685 |
.pre_save = serial_pre_save, |
686 |
.post_load = serial_post_load, |
687 |
.fields = (VMStateField []) { |
688 |
VMSTATE_UINT16_V(divider, SerialState, 2),
|
689 |
VMSTATE_UINT8(rbr, SerialState), |
690 |
VMSTATE_UINT8(ier, SerialState), |
691 |
VMSTATE_UINT8(iir, SerialState), |
692 |
VMSTATE_UINT8(lcr, SerialState), |
693 |
VMSTATE_UINT8(mcr, SerialState), |
694 |
VMSTATE_UINT8(lsr, SerialState), |
695 |
VMSTATE_UINT8(msr, SerialState), |
696 |
VMSTATE_UINT8(scr, SerialState), |
697 |
VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
|
698 |
VMSTATE_END_OF_LIST() |
699 |
} |
700 |
}; |
701 |
|
702 |
static void serial_reset(void *opaque) |
703 |
{ |
704 |
SerialState *s = opaque; |
705 |
|
706 |
s->rbr = 0;
|
707 |
s->ier = 0;
|
708 |
s->iir = UART_IIR_NO_INT; |
709 |
s->lcr = 0;
|
710 |
s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
711 |
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
712 |
/* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
|
713 |
s->divider = 0x0C;
|
714 |
s->mcr = UART_MCR_OUT2; |
715 |
s->scr = 0;
|
716 |
s->tsr_retry = 0;
|
717 |
s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10; |
718 |
s->poll_msl = 0;
|
719 |
|
720 |
fifo_clear(s,RECV_FIFO); |
721 |
fifo_clear(s,XMIT_FIFO); |
722 |
|
723 |
s->last_xmit_ts = qemu_get_clock_ns(vm_clock); |
724 |
|
725 |
s->thr_ipending = 0;
|
726 |
s->last_break_enable = 0;
|
727 |
qemu_irq_lower(s->irq); |
728 |
} |
729 |
|
730 |
static void serial_init_core(SerialState *s) |
731 |
{ |
732 |
if (!s->chr) {
|
733 |
fprintf(stderr, "Can't create serial device, empty char device\n");
|
734 |
exit(1);
|
735 |
} |
736 |
|
737 |
s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s); |
738 |
|
739 |
s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); |
740 |
s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s); |
741 |
|
742 |
qemu_register_reset(serial_reset, s); |
743 |
|
744 |
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, |
745 |
serial_event, s); |
746 |
} |
747 |
|
748 |
/* Change the main reference oscillator frequency. */
|
749 |
void serial_set_frequency(SerialState *s, uint32_t frequency)
|
750 |
{ |
751 |
s->baudbase = frequency; |
752 |
serial_update_parameters(s); |
753 |
} |
754 |
|
755 |
static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
756 |
static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
757 |
|
758 |
static int serial_isa_initfn(ISADevice *dev) |
759 |
{ |
760 |
static int index; |
761 |
ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev); |
762 |
SerialState *s = &isa->state; |
763 |
|
764 |
if (isa->index == -1) |
765 |
isa->index = index; |
766 |
if (isa->index >= MAX_SERIAL_PORTS)
|
767 |
return -1; |
768 |
if (isa->iobase == -1) |
769 |
isa->iobase = isa_serial_io[isa->index]; |
770 |
if (isa->isairq == -1) |
771 |
isa->isairq = isa_serial_irq[isa->index]; |
772 |
index++; |
773 |
|
774 |
s->baudbase = 115200;
|
775 |
isa_init_irq(dev, &s->irq, isa->isairq); |
776 |
serial_init_core(s); |
777 |
qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
|
778 |
|
779 |
register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s); |
780 |
register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s); |
781 |
isa_init_ioport_range(dev, isa->iobase, 8);
|
782 |
return 0; |
783 |
} |
784 |
|
785 |
static const VMStateDescription vmstate_isa_serial = { |
786 |
.name = "serial",
|
787 |
.version_id = 3,
|
788 |
.minimum_version_id = 2,
|
789 |
.fields = (VMStateField []) { |
790 |
VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
|
791 |
VMSTATE_END_OF_LIST() |
792 |
} |
793 |
}; |
794 |
|
795 |
SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
796 |
CharDriverState *chr) |
797 |
{ |
798 |
SerialState *s; |
799 |
|
800 |
s = qemu_mallocz(sizeof(SerialState));
|
801 |
|
802 |
s->irq = irq; |
803 |
s->baudbase = baudbase; |
804 |
s->chr = chr; |
805 |
serial_init_core(s); |
806 |
|
807 |
vmstate_register(NULL, base, &vmstate_serial, s);
|
808 |
|
809 |
register_ioport_write(base, 8, 1, serial_ioport_write, s); |
810 |
register_ioport_read(base, 8, 1, serial_ioport_read, s); |
811 |
return s;
|
812 |
} |
813 |
|
814 |
/* Memory mapped interface */
|
815 |
static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr) |
816 |
{ |
817 |
SerialState *s = opaque; |
818 |
|
819 |
return serial_ioport_read(s, addr >> s->it_shift) & 0xFF; |
820 |
} |
821 |
|
822 |
static void serial_mm_writeb(void *opaque, target_phys_addr_t addr, |
823 |
uint32_t value) |
824 |
{ |
825 |
SerialState *s = opaque; |
826 |
|
827 |
serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
828 |
} |
829 |
|
830 |
static uint32_t serial_mm_readw_be(void *opaque, target_phys_addr_t addr) |
831 |
{ |
832 |
SerialState *s = opaque; |
833 |
uint32_t val; |
834 |
|
835 |
val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
836 |
val = bswap16(val); |
837 |
return val;
|
838 |
} |
839 |
|
840 |
static uint32_t serial_mm_readw_le(void *opaque, target_phys_addr_t addr) |
841 |
{ |
842 |
SerialState *s = opaque; |
843 |
uint32_t val; |
844 |
|
845 |
val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
846 |
return val;
|
847 |
} |
848 |
|
849 |
static void serial_mm_writew_be(void *opaque, target_phys_addr_t addr, |
850 |
uint32_t value) |
851 |
{ |
852 |
SerialState *s = opaque; |
853 |
|
854 |
value = bswap16(value); |
855 |
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
856 |
} |
857 |
|
858 |
static void serial_mm_writew_le(void *opaque, target_phys_addr_t addr, |
859 |
uint32_t value) |
860 |
{ |
861 |
SerialState *s = opaque; |
862 |
|
863 |
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
864 |
} |
865 |
|
866 |
static uint32_t serial_mm_readl_be(void *opaque, target_phys_addr_t addr) |
867 |
{ |
868 |
SerialState *s = opaque; |
869 |
uint32_t val; |
870 |
|
871 |
val = serial_ioport_read(s, addr >> s->it_shift); |
872 |
val = bswap32(val); |
873 |
return val;
|
874 |
} |
875 |
|
876 |
static uint32_t serial_mm_readl_le(void *opaque, target_phys_addr_t addr) |
877 |
{ |
878 |
SerialState *s = opaque; |
879 |
uint32_t val; |
880 |
|
881 |
val = serial_ioport_read(s, addr >> s->it_shift); |
882 |
return val;
|
883 |
} |
884 |
|
885 |
static void serial_mm_writel_be(void *opaque, target_phys_addr_t addr, |
886 |
uint32_t value) |
887 |
{ |
888 |
SerialState *s = opaque; |
889 |
|
890 |
value = bswap32(value); |
891 |
serial_ioport_write(s, addr >> s->it_shift, value); |
892 |
} |
893 |
|
894 |
static void serial_mm_writel_le(void *opaque, target_phys_addr_t addr, |
895 |
uint32_t value) |
896 |
{ |
897 |
SerialState *s = opaque; |
898 |
|
899 |
serial_ioport_write(s, addr >> s->it_shift, value); |
900 |
} |
901 |
|
902 |
static CPUReadMemoryFunc * const serial_mm_read_be[] = { |
903 |
&serial_mm_readb, |
904 |
&serial_mm_readw_be, |
905 |
&serial_mm_readl_be, |
906 |
}; |
907 |
|
908 |
static CPUWriteMemoryFunc * const serial_mm_write_be[] = { |
909 |
&serial_mm_writeb, |
910 |
&serial_mm_writew_be, |
911 |
&serial_mm_writel_be, |
912 |
}; |
913 |
|
914 |
static CPUReadMemoryFunc * const serial_mm_read_le[] = { |
915 |
&serial_mm_readb, |
916 |
&serial_mm_readw_le, |
917 |
&serial_mm_readl_le, |
918 |
}; |
919 |
|
920 |
static CPUWriteMemoryFunc * const serial_mm_write_le[] = { |
921 |
&serial_mm_writeb, |
922 |
&serial_mm_writew_le, |
923 |
&serial_mm_writel_le, |
924 |
}; |
925 |
|
926 |
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
927 |
qemu_irq irq, int baudbase,
|
928 |
CharDriverState *chr, int ioregister,
|
929 |
int be)
|
930 |
{ |
931 |
SerialState *s; |
932 |
int s_io_memory;
|
933 |
|
934 |
s = qemu_mallocz(sizeof(SerialState));
|
935 |
|
936 |
s->it_shift = it_shift; |
937 |
s->irq = irq; |
938 |
s->baudbase = baudbase; |
939 |
s->chr = chr; |
940 |
|
941 |
serial_init_core(s); |
942 |
vmstate_register(NULL, base, &vmstate_serial, s);
|
943 |
|
944 |
if (ioregister) {
|
945 |
if (be) {
|
946 |
s_io_memory = cpu_register_io_memory(serial_mm_read_be, |
947 |
serial_mm_write_be, s, |
948 |
DEVICE_NATIVE_ENDIAN); |
949 |
} else {
|
950 |
s_io_memory = cpu_register_io_memory(serial_mm_read_le, |
951 |
serial_mm_write_le, s, |
952 |
DEVICE_NATIVE_ENDIAN); |
953 |
} |
954 |
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
|
955 |
} |
956 |
serial_update_msl(s); |
957 |
return s;
|
958 |
} |
959 |
|
960 |
static ISADeviceInfo serial_isa_info = {
|
961 |
.qdev.name = "isa-serial",
|
962 |
.qdev.size = sizeof(ISASerialState),
|
963 |
.qdev.vmsd = &vmstate_isa_serial, |
964 |
.init = serial_isa_initfn, |
965 |
.qdev.props = (Property[]) { |
966 |
DEFINE_PROP_UINT32("index", ISASerialState, index, -1), |
967 |
DEFINE_PROP_HEX32("iobase", ISASerialState, iobase, -1), |
968 |
DEFINE_PROP_UINT32("irq", ISASerialState, isairq, -1), |
969 |
DEFINE_PROP_CHR("chardev", ISASerialState, state.chr),
|
970 |
DEFINE_PROP_END_OF_LIST(), |
971 |
}, |
972 |
}; |
973 |
|
974 |
static void serial_register_devices(void) |
975 |
{ |
976 |
isa_qdev_register(&serial_isa_info); |
977 |
} |
978 |
|
979 |
device_init(serial_register_devices) |