root / hw / twl92230.c @ 5c3234c6
History | View | Annotate | Download (24.3 kB)
1 |
/*
|
---|---|
2 |
* TI TWL92230C energy-management companion device for the OMAP24xx.
|
3 |
* Aka. Menelaus (N4200 MENELAUS1_V2.2)
|
4 |
*
|
5 |
* Copyright (C) 2008 Nokia Corporation
|
6 |
* Written by Andrzej Zaborowski <andrew@openedhand.com>
|
7 |
*
|
8 |
* This program is free software; you can redistribute it and/or
|
9 |
* modify it under the terms of the GNU General Public License as
|
10 |
* published by the Free Software Foundation; either version 2 or
|
11 |
* (at your option) version 3 of the License.
|
12 |
*
|
13 |
* This program is distributed in the hope that it will be useful,
|
14 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
15 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
16 |
* GNU General Public License for more details.
|
17 |
*
|
18 |
* You should have received a copy of the GNU General Public License along
|
19 |
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
20 |
*/
|
21 |
|
22 |
#include "hw.h" |
23 |
#include "qemu-timer.h" |
24 |
#include "i2c.h" |
25 |
#include "console.h" |
26 |
|
27 |
#define VERBOSE 1 |
28 |
|
29 |
typedef struct { |
30 |
i2c_slave i2c; |
31 |
|
32 |
int firstbyte;
|
33 |
uint8_t reg; |
34 |
|
35 |
uint8_t vcore[5];
|
36 |
uint8_t dcdc[3];
|
37 |
uint8_t ldo[8];
|
38 |
uint8_t sleep[2];
|
39 |
uint8_t osc; |
40 |
uint8_t detect; |
41 |
uint16_t mask; |
42 |
uint16_t status; |
43 |
uint8_t dir; |
44 |
uint8_t inputs; |
45 |
uint8_t outputs; |
46 |
uint8_t bbsms; |
47 |
uint8_t pull[4];
|
48 |
uint8_t mmc_ctrl[3];
|
49 |
uint8_t mmc_debounce; |
50 |
struct {
|
51 |
uint8_t ctrl; |
52 |
uint16_t comp; |
53 |
QEMUTimer *hz_tm; |
54 |
int64_t next; |
55 |
struct tm tm;
|
56 |
struct tm new;
|
57 |
struct tm alm;
|
58 |
int sec_offset;
|
59 |
int alm_sec;
|
60 |
int next_comp;
|
61 |
} rtc; |
62 |
uint16_t rtc_next_vmstate; |
63 |
qemu_irq out[4];
|
64 |
qemu_irq *in; |
65 |
uint8_t pwrbtn_state; |
66 |
qemu_irq pwrbtn; |
67 |
} MenelausState; |
68 |
|
69 |
static inline void menelaus_update(MenelausState *s) |
70 |
{ |
71 |
qemu_set_irq(s->out[3], s->status & ~s->mask);
|
72 |
} |
73 |
|
74 |
static inline void menelaus_rtc_start(MenelausState *s) |
75 |
{ |
76 |
s->rtc.next += qemu_get_clock_ms(rt_clock); |
77 |
qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); |
78 |
} |
79 |
|
80 |
static inline void menelaus_rtc_stop(MenelausState *s) |
81 |
{ |
82 |
qemu_del_timer(s->rtc.hz_tm); |
83 |
s->rtc.next -= qemu_get_clock_ms(rt_clock); |
84 |
if (s->rtc.next < 1) |
85 |
s->rtc.next = 1;
|
86 |
} |
87 |
|
88 |
static void menelaus_rtc_update(MenelausState *s) |
89 |
{ |
90 |
qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset); |
91 |
} |
92 |
|
93 |
static void menelaus_alm_update(MenelausState *s) |
94 |
{ |
95 |
if ((s->rtc.ctrl & 3) == 3) |
96 |
s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset; |
97 |
} |
98 |
|
99 |
static void menelaus_rtc_hz(void *opaque) |
100 |
{ |
101 |
MenelausState *s = (MenelausState *) opaque; |
102 |
|
103 |
s->rtc.next_comp --; |
104 |
s->rtc.alm_sec --; |
105 |
s->rtc.next += 1000;
|
106 |
qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); |
107 |
if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */ |
108 |
menelaus_rtc_update(s); |
109 |
if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec) |
110 |
s->status |= 1 << 8; /* RTCTMR */ |
111 |
else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min) |
112 |
s->status |= 1 << 8; /* RTCTMR */ |
113 |
else if (!s->rtc.tm.tm_hour) |
114 |
s->status |= 1 << 8; /* RTCTMR */ |
115 |
} else
|
116 |
s->status |= 1 << 8; /* RTCTMR */ |
117 |
if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */ |
118 |
if (s->rtc.alm_sec == 0) |
119 |
s->status |= 1 << 9; /* RTCALM */ |
120 |
/* TODO: wake-up */
|
121 |
} |
122 |
if (s->rtc.next_comp <= 0) { |
123 |
s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000); |
124 |
s->rtc.next_comp = 3600;
|
125 |
} |
126 |
menelaus_update(s); |
127 |
} |
128 |
|
129 |
static void menelaus_reset(i2c_slave *i2c) |
130 |
{ |
131 |
MenelausState *s = (MenelausState *) i2c; |
132 |
s->reg = 0x00;
|
133 |
|
134 |
s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */ |
135 |
s->vcore[1] = 0x05; |
136 |
s->vcore[2] = 0x02; |
137 |
s->vcore[3] = 0x0c; |
138 |
s->vcore[4] = 0x03; |
139 |
s->dcdc[0] = 0x33; /* Depends on wiring */ |
140 |
s->dcdc[1] = 0x03; |
141 |
s->dcdc[2] = 0x00; |
142 |
s->ldo[0] = 0x95; |
143 |
s->ldo[1] = 0x7e; |
144 |
s->ldo[2] = 0x00; |
145 |
s->ldo[3] = 0x00; /* Depends on wiring */ |
146 |
s->ldo[4] = 0x03; /* Depends on wiring */ |
147 |
s->ldo[5] = 0x00; |
148 |
s->ldo[6] = 0x00; |
149 |
s->ldo[7] = 0x00; |
150 |
s->sleep[0] = 0x00; |
151 |
s->sleep[1] = 0x00; |
152 |
s->osc = 0x01;
|
153 |
s->detect = 0x09;
|
154 |
s->mask = 0x0fff;
|
155 |
s->status = 0;
|
156 |
s->dir = 0x07;
|
157 |
s->outputs = 0x00;
|
158 |
s->bbsms = 0x00;
|
159 |
s->pull[0] = 0x00; |
160 |
s->pull[1] = 0x00; |
161 |
s->pull[2] = 0x00; |
162 |
s->pull[3] = 0x00; |
163 |
s->mmc_ctrl[0] = 0x03; |
164 |
s->mmc_ctrl[1] = 0xc0; |
165 |
s->mmc_ctrl[2] = 0x00; |
166 |
s->mmc_debounce = 0x05;
|
167 |
|
168 |
if (s->rtc.ctrl & 1) |
169 |
menelaus_rtc_stop(s); |
170 |
s->rtc.ctrl = 0x00;
|
171 |
s->rtc.comp = 0x0000;
|
172 |
s->rtc.next = 1000;
|
173 |
s->rtc.sec_offset = 0;
|
174 |
s->rtc.next_comp = 1800;
|
175 |
s->rtc.alm_sec = 1800;
|
176 |
s->rtc.alm.tm_sec = 0x00;
|
177 |
s->rtc.alm.tm_min = 0x00;
|
178 |
s->rtc.alm.tm_hour = 0x00;
|
179 |
s->rtc.alm.tm_mday = 0x01;
|
180 |
s->rtc.alm.tm_mon = 0x00;
|
181 |
s->rtc.alm.tm_year = 2004;
|
182 |
menelaus_update(s); |
183 |
} |
184 |
|
185 |
static void menelaus_gpio_set(void *opaque, int line, int level) |
186 |
{ |
187 |
MenelausState *s = (MenelausState *) opaque; |
188 |
|
189 |
/* No interrupt generated */
|
190 |
s->inputs &= ~(1 << line);
|
191 |
s->inputs |= level << line; |
192 |
} |
193 |
|
194 |
static void menelaus_pwrbtn_set(void *opaque, int line, int level) |
195 |
{ |
196 |
MenelausState *s = (MenelausState *) opaque; |
197 |
|
198 |
if (!s->pwrbtn_state && level) {
|
199 |
s->status |= 1 << 11; /* PSHBTN */ |
200 |
menelaus_update(s); |
201 |
} |
202 |
s->pwrbtn_state = level; |
203 |
} |
204 |
|
205 |
#define MENELAUS_REV 0x01 |
206 |
#define MENELAUS_VCORE_CTRL1 0x02 |
207 |
#define MENELAUS_VCORE_CTRL2 0x03 |
208 |
#define MENELAUS_VCORE_CTRL3 0x04 |
209 |
#define MENELAUS_VCORE_CTRL4 0x05 |
210 |
#define MENELAUS_VCORE_CTRL5 0x06 |
211 |
#define MENELAUS_DCDC_CTRL1 0x07 |
212 |
#define MENELAUS_DCDC_CTRL2 0x08 |
213 |
#define MENELAUS_DCDC_CTRL3 0x09 |
214 |
#define MENELAUS_LDO_CTRL1 0x0a |
215 |
#define MENELAUS_LDO_CTRL2 0x0b |
216 |
#define MENELAUS_LDO_CTRL3 0x0c |
217 |
#define MENELAUS_LDO_CTRL4 0x0d |
218 |
#define MENELAUS_LDO_CTRL5 0x0e |
219 |
#define MENELAUS_LDO_CTRL6 0x0f |
220 |
#define MENELAUS_LDO_CTRL7 0x10 |
221 |
#define MENELAUS_LDO_CTRL8 0x11 |
222 |
#define MENELAUS_SLEEP_CTRL1 0x12 |
223 |
#define MENELAUS_SLEEP_CTRL2 0x13 |
224 |
#define MENELAUS_DEVICE_OFF 0x14 |
225 |
#define MENELAUS_OSC_CTRL 0x15 |
226 |
#define MENELAUS_DETECT_CTRL 0x16 |
227 |
#define MENELAUS_INT_MASK1 0x17 |
228 |
#define MENELAUS_INT_MASK2 0x18 |
229 |
#define MENELAUS_INT_STATUS1 0x19 |
230 |
#define MENELAUS_INT_STATUS2 0x1a |
231 |
#define MENELAUS_INT_ACK1 0x1b |
232 |
#define MENELAUS_INT_ACK2 0x1c |
233 |
#define MENELAUS_GPIO_CTRL 0x1d |
234 |
#define MENELAUS_GPIO_IN 0x1e |
235 |
#define MENELAUS_GPIO_OUT 0x1f |
236 |
#define MENELAUS_BBSMS 0x20 |
237 |
#define MENELAUS_RTC_CTRL 0x21 |
238 |
#define MENELAUS_RTC_UPDATE 0x22 |
239 |
#define MENELAUS_RTC_SEC 0x23 |
240 |
#define MENELAUS_RTC_MIN 0x24 |
241 |
#define MENELAUS_RTC_HR 0x25 |
242 |
#define MENELAUS_RTC_DAY 0x26 |
243 |
#define MENELAUS_RTC_MON 0x27 |
244 |
#define MENELAUS_RTC_YR 0x28 |
245 |
#define MENELAUS_RTC_WKDAY 0x29 |
246 |
#define MENELAUS_RTC_AL_SEC 0x2a |
247 |
#define MENELAUS_RTC_AL_MIN 0x2b |
248 |
#define MENELAUS_RTC_AL_HR 0x2c |
249 |
#define MENELAUS_RTC_AL_DAY 0x2d |
250 |
#define MENELAUS_RTC_AL_MON 0x2e |
251 |
#define MENELAUS_RTC_AL_YR 0x2f |
252 |
#define MENELAUS_RTC_COMP_MSB 0x30 |
253 |
#define MENELAUS_RTC_COMP_LSB 0x31 |
254 |
#define MENELAUS_S1_PULL_EN 0x32 |
255 |
#define MENELAUS_S1_PULL_DIR 0x33 |
256 |
#define MENELAUS_S2_PULL_EN 0x34 |
257 |
#define MENELAUS_S2_PULL_DIR 0x35 |
258 |
#define MENELAUS_MCT_CTRL1 0x36 |
259 |
#define MENELAUS_MCT_CTRL2 0x37 |
260 |
#define MENELAUS_MCT_CTRL3 0x38 |
261 |
#define MENELAUS_MCT_PIN_ST 0x39 |
262 |
#define MENELAUS_DEBOUNCE1 0x3a |
263 |
|
264 |
static uint8_t menelaus_read(void *opaque, uint8_t addr) |
265 |
{ |
266 |
MenelausState *s = (MenelausState *) opaque; |
267 |
int reg = 0; |
268 |
|
269 |
switch (addr) {
|
270 |
case MENELAUS_REV:
|
271 |
return 0x22; |
272 |
|
273 |
case MENELAUS_VCORE_CTRL5: reg ++;
|
274 |
case MENELAUS_VCORE_CTRL4: reg ++;
|
275 |
case MENELAUS_VCORE_CTRL3: reg ++;
|
276 |
case MENELAUS_VCORE_CTRL2: reg ++;
|
277 |
case MENELAUS_VCORE_CTRL1:
|
278 |
return s->vcore[reg];
|
279 |
|
280 |
case MENELAUS_DCDC_CTRL3: reg ++;
|
281 |
case MENELAUS_DCDC_CTRL2: reg ++;
|
282 |
case MENELAUS_DCDC_CTRL1:
|
283 |
return s->dcdc[reg];
|
284 |
|
285 |
case MENELAUS_LDO_CTRL8: reg ++;
|
286 |
case MENELAUS_LDO_CTRL7: reg ++;
|
287 |
case MENELAUS_LDO_CTRL6: reg ++;
|
288 |
case MENELAUS_LDO_CTRL5: reg ++;
|
289 |
case MENELAUS_LDO_CTRL4: reg ++;
|
290 |
case MENELAUS_LDO_CTRL3: reg ++;
|
291 |
case MENELAUS_LDO_CTRL2: reg ++;
|
292 |
case MENELAUS_LDO_CTRL1:
|
293 |
return s->ldo[reg];
|
294 |
|
295 |
case MENELAUS_SLEEP_CTRL2: reg ++;
|
296 |
case MENELAUS_SLEEP_CTRL1:
|
297 |
return s->sleep[reg];
|
298 |
|
299 |
case MENELAUS_DEVICE_OFF:
|
300 |
return 0; |
301 |
|
302 |
case MENELAUS_OSC_CTRL:
|
303 |
return s->osc | (1 << 7); /* CLK32K_GOOD */ |
304 |
|
305 |
case MENELAUS_DETECT_CTRL:
|
306 |
return s->detect;
|
307 |
|
308 |
case MENELAUS_INT_MASK1:
|
309 |
return (s->mask >> 0) & 0xff; |
310 |
case MENELAUS_INT_MASK2:
|
311 |
return (s->mask >> 8) & 0xff; |
312 |
|
313 |
case MENELAUS_INT_STATUS1:
|
314 |
return (s->status >> 0) & 0xff; |
315 |
case MENELAUS_INT_STATUS2:
|
316 |
return (s->status >> 8) & 0xff; |
317 |
|
318 |
case MENELAUS_INT_ACK1:
|
319 |
case MENELAUS_INT_ACK2:
|
320 |
return 0; |
321 |
|
322 |
case MENELAUS_GPIO_CTRL:
|
323 |
return s->dir;
|
324 |
case MENELAUS_GPIO_IN:
|
325 |
return s->inputs | (~s->dir & s->outputs);
|
326 |
case MENELAUS_GPIO_OUT:
|
327 |
return s->outputs;
|
328 |
|
329 |
case MENELAUS_BBSMS:
|
330 |
return s->bbsms;
|
331 |
|
332 |
case MENELAUS_RTC_CTRL:
|
333 |
return s->rtc.ctrl;
|
334 |
case MENELAUS_RTC_UPDATE:
|
335 |
return 0x00; |
336 |
case MENELAUS_RTC_SEC:
|
337 |
menelaus_rtc_update(s); |
338 |
return to_bcd(s->rtc.tm.tm_sec);
|
339 |
case MENELAUS_RTC_MIN:
|
340 |
menelaus_rtc_update(s); |
341 |
return to_bcd(s->rtc.tm.tm_min);
|
342 |
case MENELAUS_RTC_HR:
|
343 |
menelaus_rtc_update(s); |
344 |
if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */ |
345 |
return to_bcd((s->rtc.tm.tm_hour % 12) + 1) | |
346 |
(!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */ |
347 |
else
|
348 |
return to_bcd(s->rtc.tm.tm_hour);
|
349 |
case MENELAUS_RTC_DAY:
|
350 |
menelaus_rtc_update(s); |
351 |
return to_bcd(s->rtc.tm.tm_mday);
|
352 |
case MENELAUS_RTC_MON:
|
353 |
menelaus_rtc_update(s); |
354 |
return to_bcd(s->rtc.tm.tm_mon + 1); |
355 |
case MENELAUS_RTC_YR:
|
356 |
menelaus_rtc_update(s); |
357 |
return to_bcd(s->rtc.tm.tm_year - 2000); |
358 |
case MENELAUS_RTC_WKDAY:
|
359 |
menelaus_rtc_update(s); |
360 |
return to_bcd(s->rtc.tm.tm_wday);
|
361 |
case MENELAUS_RTC_AL_SEC:
|
362 |
return to_bcd(s->rtc.alm.tm_sec);
|
363 |
case MENELAUS_RTC_AL_MIN:
|
364 |
return to_bcd(s->rtc.alm.tm_min);
|
365 |
case MENELAUS_RTC_AL_HR:
|
366 |
if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */ |
367 |
return to_bcd((s->rtc.alm.tm_hour % 12) + 1) | |
368 |
(!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */ |
369 |
else
|
370 |
return to_bcd(s->rtc.alm.tm_hour);
|
371 |
case MENELAUS_RTC_AL_DAY:
|
372 |
return to_bcd(s->rtc.alm.tm_mday);
|
373 |
case MENELAUS_RTC_AL_MON:
|
374 |
return to_bcd(s->rtc.alm.tm_mon + 1); |
375 |
case MENELAUS_RTC_AL_YR:
|
376 |
return to_bcd(s->rtc.alm.tm_year - 2000); |
377 |
case MENELAUS_RTC_COMP_MSB:
|
378 |
return (s->rtc.comp >> 8) & 0xff; |
379 |
case MENELAUS_RTC_COMP_LSB:
|
380 |
return (s->rtc.comp >> 0) & 0xff; |
381 |
|
382 |
case MENELAUS_S1_PULL_EN:
|
383 |
return s->pull[0]; |
384 |
case MENELAUS_S1_PULL_DIR:
|
385 |
return s->pull[1]; |
386 |
case MENELAUS_S2_PULL_EN:
|
387 |
return s->pull[2]; |
388 |
case MENELAUS_S2_PULL_DIR:
|
389 |
return s->pull[3]; |
390 |
|
391 |
case MENELAUS_MCT_CTRL3: reg ++;
|
392 |
case MENELAUS_MCT_CTRL2: reg ++;
|
393 |
case MENELAUS_MCT_CTRL1:
|
394 |
return s->mmc_ctrl[reg];
|
395 |
case MENELAUS_MCT_PIN_ST:
|
396 |
/* TODO: return the real Card Detect */
|
397 |
return 0; |
398 |
case MENELAUS_DEBOUNCE1:
|
399 |
return s->mmc_debounce;
|
400 |
|
401 |
default:
|
402 |
#ifdef VERBOSE
|
403 |
printf("%s: unknown register %02x\n", __FUNCTION__, addr);
|
404 |
#endif
|
405 |
break;
|
406 |
} |
407 |
return 0; |
408 |
} |
409 |
|
410 |
static void menelaus_write(void *opaque, uint8_t addr, uint8_t value) |
411 |
{ |
412 |
MenelausState *s = (MenelausState *) opaque; |
413 |
int line;
|
414 |
int reg = 0; |
415 |
struct tm tm;
|
416 |
|
417 |
switch (addr) {
|
418 |
case MENELAUS_VCORE_CTRL1:
|
419 |
s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12); |
420 |
break;
|
421 |
case MENELAUS_VCORE_CTRL2:
|
422 |
s->vcore[1] = value;
|
423 |
break;
|
424 |
case MENELAUS_VCORE_CTRL3:
|
425 |
s->vcore[2] = MIN(value & 0x1f, 0x12); |
426 |
break;
|
427 |
case MENELAUS_VCORE_CTRL4:
|
428 |
s->vcore[3] = MIN(value & 0x1f, 0x12); |
429 |
break;
|
430 |
case MENELAUS_VCORE_CTRL5:
|
431 |
s->vcore[4] = value & 3; |
432 |
/* XXX
|
433 |
* auto set to 3 on M_Active, nRESWARM
|
434 |
* auto set to 0 on M_WaitOn, M_Backup
|
435 |
*/
|
436 |
break;
|
437 |
|
438 |
case MENELAUS_DCDC_CTRL1:
|
439 |
s->dcdc[0] = value & 0x3f; |
440 |
break;
|
441 |
case MENELAUS_DCDC_CTRL2:
|
442 |
s->dcdc[1] = value & 0x07; |
443 |
/* XXX
|
444 |
* auto set to 3 on M_Active, nRESWARM
|
445 |
* auto set to 0 on M_WaitOn, M_Backup
|
446 |
*/
|
447 |
break;
|
448 |
case MENELAUS_DCDC_CTRL3:
|
449 |
s->dcdc[2] = value & 0x07; |
450 |
break;
|
451 |
|
452 |
case MENELAUS_LDO_CTRL1:
|
453 |
s->ldo[0] = value;
|
454 |
break;
|
455 |
case MENELAUS_LDO_CTRL2:
|
456 |
s->ldo[1] = value & 0x7f; |
457 |
/* XXX
|
458 |
* auto set to 0x7e on M_WaitOn, M_Backup
|
459 |
*/
|
460 |
break;
|
461 |
case MENELAUS_LDO_CTRL3:
|
462 |
s->ldo[2] = value & 3; |
463 |
/* XXX
|
464 |
* auto set to 3 on M_Active, nRESWARM
|
465 |
* auto set to 0 on M_WaitOn, M_Backup
|
466 |
*/
|
467 |
break;
|
468 |
case MENELAUS_LDO_CTRL4:
|
469 |
s->ldo[3] = value & 3; |
470 |
/* XXX
|
471 |
* auto set to 3 on M_Active, nRESWARM
|
472 |
* auto set to 0 on M_WaitOn, M_Backup
|
473 |
*/
|
474 |
break;
|
475 |
case MENELAUS_LDO_CTRL5:
|
476 |
s->ldo[4] = value & 3; |
477 |
/* XXX
|
478 |
* auto set to 3 on M_Active, nRESWARM
|
479 |
* auto set to 0 on M_WaitOn, M_Backup
|
480 |
*/
|
481 |
break;
|
482 |
case MENELAUS_LDO_CTRL6:
|
483 |
s->ldo[5] = value & 3; |
484 |
break;
|
485 |
case MENELAUS_LDO_CTRL7:
|
486 |
s->ldo[6] = value & 3; |
487 |
break;
|
488 |
case MENELAUS_LDO_CTRL8:
|
489 |
s->ldo[7] = value & 3; |
490 |
break;
|
491 |
|
492 |
case MENELAUS_SLEEP_CTRL2: reg ++;
|
493 |
case MENELAUS_SLEEP_CTRL1:
|
494 |
s->sleep[reg] = value; |
495 |
break;
|
496 |
|
497 |
case MENELAUS_DEVICE_OFF:
|
498 |
if (value & 1) |
499 |
menelaus_reset(&s->i2c); |
500 |
break;
|
501 |
|
502 |
case MENELAUS_OSC_CTRL:
|
503 |
s->osc = value & 7;
|
504 |
break;
|
505 |
|
506 |
case MENELAUS_DETECT_CTRL:
|
507 |
s->detect = value & 0x7f;
|
508 |
break;
|
509 |
|
510 |
case MENELAUS_INT_MASK1:
|
511 |
s->mask &= 0xf00;
|
512 |
s->mask |= value << 0;
|
513 |
menelaus_update(s); |
514 |
break;
|
515 |
case MENELAUS_INT_MASK2:
|
516 |
s->mask &= 0x0ff;
|
517 |
s->mask |= value << 8;
|
518 |
menelaus_update(s); |
519 |
break;
|
520 |
|
521 |
case MENELAUS_INT_ACK1:
|
522 |
s->status &= ~(((uint16_t) value) << 0);
|
523 |
menelaus_update(s); |
524 |
break;
|
525 |
case MENELAUS_INT_ACK2:
|
526 |
s->status &= ~(((uint16_t) value) << 8);
|
527 |
menelaus_update(s); |
528 |
break;
|
529 |
|
530 |
case MENELAUS_GPIO_CTRL:
|
531 |
for (line = 0; line < 3; line ++) { |
532 |
if (((s->dir ^ value) >> line) & 1) { |
533 |
qemu_set_irq(s->out[line], |
534 |
((s->outputs & ~s->dir) >> line) & 1);
|
535 |
} |
536 |
} |
537 |
s->dir = value & 0x67;
|
538 |
break;
|
539 |
case MENELAUS_GPIO_OUT:
|
540 |
for (line = 0; line < 3; line ++) { |
541 |
if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) { |
542 |
qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
|
543 |
} |
544 |
} |
545 |
s->outputs = value & 0x07;
|
546 |
break;
|
547 |
|
548 |
case MENELAUS_BBSMS:
|
549 |
s->bbsms = 0x0d;
|
550 |
break;
|
551 |
|
552 |
case MENELAUS_RTC_CTRL:
|
553 |
if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */ |
554 |
if (value & 1) |
555 |
menelaus_rtc_start(s); |
556 |
else
|
557 |
menelaus_rtc_stop(s); |
558 |
} |
559 |
s->rtc.ctrl = value & 0x1f;
|
560 |
menelaus_alm_update(s); |
561 |
break;
|
562 |
case MENELAUS_RTC_UPDATE:
|
563 |
menelaus_rtc_update(s); |
564 |
memcpy(&tm, &s->rtc.tm, sizeof(tm));
|
565 |
switch (value & 0xf) { |
566 |
case 0: |
567 |
break;
|
568 |
case 1: |
569 |
tm.tm_sec = s->rtc.new.tm_sec; |
570 |
break;
|
571 |
case 2: |
572 |
tm.tm_min = s->rtc.new.tm_min; |
573 |
break;
|
574 |
case 3: |
575 |
if (s->rtc.new.tm_hour > 23) |
576 |
goto rtc_badness;
|
577 |
tm.tm_hour = s->rtc.new.tm_hour; |
578 |
break;
|
579 |
case 4: |
580 |
if (s->rtc.new.tm_mday < 1) |
581 |
goto rtc_badness;
|
582 |
/* TODO check range */
|
583 |
tm.tm_mday = s->rtc.new.tm_mday; |
584 |
break;
|
585 |
case 5: |
586 |
if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11) |
587 |
goto rtc_badness;
|
588 |
tm.tm_mon = s->rtc.new.tm_mon; |
589 |
break;
|
590 |
case 6: |
591 |
tm.tm_year = s->rtc.new.tm_year; |
592 |
break;
|
593 |
case 7: |
594 |
/* TODO set .tm_mday instead */
|
595 |
tm.tm_wday = s->rtc.new.tm_wday; |
596 |
break;
|
597 |
case 8: |
598 |
if (s->rtc.new.tm_hour > 23) |
599 |
goto rtc_badness;
|
600 |
if (s->rtc.new.tm_mday < 1) |
601 |
goto rtc_badness;
|
602 |
if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11) |
603 |
goto rtc_badness;
|
604 |
tm.tm_sec = s->rtc.new.tm_sec; |
605 |
tm.tm_min = s->rtc.new.tm_min; |
606 |
tm.tm_hour = s->rtc.new.tm_hour; |
607 |
tm.tm_mday = s->rtc.new.tm_mday; |
608 |
tm.tm_mon = s->rtc.new.tm_mon; |
609 |
tm.tm_year = s->rtc.new.tm_year; |
610 |
break;
|
611 |
rtc_badness:
|
612 |
default:
|
613 |
fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
|
614 |
__FUNCTION__, value); |
615 |
s->status |= 1 << 10; /* RTCERR */ |
616 |
menelaus_update(s); |
617 |
} |
618 |
s->rtc.sec_offset = qemu_timedate_diff(&tm); |
619 |
break;
|
620 |
case MENELAUS_RTC_SEC:
|
621 |
s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
|
622 |
break;
|
623 |
case MENELAUS_RTC_MIN:
|
624 |
s->rtc.tm.tm_min = from_bcd(value & 0x7f);
|
625 |
break;
|
626 |
case MENELAUS_RTC_HR:
|
627 |
s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */ |
628 |
MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) : |
629 |
from_bcd(value & 0x3f);
|
630 |
break;
|
631 |
case MENELAUS_RTC_DAY:
|
632 |
s->rtc.tm.tm_mday = from_bcd(value); |
633 |
break;
|
634 |
case MENELAUS_RTC_MON:
|
635 |
s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1; |
636 |
break;
|
637 |
case MENELAUS_RTC_YR:
|
638 |
s->rtc.tm.tm_year = 2000 + from_bcd(value);
|
639 |
break;
|
640 |
case MENELAUS_RTC_WKDAY:
|
641 |
s->rtc.tm.tm_mday = from_bcd(value); |
642 |
break;
|
643 |
case MENELAUS_RTC_AL_SEC:
|
644 |
s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
|
645 |
menelaus_alm_update(s); |
646 |
break;
|
647 |
case MENELAUS_RTC_AL_MIN:
|
648 |
s->rtc.alm.tm_min = from_bcd(value & 0x7f);
|
649 |
menelaus_alm_update(s); |
650 |
break;
|
651 |
case MENELAUS_RTC_AL_HR:
|
652 |
s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */ |
653 |
MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) : |
654 |
from_bcd(value & 0x3f);
|
655 |
menelaus_alm_update(s); |
656 |
break;
|
657 |
case MENELAUS_RTC_AL_DAY:
|
658 |
s->rtc.alm.tm_mday = from_bcd(value); |
659 |
menelaus_alm_update(s); |
660 |
break;
|
661 |
case MENELAUS_RTC_AL_MON:
|
662 |
s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1; |
663 |
menelaus_alm_update(s); |
664 |
break;
|
665 |
case MENELAUS_RTC_AL_YR:
|
666 |
s->rtc.alm.tm_year = 2000 + from_bcd(value);
|
667 |
menelaus_alm_update(s); |
668 |
break;
|
669 |
case MENELAUS_RTC_COMP_MSB:
|
670 |
s->rtc.comp &= 0xff;
|
671 |
s->rtc.comp |= value << 8;
|
672 |
break;
|
673 |
case MENELAUS_RTC_COMP_LSB:
|
674 |
s->rtc.comp &= 0xff << 8; |
675 |
s->rtc.comp |= value; |
676 |
break;
|
677 |
|
678 |
case MENELAUS_S1_PULL_EN:
|
679 |
s->pull[0] = value;
|
680 |
break;
|
681 |
case MENELAUS_S1_PULL_DIR:
|
682 |
s->pull[1] = value & 0x1f; |
683 |
break;
|
684 |
case MENELAUS_S2_PULL_EN:
|
685 |
s->pull[2] = value;
|
686 |
break;
|
687 |
case MENELAUS_S2_PULL_DIR:
|
688 |
s->pull[3] = value & 0x1f; |
689 |
break;
|
690 |
|
691 |
case MENELAUS_MCT_CTRL1:
|
692 |
s->mmc_ctrl[0] = value & 0x7f; |
693 |
break;
|
694 |
case MENELAUS_MCT_CTRL2:
|
695 |
s->mmc_ctrl[1] = value;
|
696 |
/* TODO update Card Detect interrupts */
|
697 |
break;
|
698 |
case MENELAUS_MCT_CTRL3:
|
699 |
s->mmc_ctrl[2] = value & 0xf; |
700 |
break;
|
701 |
case MENELAUS_DEBOUNCE1:
|
702 |
s->mmc_debounce = value & 0x3f;
|
703 |
break;
|
704 |
|
705 |
default:
|
706 |
#ifdef VERBOSE
|
707 |
printf("%s: unknown register %02x\n", __FUNCTION__, addr);
|
708 |
#endif
|
709 |
} |
710 |
} |
711 |
|
712 |
static void menelaus_event(i2c_slave *i2c, enum i2c_event event) |
713 |
{ |
714 |
MenelausState *s = (MenelausState *) i2c; |
715 |
|
716 |
if (event == I2C_START_SEND)
|
717 |
s->firstbyte = 1;
|
718 |
} |
719 |
|
720 |
static int menelaus_tx(i2c_slave *i2c, uint8_t data) |
721 |
{ |
722 |
MenelausState *s = (MenelausState *) i2c; |
723 |
/* Interpret register address byte */
|
724 |
if (s->firstbyte) {
|
725 |
s->reg = data; |
726 |
s->firstbyte = 0;
|
727 |
} else
|
728 |
menelaus_write(s, s->reg ++, data); |
729 |
|
730 |
return 0; |
731 |
} |
732 |
|
733 |
static int menelaus_rx(i2c_slave *i2c) |
734 |
{ |
735 |
MenelausState *s = (MenelausState *) i2c; |
736 |
|
737 |
return menelaus_read(s, s->reg ++);
|
738 |
} |
739 |
|
740 |
/* Save restore 32 bit int as uint16_t
|
741 |
This is a Big hack, but it is how the old state did it.
|
742 |
Or we broke compatibility in the state, or we can't use struct tm
|
743 |
*/
|
744 |
|
745 |
static int get_int32_as_uint16(QEMUFile *f, void *pv, size_t size) |
746 |
{ |
747 |
int *v = pv;
|
748 |
*v = qemu_get_be16(f); |
749 |
return 0; |
750 |
} |
751 |
|
752 |
static void put_int32_as_uint16(QEMUFile *f, void *pv, size_t size) |
753 |
{ |
754 |
int *v = pv;
|
755 |
qemu_put_be16(f, *v); |
756 |
} |
757 |
|
758 |
static const VMStateInfo vmstate_hack_int32_as_uint16 = { |
759 |
.name = "int32_as_uint16",
|
760 |
.get = get_int32_as_uint16, |
761 |
.put = put_int32_as_uint16, |
762 |
}; |
763 |
|
764 |
#define VMSTATE_UINT16_HACK(_f, _s) \
|
765 |
VMSTATE_SINGLE(_f, _s, 0, vmstate_hack_int32_as_uint16, int32_t)
|
766 |
|
767 |
|
768 |
static const VMStateDescription vmstate_menelaus_tm = { |
769 |
.name = "menelaus_tm",
|
770 |
.version_id = 0,
|
771 |
.minimum_version_id = 0,
|
772 |
.minimum_version_id_old = 0,
|
773 |
.fields = (VMStateField []) { |
774 |
VMSTATE_UINT16_HACK(tm_sec, struct tm),
|
775 |
VMSTATE_UINT16_HACK(tm_min, struct tm),
|
776 |
VMSTATE_UINT16_HACK(tm_hour, struct tm),
|
777 |
VMSTATE_UINT16_HACK(tm_mday, struct tm),
|
778 |
VMSTATE_UINT16_HACK(tm_min, struct tm),
|
779 |
VMSTATE_UINT16_HACK(tm_year, struct tm),
|
780 |
VMSTATE_END_OF_LIST() |
781 |
} |
782 |
}; |
783 |
|
784 |
static void menelaus_pre_save(void *opaque) |
785 |
{ |
786 |
MenelausState *s = opaque; |
787 |
/* Should be <= 1000 */
|
788 |
s->rtc_next_vmstate = s->rtc.next - qemu_get_clock_ms(rt_clock); |
789 |
} |
790 |
|
791 |
static int menelaus_post_load(void *opaque, int version_id) |
792 |
{ |
793 |
MenelausState *s = opaque; |
794 |
|
795 |
if (s->rtc.ctrl & 1) /* RTC_EN */ |
796 |
menelaus_rtc_stop(s); |
797 |
|
798 |
s->rtc.next = s->rtc_next_vmstate; |
799 |
|
800 |
menelaus_alm_update(s); |
801 |
menelaus_update(s); |
802 |
if (s->rtc.ctrl & 1) /* RTC_EN */ |
803 |
menelaus_rtc_start(s); |
804 |
return 0; |
805 |
} |
806 |
|
807 |
static const VMStateDescription vmstate_menelaus = { |
808 |
.name = "menelaus",
|
809 |
.version_id = 0,
|
810 |
.minimum_version_id = 0,
|
811 |
.minimum_version_id_old = 0,
|
812 |
.pre_save = menelaus_pre_save, |
813 |
.post_load = menelaus_post_load, |
814 |
.fields = (VMStateField []) { |
815 |
VMSTATE_INT32(firstbyte, MenelausState), |
816 |
VMSTATE_UINT8(reg, MenelausState), |
817 |
VMSTATE_UINT8_ARRAY(vcore, MenelausState, 5),
|
818 |
VMSTATE_UINT8_ARRAY(dcdc, MenelausState, 3),
|
819 |
VMSTATE_UINT8_ARRAY(ldo, MenelausState, 8),
|
820 |
VMSTATE_UINT8_ARRAY(sleep, MenelausState, 2),
|
821 |
VMSTATE_UINT8(osc, MenelausState), |
822 |
VMSTATE_UINT8(detect, MenelausState), |
823 |
VMSTATE_UINT16(mask, MenelausState), |
824 |
VMSTATE_UINT16(status, MenelausState), |
825 |
VMSTATE_UINT8(dir, MenelausState), |
826 |
VMSTATE_UINT8(inputs, MenelausState), |
827 |
VMSTATE_UINT8(outputs, MenelausState), |
828 |
VMSTATE_UINT8(bbsms, MenelausState), |
829 |
VMSTATE_UINT8_ARRAY(pull, MenelausState, 4),
|
830 |
VMSTATE_UINT8_ARRAY(mmc_ctrl, MenelausState, 3),
|
831 |
VMSTATE_UINT8(mmc_debounce, MenelausState), |
832 |
VMSTATE_UINT8(rtc.ctrl, MenelausState), |
833 |
VMSTATE_UINT16(rtc.comp, MenelausState), |
834 |
VMSTATE_UINT16(rtc_next_vmstate, MenelausState), |
835 |
VMSTATE_STRUCT(rtc.new, MenelausState, 0, vmstate_menelaus_tm,
|
836 |
struct tm),
|
837 |
VMSTATE_STRUCT(rtc.alm, MenelausState, 0, vmstate_menelaus_tm,
|
838 |
struct tm),
|
839 |
VMSTATE_UINT8(pwrbtn_state, MenelausState), |
840 |
VMSTATE_I2C_SLAVE(i2c, MenelausState), |
841 |
VMSTATE_END_OF_LIST() |
842 |
} |
843 |
}; |
844 |
|
845 |
static int twl92230_init(i2c_slave *i2c) |
846 |
{ |
847 |
MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c); |
848 |
|
849 |
s->rtc.hz_tm = qemu_new_timer_ms(rt_clock, menelaus_rtc_hz, s); |
850 |
/* Three output pins plus one interrupt pin. */
|
851 |
qdev_init_gpio_out(&i2c->qdev, s->out, 4);
|
852 |
qdev_init_gpio_in(&i2c->qdev, menelaus_gpio_set, 3);
|
853 |
s->pwrbtn = qemu_allocate_irqs(menelaus_pwrbtn_set, s, 1)[0]; |
854 |
|
855 |
menelaus_reset(&s->i2c); |
856 |
|
857 |
return 0; |
858 |
} |
859 |
|
860 |
static I2CSlaveInfo twl92230_info = {
|
861 |
.qdev.name ="twl92230",
|
862 |
.qdev.size = sizeof(MenelausState),
|
863 |
.qdev.vmsd = &vmstate_menelaus, |
864 |
.init = twl92230_init, |
865 |
.event = menelaus_event, |
866 |
.recv = menelaus_rx, |
867 |
.send = menelaus_tx |
868 |
}; |
869 |
|
870 |
static void twl92230_register_devices(void) |
871 |
{ |
872 |
i2c_register_slave(&twl92230_info); |
873 |
} |
874 |
|
875 |
device_init(twl92230_register_devices) |