Revision 5c6a0628 target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 450 | 450 |
{
|
| 451 | 451 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 452 | 452 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 453 |
tcg_gen_add_tl(dst, src1, src2); |
|
| 454 |
tcg_gen_mov_tl(cpu_cc_dst, dst); |
|
| 453 |
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 455 | 454 |
gen_cc_clear_icc(); |
| 456 | 455 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 457 | 456 |
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
| ... | ... | |
| 462 | 461 |
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
| 463 | 462 |
gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| 464 | 463 |
#endif |
| 464 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 465 | 465 |
} |
| 466 | 466 |
|
| 467 | 467 |
static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 469 | 469 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 470 | 470 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 471 | 471 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
| 472 |
tcg_gen_add_tl(dst, src1, cpu_tmp0);
|
|
| 472 |
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
|
|
| 473 | 473 |
gen_cc_clear_icc(); |
| 474 |
gen_cc_C_add_icc(dst, cpu_cc_src); |
|
| 474 |
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
|
|
| 475 | 475 |
#ifdef TARGET_SPARC64 |
| 476 | 476 |
gen_cc_clear_xcc(); |
| 477 |
gen_cc_C_add_xcc(dst, cpu_cc_src); |
|
| 477 |
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
|
|
| 478 | 478 |
#endif |
| 479 |
tcg_gen_add_tl(dst, dst, cpu_cc_src2); |
|
| 480 |
tcg_gen_mov_tl(cpu_cc_dst, dst); |
|
| 479 |
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
|
| 481 | 480 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 482 | 481 |
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
| 483 | 482 |
gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| ... | ... | |
| 486 | 485 |
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
| 487 | 486 |
gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| 488 | 487 |
#endif |
| 488 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 489 | 489 |
} |
| 490 | 490 |
|
| 491 | 491 |
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
| 492 | 492 |
{
|
| 493 | 493 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 494 | 494 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 495 |
tcg_gen_add_tl(dst, src1, src2); |
|
| 496 |
tcg_gen_mov_tl(cpu_cc_dst, dst); |
|
| 495 |
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 497 | 496 |
gen_cc_clear_icc(); |
| 498 | 497 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 499 | 498 |
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
| ... | ... | |
| 505 | 504 |
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
| 506 | 505 |
gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| 507 | 506 |
#endif |
| 507 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 508 | 508 |
} |
| 509 | 509 |
|
| 510 | 510 |
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 512 | 512 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 513 | 513 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 514 | 514 |
gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
| 515 |
tcg_gen_add_tl(dst, src1, src2); |
|
| 516 |
tcg_gen_mov_tl(cpu_cc_dst, dst); |
|
| 517 |
gen_add_tv(dst, cpu_cc_src, cpu_cc_src2); |
|
| 515 |
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 516 |
gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 518 | 517 |
gen_cc_clear_icc(); |
| 519 | 518 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 520 | 519 |
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
| ... | ... | |
| 524 | 523 |
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
| 525 | 524 |
gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| 526 | 525 |
#endif |
| 526 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 527 | 527 |
} |
| 528 | 528 |
|
| 529 | 529 |
/* old op: |
| ... | ... | |
| 619 | 619 |
{
|
| 620 | 620 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 621 | 621 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 622 |
tcg_gen_sub_tl(dst, src1, src2); |
|
| 623 |
tcg_gen_mov_tl(cpu_cc_dst, dst); |
|
| 622 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 624 | 623 |
gen_cc_clear_icc(); |
| 625 | 624 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 626 | 625 |
gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
| ... | ... | |
| 631 | 630 |
gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
| 632 | 631 |
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| 633 | 632 |
#endif |
| 633 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 634 | 634 |
} |
| 635 | 635 |
|
| 636 | 636 |
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 638 | 638 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 639 | 639 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 640 | 640 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
| 641 |
tcg_gen_sub_tl(dst, src1, cpu_tmp0);
|
|
| 641 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
|
|
| 642 | 642 |
gen_cc_clear_icc(); |
| 643 |
gen_cc_C_sub_icc(dst, cpu_cc_src); |
|
| 643 |
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
|
|
| 644 | 644 |
#ifdef TARGET_SPARC64 |
| 645 | 645 |
gen_cc_clear_xcc(); |
| 646 |
gen_cc_C_sub_xcc(dst, cpu_cc_src); |
|
| 646 |
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
|
|
| 647 | 647 |
#endif |
| 648 |
tcg_gen_sub_tl(dst, dst, cpu_cc_src2); |
|
| 649 |
tcg_gen_mov_tl(cpu_cc_dst, dst); |
|
| 648 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
|
| 650 | 649 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 651 | 650 |
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
| 652 | 651 |
gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| ... | ... | |
| 655 | 654 |
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
| 656 | 655 |
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| 657 | 656 |
#endif |
| 657 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 658 | 658 |
} |
| 659 | 659 |
|
| 660 | 660 |
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
| 661 | 661 |
{
|
| 662 | 662 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 663 | 663 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 664 |
tcg_gen_sub_tl(dst, src1, src2); |
|
| 665 |
tcg_gen_mov_tl(cpu_cc_dst, dst); |
|
| 664 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 666 | 665 |
gen_cc_clear_icc(); |
| 667 | 666 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 668 | 667 |
gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
| ... | ... | |
| 674 | 673 |
gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
| 675 | 674 |
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| 676 | 675 |
#endif |
| 676 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 677 | 677 |
} |
| 678 | 678 |
|
| 679 | 679 |
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 681 | 681 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 682 | 682 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 683 | 683 |
gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
| 684 |
tcg_gen_sub_tl(dst, src1, src2); |
|
| 685 |
tcg_gen_mov_tl(cpu_cc_dst, dst); |
|
| 686 |
gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2); |
|
| 684 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 685 |
gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 687 | 686 |
gen_cc_clear_icc(); |
| 688 | 687 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 689 | 688 |
gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
| ... | ... | |
| 693 | 692 |
gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
| 694 | 693 |
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| 695 | 694 |
#endif |
| 695 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 696 | 696 |
} |
| 697 | 697 |
|
| 698 | 698 |
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 741 | 741 |
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
| 742 | 742 |
|
| 743 | 743 |
/* do addition and update flags */ |
| 744 |
tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2); |
|
| 745 |
tcg_gen_mov_tl(cpu_cc_dst, dst); |
|
| 744 |
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
|
| 746 | 745 |
|
| 747 | 746 |
gen_cc_clear_icc(); |
| 748 | 747 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 749 | 748 |
gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
| 750 | 749 |
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
| 750 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
|
| 751 | 751 |
} |
| 752 | 752 |
|
| 753 | 753 |
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 818 | 818 |
l2 = gen_new_label(); |
| 819 | 819 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 820 | 820 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 821 |
gen_trap_ifdivzero_tl(src2); |
|
| 821 |
gen_trap_ifdivzero_tl(cpu_cc_src2);
|
|
| 822 | 822 |
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
| 823 | 823 |
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1); |
| 824 | 824 |
tcg_gen_movi_i64(dst, INT64_MIN); |
| ... | ... | |
| 837 | 837 |
gen_cc_clear_icc(); |
| 838 | 838 |
gen_cc_NZ_icc(cpu_cc_dst); |
| 839 | 839 |
l1 = gen_new_label(); |
| 840 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); |
|
| 841 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
|
| 840 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1); |
|
| 842 | 841 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
| 843 | 842 |
gen_set_label(l1); |
| 844 | 843 |
} |
| ... | ... | |
| 1866 | 1865 |
|
| 1867 | 1866 |
rs1 = GET_FIELD(insn, 13, 17); |
| 1868 | 1867 |
if (rs1 == 0) |
| 1869 |
//r_rs1 = tcg_const_tl(0); |
|
| 1870 |
tcg_gen_movi_tl(def, 0); |
|
| 1868 |
r_rs1 = tcg_const_tl(0); // XXX how to free? |
|
| 1871 | 1869 |
else if (rs1 < 8) |
| 1872 |
//r_rs1 = cpu_gregs[rs1]; |
|
| 1873 |
tcg_gen_mov_tl(def, cpu_gregs[rs1]); |
|
| 1870 |
r_rs1 = cpu_gregs[rs1]; |
|
| 1874 | 1871 |
else |
| 1875 | 1872 |
tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); |
| 1876 | 1873 |
return r_rs1; |
| ... | ... | |
| 1916 | 1913 |
rd = GET_FIELD(insn, 2, 6); |
| 1917 | 1914 |
|
| 1918 | 1915 |
cpu_dst = cpu_T[0]; |
| 1919 |
cpu_src1 = cpu_T[0]; // const
|
|
| 1920 |
cpu_src2 = cpu_T[1]; // const
|
|
| 1916 |
cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
|
|
| 1917 |
cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
|
|
| 1921 | 1918 |
|
| 1922 | 1919 |
// loads and stores |
| 1923 | 1920 |
cpu_addr = cpu_T[0]; |
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