root / hw / pcie_regs.h @ 5c6c0e51
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/*
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* constants for pcie configurations space from pci express spec.
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*
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* TODO:
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* Those constants and macros should go to Linux pci_regs.h
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* Once they're merged, they will go away.
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*/
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#ifndef QEMU_PCIE_REGS_H
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#define QEMU_PCIE_REGS_H
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/* express capability */
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#define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2 */ |
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#define PCI_EXT_CAP_VER_SHIFT 16 |
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#define PCI_EXT_CAP_NEXT_SHIFT 20 |
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#define PCI_EXT_CAP_NEXT_MASK (0xffc << PCI_EXT_CAP_NEXT_SHIFT) |
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#define PCI_EXT_CAP(id, ver, next) \
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((id) | \ |
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((ver) << PCI_EXT_CAP_VER_SHIFT) | \ |
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((next) << PCI_EXT_CAP_NEXT_SHIFT)) |
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#define PCI_EXT_CAP_ALIGN 4 |
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#define PCI_EXT_CAP_ALIGNUP(x) \
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(((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1)) |
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/* PCI_EXP_FLAGS */
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#define PCI_EXP_FLAGS_VER2 2 /* for now, supports only ver. 2 */ |
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#define PCI_EXP_FLAGS_IRQ_SHIFT (ffs(PCI_EXP_FLAGS_IRQ) - 1) |
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#define PCI_EXP_FLAGS_TYPE_SHIFT (ffs(PCI_EXP_FLAGS_TYPE) - 1) |
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/* PCI_EXP_LINK{CAP, STA} */
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/* link speed */
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#define PCI_EXP_LNK_LS_25 1 |
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#define PCI_EXP_LNK_MLW_SHIFT (ffs(PCI_EXP_LNKCAP_MLW) - 1) |
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#define PCI_EXP_LNK_MLW_1 (1 << PCI_EXP_LNK_MLW_SHIFT) |
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/* PCI_EXP_LINKCAP */
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#define PCI_EXP_LNKCAP_ASPMS_SHIFT (ffs(PCI_EXP_LNKCAP_ASPMS) - 1) |
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#define PCI_EXP_LNKCAP_ASPMS_0S (1 << PCI_EXP_LNKCAP_ASPMS_SHIFT) |
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#define PCI_EXP_LNKCAP_PN_SHIFT (ffs(PCI_EXP_LNKCAP_PN) - 1) |
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#define PCI_EXP_SLTCAP_PSN_SHIFT (ffs(PCI_EXP_SLTCAP_PSN) - 1) |
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#define PCI_EXP_SLTCTL_IND_RESERVED 0x0 |
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#define PCI_EXP_SLTCTL_IND_ON 0x1 |
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#define PCI_EXP_SLTCTL_IND_BLINK 0x2 |
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#define PCI_EXP_SLTCTL_IND_OFF 0x3 |
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#define PCI_EXP_SLTCTL_AIC_SHIFT (ffs(PCI_EXP_SLTCTL_AIC) - 1) |
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#define PCI_EXP_SLTCTL_AIC_OFF \
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(PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_AIC_SHIFT) |
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#define PCI_EXP_SLTCTL_PIC_SHIFT (ffs(PCI_EXP_SLTCTL_PIC) - 1) |
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#define PCI_EXP_SLTCTL_PIC_OFF \
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(PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_PIC_SHIFT) |
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#define PCI_EXP_SLTCTL_SUPPORTED \
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(PCI_EXP_SLTCTL_ABPE | \ |
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PCI_EXP_SLTCTL_PDCE | \ |
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PCI_EXP_SLTCTL_CCIE | \ |
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PCI_EXP_SLTCTL_HPIE | \ |
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PCI_EXP_SLTCTL_AIC | \ |
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PCI_EXP_SLTCTL_PCC | \ |
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PCI_EXP_SLTCTL_EIC) |
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#define PCI_EXP_DEVCAP2_EFF 0x100000 |
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#define PCI_EXP_DEVCAP2_EETLPP 0x200000 |
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#define PCI_EXP_DEVCTL2_EETLPPB 0x80 |
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/* ARI */
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#define PCI_ARI_VER 1 |
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#define PCI_ARI_SIZEOF 8 |
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/* AER */
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#define PCI_ERR_VER 2 |
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#define PCI_ERR_SIZEOF 0x48 |
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#define PCI_ERR_UNC_SDN 0x00000020 /* surprise down */ |
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#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */ |
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#define PCI_ERR_UNC_INTN 0x00400000 /* Internal Error */ |
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#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC Blcoked TLP */ |
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#define PCI_ERR_UNC_ATOP_EBLOCKED 0x01000000 /* atomic op egress blocked */ |
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#define PCI_ERR_UNC_TLP_PRF_BLOCKED 0x02000000 /* TLP Prefix Blocked */ |
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#define PCI_ERR_COR_ADV_NONFATAL 0x00002000 /* Advisory Non-Fatal */ |
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#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */ |
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#define PCI_ERR_COR_HL_OVERFLOW 0x00008000 /* Header Long Overflow */ |
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#define PCI_ERR_CAP_FEP_MASK 0x0000001f |
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#define PCI_ERR_CAP_MHRC 0x00000200 |
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#define PCI_ERR_CAP_MHRE 0x00000400 |
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#define PCI_ERR_CAP_TLP 0x00000800 |
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#define PCI_ERR_HEADER_LOG_SIZE 16 |
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#define PCI_ERR_TLP_PREFIX_LOG 0x38 |
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#define PCI_ERR_TLP_PREFIX_LOG_SIZE 16 |
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#define PCI_SEC_STATUS_RCV_SYSTEM_ERROR 0x4000 |
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/* aer root error command/status */
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#define PCI_ERR_ROOT_CMD_EN_MASK (PCI_ERR_ROOT_CMD_COR_EN | \
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PCI_ERR_ROOT_CMD_NONFATAL_EN | \ |
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PCI_ERR_ROOT_CMD_FATAL_EN) |
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#define PCI_ERR_ROOT_IRQ_MAX 32 |
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#define PCI_ERR_ROOT_IRQ 0xf8000000 |
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#define PCI_ERR_ROOT_IRQ_SHIFT (ffs(PCI_ERR_ROOT_IRQ) - 1) |
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#define PCI_ERR_ROOT_STATUS_REPORT_MASK (PCI_ERR_ROOT_COR_RCV | \
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PCI_ERR_ROOT_MULTI_COR_RCV | \ |
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PCI_ERR_ROOT_UNCOR_RCV | \ |
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PCI_ERR_ROOT_MULTI_UNCOR_RCV | \ |
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PCI_ERR_ROOT_FIRST_FATAL | \ |
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PCI_ERR_ROOT_NONFATAL_RCV | \ |
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PCI_ERR_ROOT_FATAL_RCV) |
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#define PCI_ERR_UNC_SUPPORTED (PCI_ERR_UNC_DLP | \
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PCI_ERR_UNC_SDN | \ |
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PCI_ERR_UNC_POISON_TLP | \ |
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PCI_ERR_UNC_FCP | \ |
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PCI_ERR_UNC_COMP_TIME | \ |
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PCI_ERR_UNC_COMP_ABORT | \ |
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PCI_ERR_UNC_UNX_COMP | \ |
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PCI_ERR_UNC_RX_OVER | \ |
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PCI_ERR_UNC_MALF_TLP | \ |
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PCI_ERR_UNC_ECRC | \ |
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PCI_ERR_UNC_UNSUP | \ |
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PCI_ERR_UNC_ACSV | \ |
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PCI_ERR_UNC_INTN | \ |
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PCI_ERR_UNC_MCBTLP | \ |
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PCI_ERR_UNC_ATOP_EBLOCKED | \ |
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PCI_ERR_UNC_TLP_PRF_BLOCKED) |
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#define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP | \
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PCI_ERR_UNC_SDN | \ |
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PCI_ERR_UNC_FCP | \ |
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PCI_ERR_UNC_RX_OVER | \ |
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PCI_ERR_UNC_MALF_TLP | \ |
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PCI_ERR_UNC_INTN) |
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#define PCI_ERR_COR_SUPPORTED (PCI_ERR_COR_RCVR | \
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PCI_ERR_COR_BAD_TLP | \ |
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PCI_ERR_COR_BAD_DLLP | \ |
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PCI_ERR_COR_REP_ROLL | \ |
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PCI_ERR_COR_REP_TIMER | \ |
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PCI_ERR_COR_ADV_NONFATAL | \ |
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PCI_ERR_COR_INTERNAL | \ |
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PCI_ERR_COR_HL_OVERFLOW) |
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#define PCI_ERR_COR_MASK_DEFAULT (PCI_ERR_COR_ADV_NONFATAL | \
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PCI_ERR_COR_INTERNAL | \ |
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PCI_ERR_COR_HL_OVERFLOW) |
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#endif /* QEMU_PCIE_REGS_H */ |