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/*
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 * QEMU PC System Emulator
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 *
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 * Copyright (c) 2003-2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "pc.h"
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#include "fdc.h"
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#include "pci.h"
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#include "block.h"
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#include "sysemu.h"
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#include "audio/audio.h"
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#include "net.h"
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#include "smbus.h"
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#include "boards.h"
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#include "console.h"
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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#define BIOS_FILENAME "bios.bin"
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#define VGABIOS_FILENAME "vgabios.bin"
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#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
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#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
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/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
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#define ACPI_DATA_SIZE       0x10000
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#define MAX_IDE_BUS 2
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static fdctrl_t *floppy_controller;
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static RTCState *rtc_state;
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static PITState *pit;
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static IOAPICState *ioapic;
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static PCIDevice *i440fx_state;
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
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{
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}
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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{
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    qemu_irq_raise(ferr_irq);
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}
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
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{
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    qemu_irq_lower(ferr_irq);
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}
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env)
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{
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    /* Note: when using kqemu, it is more logical to return the host TSC
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       because kqemu does not trap the RDTSC instruction for
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       performance reasons */
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#if USE_KQEMU
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    if (env->kqemu_enabled) {
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        return cpu_get_real_ticks();
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    } else
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#endif
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    {
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        return cpu_get_ticks();
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    }
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}
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/* SMM support */
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void cpu_smm_update(CPUState *env)
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{
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    if (i440fx_state && env == first_cpu)
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        i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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}
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{
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    int intno;
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    intno = apic_get_interrupt(env);
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    if (intno >= 0) {
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        /* set irq request if a PIC irq is still pending */
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        /* XXX: improve that */
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        pic_update_irq(isa_pic);
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        return intno;
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    }
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    /* read the irq from the PIC */
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    if (!apic_accept_pic_intr(env))
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        return -1;
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    intno = pic_read_irq(isa_pic);
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    return intno;
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}
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static void pic_irq_request(void *opaque, int irq, int level)
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{
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    CPUState *env = first_cpu;
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    if (!level)
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        return;
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    while (env) {
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        if (apic_accept_pic_intr(env))
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            apic_local_deliver(env, APIC_LINT0);
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        env = env->next_cpu;
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    }
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}
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE          0x14
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static int cmos_get_fd_drive_type(int fd0)
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{
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    int val;
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    switch (fd0) {
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    case 0:
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        /* 1.44 Mb 3"5 drive */
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        val = 4;
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        break;
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    case 1:
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        /* 2.88 Mb 3"5 drive */
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        val = 5;
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        break;
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    case 2:
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        /* 1.2 Mb 5"5 drive */
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        val = 2;
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        break;
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    default:
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        val = 0;
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        break;
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    }
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    return val;
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}
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
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{
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    RTCState *s = rtc_state;
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    int cylinders, heads, sectors;
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    bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
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    rtc_set_memory(s, type_ofs, 47);
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    rtc_set_memory(s, info_ofs, cylinders);
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    rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
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    rtc_set_memory(s, info_ofs + 2, heads);
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    rtc_set_memory(s, info_ofs + 3, 0xff);
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    rtc_set_memory(s, info_ofs + 4, 0xff);
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    rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
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    rtc_set_memory(s, info_ofs + 6, cylinders);
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    rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
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    rtc_set_memory(s, info_ofs + 8, sectors);
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}
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device)
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{
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    switch(boot_device) {
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    case 'a':
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    case 'b':
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        return 0x01; /* floppy boot */
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    case 'c':
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        return 0x02; /* hard drive boot */
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    case 'd':
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        return 0x03; /* CD-ROM boot */
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    case 'n':
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        return 0x04; /* Network boot */
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    }
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    return 0;
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}
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/* copy/pasted from cmos_init, should be made a general function
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 and used there as well */
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int pc_boot_set(const char *boot_device)
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{
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#define PC_MAX_BOOT_DEVICES 3
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    RTCState *s = rtc_state;
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    int nbds, bds[3] = { 0, };
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    int i;
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    nbds = strlen(boot_device);
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    if (nbds > PC_MAX_BOOT_DEVICES) {
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        term_printf("Too many boot devices for PC\n");
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        return(1);
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    }
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    for (i = 0; i < nbds; i++) {
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        bds[i] = boot_device2nibble(boot_device[i]);
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        if (bds[i] == 0) {
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            term_printf("Invalid boot device for PC: '%c'\n",
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                    boot_device[i]);
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            return(1);
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        }
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    }
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    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
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    rtc_set_memory(s, 0x38, (bds[2] << 4));
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    return(0);
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}
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/* hd_table must contain 4 block drivers */
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static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
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                      const char *boot_device, BlockDriverState **hd_table)
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{
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    RTCState *s = rtc_state;
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    int nbds, bds[3] = { 0, };
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    int val;
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    int fd0, fd1, nb;
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    int i;
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    /* various important CMOS locations needed by PC/Bochs bios */
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    /* memory size */
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    val = 640; /* base memory in K */
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    rtc_set_memory(s, 0x15, val);
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    rtc_set_memory(s, 0x16, val >> 8);
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    val = (ram_size / 1024) - 1024;
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    if (val > 65535)
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        val = 65535;
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    rtc_set_memory(s, 0x17, val);
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    rtc_set_memory(s, 0x18, val >> 8);
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    rtc_set_memory(s, 0x30, val);
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    rtc_set_memory(s, 0x31, val >> 8);
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    if (above_4g_mem_size) {
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        rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
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        rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
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        rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
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    }
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    if (ram_size > (16 * 1024 * 1024))
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        val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
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    else
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        val = 0;
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    if (val > 65535)
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        val = 65535;
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    rtc_set_memory(s, 0x34, val);
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    rtc_set_memory(s, 0x35, val >> 8);
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    /* set the number of CPU */
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    rtc_set_memory(s, 0x5f, smp_cpus - 1);
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    /* set boot devices, and disable floppy signature check if requested */
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#define PC_MAX_BOOT_DEVICES 3
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    nbds = strlen(boot_device);
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    if (nbds > PC_MAX_BOOT_DEVICES) {
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        fprintf(stderr, "Too many boot devices for PC\n");
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        exit(1);
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    }
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    for (i = 0; i < nbds; i++) {
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        bds[i] = boot_device2nibble(boot_device[i]);
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        if (bds[i] == 0) {
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            fprintf(stderr, "Invalid boot device for PC: '%c'\n",
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                    boot_device[i]);
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            exit(1);
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        }
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    }
278 28c5af54 j_mayer
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
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    rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
280 80cabfad bellard
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    /* floppy type */
282 b41a2cd1 bellard
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    fd0 = fdctrl_get_drive_type(floppy_controller, 0);
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    fd1 = fdctrl_get_drive_type(floppy_controller, 1);
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    val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
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    rtc_set_memory(s, 0x10, val);
288 3b46e624 ths
289 b0a21b53 bellard
    val = 0;
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    nb = 0;
291 80cabfad bellard
    if (fd0 < 3)
292 80cabfad bellard
        nb++;
293 80cabfad bellard
    if (fd1 < 3)
294 80cabfad bellard
        nb++;
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    switch (nb) {
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    case 0:
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        break;
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    case 1:
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        val |= 0x01; /* 1 drive, ready for boot */
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        break;
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    case 2:
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        val |= 0x41; /* 2 drives, ready for boot */
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        break;
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    }
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    val |= 0x02; /* FPU is there */
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    val |= 0x04; /* PS/2 mouse installed */
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    rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
308 b0a21b53 bellard
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    /* hard drives */
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    rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
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    if (hd_table[0])
313 ba6c2377 bellard
        cmos_init_hd(0x19, 0x1b, hd_table[0]);
314 5fafdf24 ths
    if (hd_table[1])
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        cmos_init_hd(0x1a, 0x24, hd_table[1]);
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    val = 0;
318 40b6ecc6 bellard
    for (i = 0; i < 4; i++) {
319 ba6c2377 bellard
        if (hd_table[i]) {
320 46d4767d bellard
            int cylinders, heads, sectors, translation;
321 46d4767d bellard
            /* NOTE: bdrv_get_geometry_hint() returns the physical
322 46d4767d bellard
                geometry.  It is always such that: 1 <= sects <= 63, 1
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                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
324 46d4767d bellard
                geometry can be different if a translation is done. */
325 46d4767d bellard
            translation = bdrv_get_translation_hint(hd_table[i]);
326 46d4767d bellard
            if (translation == BIOS_ATA_TRANSLATION_AUTO) {
327 46d4767d bellard
                bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
328 46d4767d bellard
                if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
329 46d4767d bellard
                    /* No translation. */
330 46d4767d bellard
                    translation = 0;
331 46d4767d bellard
                } else {
332 46d4767d bellard
                    /* LBA translation. */
333 46d4767d bellard
                    translation = 1;
334 46d4767d bellard
                }
335 40b6ecc6 bellard
            } else {
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                translation--;
337 ba6c2377 bellard
            }
338 ba6c2377 bellard
            val |= translation << (i * 2);
339 ba6c2377 bellard
        }
340 40b6ecc6 bellard
    }
341 ba6c2377 bellard
    rtc_set_memory(s, 0x39, val);
342 80cabfad bellard
}
343 80cabfad bellard
344 59b8ad81 bellard
void ioport_set_a20(int enable)
345 59b8ad81 bellard
{
346 59b8ad81 bellard
    /* XXX: send to all CPUs ? */
347 59b8ad81 bellard
    cpu_x86_set_a20(first_cpu, enable);
348 59b8ad81 bellard
}
349 59b8ad81 bellard
350 59b8ad81 bellard
int ioport_get_a20(void)
351 59b8ad81 bellard
{
352 59b8ad81 bellard
    return ((first_cpu->a20_mask >> 20) & 1);
353 59b8ad81 bellard
}
354 59b8ad81 bellard
355 e1a23744 bellard
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
356 e1a23744 bellard
{
357 59b8ad81 bellard
    ioport_set_a20((val >> 1) & 1);
358 e1a23744 bellard
    /* XXX: bit 0 is fast reset */
359 e1a23744 bellard
}
360 e1a23744 bellard
361 e1a23744 bellard
static uint32_t ioport92_read(void *opaque, uint32_t addr)
362 e1a23744 bellard
{
363 59b8ad81 bellard
    return ioport_get_a20() << 1;
364 e1a23744 bellard
}
365 e1a23744 bellard
366 80cabfad bellard
/***********************************************************/
367 80cabfad bellard
/* Bochs BIOS debug ports */
368 80cabfad bellard
369 9596ebb7 pbrook
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
370 80cabfad bellard
{
371 a2f659ee bellard
    static const char shutdown_str[8] = "Shutdown";
372 a2f659ee bellard
    static int shutdown_index = 0;
373 3b46e624 ths
374 80cabfad bellard
    switch(addr) {
375 80cabfad bellard
        /* Bochs BIOS messages */
376 80cabfad bellard
    case 0x400:
377 80cabfad bellard
    case 0x401:
378 80cabfad bellard
        fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
379 80cabfad bellard
        exit(1);
380 80cabfad bellard
    case 0x402:
381 80cabfad bellard
    case 0x403:
382 80cabfad bellard
#ifdef DEBUG_BIOS
383 80cabfad bellard
        fprintf(stderr, "%c", val);
384 80cabfad bellard
#endif
385 80cabfad bellard
        break;
386 a2f659ee bellard
    case 0x8900:
387 a2f659ee bellard
        /* same as Bochs power off */
388 a2f659ee bellard
        if (val == shutdown_str[shutdown_index]) {
389 a2f659ee bellard
            shutdown_index++;
390 a2f659ee bellard
            if (shutdown_index == 8) {
391 a2f659ee bellard
                shutdown_index = 0;
392 a2f659ee bellard
                qemu_system_shutdown_request();
393 a2f659ee bellard
            }
394 a2f659ee bellard
        } else {
395 a2f659ee bellard
            shutdown_index = 0;
396 a2f659ee bellard
        }
397 a2f659ee bellard
        break;
398 80cabfad bellard
399 80cabfad bellard
        /* LGPL'ed VGA BIOS messages */
400 80cabfad bellard
    case 0x501:
401 80cabfad bellard
    case 0x502:
402 80cabfad bellard
        fprintf(stderr, "VGA BIOS panic, line %d\n", val);
403 80cabfad bellard
        exit(1);
404 80cabfad bellard
    case 0x500:
405 80cabfad bellard
    case 0x503:
406 80cabfad bellard
#ifdef DEBUG_BIOS
407 80cabfad bellard
        fprintf(stderr, "%c", val);
408 80cabfad bellard
#endif
409 80cabfad bellard
        break;
410 80cabfad bellard
    }
411 80cabfad bellard
}
412 80cabfad bellard
413 9596ebb7 pbrook
static void bochs_bios_init(void)
414 80cabfad bellard
{
415 b41a2cd1 bellard
    register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
416 b41a2cd1 bellard
    register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
417 b41a2cd1 bellard
    register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
418 b41a2cd1 bellard
    register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
419 a2f659ee bellard
    register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
420 b41a2cd1 bellard
421 b41a2cd1 bellard
    register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
422 b41a2cd1 bellard
    register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
423 b41a2cd1 bellard
    register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
424 b41a2cd1 bellard
    register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
425 80cabfad bellard
}
426 80cabfad bellard
427 642a4f96 ths
/* Generate an initial boot sector which sets state and jump to
428 642a4f96 ths
   a specified vector */
429 3f6c925f balrog
static void generate_bootsect(uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
430 642a4f96 ths
{
431 642a4f96 ths
    uint8_t bootsect[512], *p;
432 642a4f96 ths
    int i;
433 e4bcb14c ths
    int hda;
434 642a4f96 ths
435 e4bcb14c ths
    hda = drive_get_index(IF_IDE, 0, 0);
436 e4bcb14c ths
    if (hda == -1) {
437 642a4f96 ths
        fprintf(stderr, "A disk image must be given for 'hda' when booting "
438 642a4f96 ths
                "a Linux kernel\n");
439 642a4f96 ths
        exit(1);
440 642a4f96 ths
    }
441 642a4f96 ths
442 642a4f96 ths
    memset(bootsect, 0, sizeof(bootsect));
443 642a4f96 ths
444 642a4f96 ths
    /* Copy the MSDOS partition table if possible */
445 e4bcb14c ths
    bdrv_read(drives_table[hda].bdrv, 0, bootsect, 1);
446 642a4f96 ths
447 642a4f96 ths
    /* Make sure we have a partition signature */
448 642a4f96 ths
    bootsect[510] = 0x55;
449 642a4f96 ths
    bootsect[511] = 0xaa;
450 642a4f96 ths
451 642a4f96 ths
    /* Actual code */
452 642a4f96 ths
    p = bootsect;
453 642a4f96 ths
    *p++ = 0xfa;                /* CLI */
454 642a4f96 ths
    *p++ = 0xfc;                /* CLD */
455 642a4f96 ths
456 642a4f96 ths
    for (i = 0; i < 6; i++) {
457 642a4f96 ths
        if (i == 1)                /* Skip CS */
458 642a4f96 ths
            continue;
459 642a4f96 ths
460 642a4f96 ths
        *p++ = 0xb8;                /* MOV AX,imm16 */
461 642a4f96 ths
        *p++ = segs[i];
462 642a4f96 ths
        *p++ = segs[i] >> 8;
463 642a4f96 ths
        *p++ = 0x8e;                /* MOV <seg>,AX */
464 642a4f96 ths
        *p++ = 0xc0 + (i << 3);
465 642a4f96 ths
    }
466 642a4f96 ths
467 642a4f96 ths
    for (i = 0; i < 8; i++) {
468 642a4f96 ths
        *p++ = 0x66;                /* 32-bit operand size */
469 642a4f96 ths
        *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
470 642a4f96 ths
        *p++ = gpr[i];
471 642a4f96 ths
        *p++ = gpr[i] >> 8;
472 642a4f96 ths
        *p++ = gpr[i] >> 16;
473 642a4f96 ths
        *p++ = gpr[i] >> 24;
474 642a4f96 ths
    }
475 642a4f96 ths
476 642a4f96 ths
    *p++ = 0xea;                /* JMP FAR */
477 642a4f96 ths
    *p++ = ip;                        /* IP */
478 642a4f96 ths
    *p++ = ip >> 8;
479 642a4f96 ths
    *p++ = segs[1];                /* CS */
480 642a4f96 ths
    *p++ = segs[1] >> 8;
481 642a4f96 ths
482 e4bcb14c ths
    bdrv_set_boot_sector(drives_table[hda].bdrv, bootsect, sizeof(bootsect));
483 642a4f96 ths
}
484 80cabfad bellard
485 642a4f96 ths
static long get_file_size(FILE *f)
486 642a4f96 ths
{
487 642a4f96 ths
    long where, size;
488 642a4f96 ths
489 642a4f96 ths
    /* XXX: on Unix systems, using fstat() probably makes more sense */
490 642a4f96 ths
491 642a4f96 ths
    where = ftell(f);
492 642a4f96 ths
    fseek(f, 0, SEEK_END);
493 642a4f96 ths
    size = ftell(f);
494 642a4f96 ths
    fseek(f, where, SEEK_SET);
495 642a4f96 ths
496 642a4f96 ths
    return size;
497 642a4f96 ths
}
498 642a4f96 ths
499 642a4f96 ths
static void load_linux(const char *kernel_filename,
500 642a4f96 ths
                       const char *initrd_filename,
501 642a4f96 ths
                       const char *kernel_cmdline)
502 642a4f96 ths
{
503 642a4f96 ths
    uint16_t protocol;
504 642a4f96 ths
    uint32_t gpr[8];
505 642a4f96 ths
    uint16_t seg[6];
506 642a4f96 ths
    uint16_t real_seg;
507 642a4f96 ths
    int setup_size, kernel_size, initrd_size, cmdline_size;
508 642a4f96 ths
    uint32_t initrd_max;
509 642a4f96 ths
    uint8_t header[1024];
510 a37af289 blueswir1
    target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr;
511 642a4f96 ths
    FILE *f, *fi;
512 642a4f96 ths
513 642a4f96 ths
    /* Align to 16 bytes as a paranoia measure */
514 642a4f96 ths
    cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
515 642a4f96 ths
516 642a4f96 ths
    /* load the kernel header */
517 642a4f96 ths
    f = fopen(kernel_filename, "rb");
518 642a4f96 ths
    if (!f || !(kernel_size = get_file_size(f)) ||
519 642a4f96 ths
        fread(header, 1, 1024, f) != 1024) {
520 642a4f96 ths
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
521 642a4f96 ths
                kernel_filename);
522 642a4f96 ths
        exit(1);
523 642a4f96 ths
    }
524 642a4f96 ths
525 642a4f96 ths
    /* kernel protocol version */
526 bc4edd79 bellard
#if 0
527 642a4f96 ths
    fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
528 bc4edd79 bellard
#endif
529 642a4f96 ths
    if (ldl_p(header+0x202) == 0x53726448)
530 642a4f96 ths
        protocol = lduw_p(header+0x206);
531 642a4f96 ths
    else
532 642a4f96 ths
        protocol = 0;
533 642a4f96 ths
534 642a4f96 ths
    if (protocol < 0x200 || !(header[0x211] & 0x01)) {
535 642a4f96 ths
        /* Low kernel */
536 a37af289 blueswir1
        real_addr    = 0x90000;
537 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
538 a37af289 blueswir1
        prot_addr    = 0x10000;
539 642a4f96 ths
    } else if (protocol < 0x202) {
540 642a4f96 ths
        /* High but ancient kernel */
541 a37af289 blueswir1
        real_addr    = 0x90000;
542 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
543 a37af289 blueswir1
        prot_addr    = 0x100000;
544 642a4f96 ths
    } else {
545 642a4f96 ths
        /* High and recent kernel */
546 a37af289 blueswir1
        real_addr    = 0x10000;
547 a37af289 blueswir1
        cmdline_addr = 0x20000;
548 a37af289 blueswir1
        prot_addr    = 0x100000;
549 642a4f96 ths
    }
550 642a4f96 ths
551 bc4edd79 bellard
#if 0
552 642a4f96 ths
    fprintf(stderr,
553 642a4f96 ths
            "qemu: real_addr     = %#zx\n"
554 642a4f96 ths
            "qemu: cmdline_addr  = %#zx\n"
555 642a4f96 ths
            "qemu: prot_addr     = %#zx\n",
556 a37af289 blueswir1
            real_addr,
557 a37af289 blueswir1
            cmdline_addr,
558 a37af289 blueswir1
            prot_addr);
559 bc4edd79 bellard
#endif
560 642a4f96 ths
561 642a4f96 ths
    /* highest address for loading the initrd */
562 642a4f96 ths
    if (protocol >= 0x203)
563 642a4f96 ths
        initrd_max = ldl_p(header+0x22c);
564 642a4f96 ths
    else
565 642a4f96 ths
        initrd_max = 0x37ffffff;
566 642a4f96 ths
567 642a4f96 ths
    if (initrd_max >= ram_size-ACPI_DATA_SIZE)
568 642a4f96 ths
        initrd_max = ram_size-ACPI_DATA_SIZE-1;
569 642a4f96 ths
570 642a4f96 ths
    /* kernel command line */
571 a37af289 blueswir1
    pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
572 642a4f96 ths
573 642a4f96 ths
    if (protocol >= 0x202) {
574 a37af289 blueswir1
        stl_p(header+0x228, cmdline_addr);
575 642a4f96 ths
    } else {
576 642a4f96 ths
        stw_p(header+0x20, 0xA33F);
577 642a4f96 ths
        stw_p(header+0x22, cmdline_addr-real_addr);
578 642a4f96 ths
    }
579 642a4f96 ths
580 642a4f96 ths
    /* loader type */
581 642a4f96 ths
    /* High nybble = B reserved for Qemu; low nybble is revision number.
582 642a4f96 ths
       If this code is substantially changed, you may want to consider
583 642a4f96 ths
       incrementing the revision. */
584 642a4f96 ths
    if (protocol >= 0x200)
585 642a4f96 ths
        header[0x210] = 0xB0;
586 642a4f96 ths
587 642a4f96 ths
    /* heap */
588 642a4f96 ths
    if (protocol >= 0x201) {
589 642a4f96 ths
        header[0x211] |= 0x80;        /* CAN_USE_HEAP */
590 642a4f96 ths
        stw_p(header+0x224, cmdline_addr-real_addr-0x200);
591 642a4f96 ths
    }
592 642a4f96 ths
593 642a4f96 ths
    /* load initrd */
594 642a4f96 ths
    if (initrd_filename) {
595 642a4f96 ths
        if (protocol < 0x200) {
596 642a4f96 ths
            fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
597 642a4f96 ths
            exit(1);
598 642a4f96 ths
        }
599 642a4f96 ths
600 642a4f96 ths
        fi = fopen(initrd_filename, "rb");
601 642a4f96 ths
        if (!fi) {
602 642a4f96 ths
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
603 642a4f96 ths
                    initrd_filename);
604 642a4f96 ths
            exit(1);
605 642a4f96 ths
        }
606 642a4f96 ths
607 642a4f96 ths
        initrd_size = get_file_size(fi);
608 a37af289 blueswir1
        initrd_addr = (initrd_max-initrd_size) & ~4095;
609 642a4f96 ths
610 642a4f96 ths
        fprintf(stderr, "qemu: loading initrd (%#x bytes) at %#zx\n",
611 a37af289 blueswir1
                initrd_size, initrd_addr);
612 642a4f96 ths
613 a37af289 blueswir1
        if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
614 642a4f96 ths
            fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
615 642a4f96 ths
                    initrd_filename);
616 642a4f96 ths
            exit(1);
617 642a4f96 ths
        }
618 642a4f96 ths
        fclose(fi);
619 642a4f96 ths
620 a37af289 blueswir1
        stl_p(header+0x218, initrd_addr);
621 642a4f96 ths
        stl_p(header+0x21c, initrd_size);
622 642a4f96 ths
    }
623 642a4f96 ths
624 642a4f96 ths
    /* store the finalized header and load the rest of the kernel */
625 a37af289 blueswir1
    cpu_physical_memory_write(real_addr, header, 1024);
626 642a4f96 ths
627 642a4f96 ths
    setup_size = header[0x1f1];
628 642a4f96 ths
    if (setup_size == 0)
629 642a4f96 ths
        setup_size = 4;
630 642a4f96 ths
631 642a4f96 ths
    setup_size = (setup_size+1)*512;
632 642a4f96 ths
    kernel_size -= setup_size;        /* Size of protected-mode code */
633 642a4f96 ths
634 a37af289 blueswir1
    if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
635 a37af289 blueswir1
        !fread_targphys_ok(prot_addr, kernel_size, f)) {
636 642a4f96 ths
        fprintf(stderr, "qemu: read error on kernel '%s'\n",
637 642a4f96 ths
                kernel_filename);
638 642a4f96 ths
        exit(1);
639 642a4f96 ths
    }
640 642a4f96 ths
    fclose(f);
641 642a4f96 ths
642 642a4f96 ths
    /* generate bootsector to set up the initial register state */
643 a37af289 blueswir1
    real_seg = real_addr >> 4;
644 642a4f96 ths
    seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
645 642a4f96 ths
    seg[1] = real_seg+0x20;        /* CS */
646 642a4f96 ths
    memset(gpr, 0, sizeof gpr);
647 642a4f96 ths
    gpr[4] = cmdline_addr-real_addr-16;        /* SP (-16 is paranoia) */
648 642a4f96 ths
649 642a4f96 ths
    generate_bootsect(gpr, seg, 0);
650 642a4f96 ths
}
651 642a4f96 ths
652 59b8ad81 bellard
static void main_cpu_reset(void *opaque)
653 59b8ad81 bellard
{
654 59b8ad81 bellard
    CPUState *env = opaque;
655 59b8ad81 bellard
    cpu_reset(env);
656 59b8ad81 bellard
}
657 59b8ad81 bellard
658 b41a2cd1 bellard
static const int ide_iobase[2] = { 0x1f0, 0x170 };
659 b41a2cd1 bellard
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
660 b41a2cd1 bellard
static const int ide_irq[2] = { 14, 15 };
661 b41a2cd1 bellard
662 b41a2cd1 bellard
#define NE2000_NB_MAX 6
663 b41a2cd1 bellard
664 8d11df9e bellard
static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
665 b41a2cd1 bellard
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
666 b41a2cd1 bellard
667 8d11df9e bellard
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
668 8d11df9e bellard
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
669 8d11df9e bellard
670 6508fe59 bellard
static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
671 6508fe59 bellard
static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
672 6508fe59 bellard
673 6a36d84e bellard
#ifdef HAS_AUDIO
674 d537cf6c pbrook
static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
675 6a36d84e bellard
{
676 6a36d84e bellard
    struct soundhw *c;
677 6a36d84e bellard
    int audio_enabled = 0;
678 6a36d84e bellard
679 6a36d84e bellard
    for (c = soundhw; !audio_enabled && c->name; ++c) {
680 6a36d84e bellard
        audio_enabled = c->enabled;
681 6a36d84e bellard
    }
682 6a36d84e bellard
683 6a36d84e bellard
    if (audio_enabled) {
684 6a36d84e bellard
        AudioState *s;
685 6a36d84e bellard
686 6a36d84e bellard
        s = AUD_init ();
687 6a36d84e bellard
        if (s) {
688 6a36d84e bellard
            for (c = soundhw; c->name; ++c) {
689 6a36d84e bellard
                if (c->enabled) {
690 6a36d84e bellard
                    if (c->isa) {
691 d537cf6c pbrook
                        c->init.init_isa (s, pic);
692 6a36d84e bellard
                    }
693 6a36d84e bellard
                    else {
694 6a36d84e bellard
                        if (pci_bus) {
695 6a36d84e bellard
                            c->init.init_pci (pci_bus, s);
696 6a36d84e bellard
                        }
697 6a36d84e bellard
                    }
698 6a36d84e bellard
                }
699 6a36d84e bellard
            }
700 6a36d84e bellard
        }
701 6a36d84e bellard
    }
702 6a36d84e bellard
}
703 6a36d84e bellard
#endif
704 6a36d84e bellard
705 d537cf6c pbrook
static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
706 a41b2ff2 pbrook
{
707 a41b2ff2 pbrook
    static int nb_ne2k = 0;
708 a41b2ff2 pbrook
709 a41b2ff2 pbrook
    if (nb_ne2k == NE2000_NB_MAX)
710 a41b2ff2 pbrook
        return;
711 d537cf6c pbrook
    isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
712 a41b2ff2 pbrook
    nb_ne2k++;
713 a41b2ff2 pbrook
}
714 a41b2ff2 pbrook
715 80cabfad bellard
/* PC hardware initialisation */
716 00f82b8a aurel32
static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
717 b881c2c6 blueswir1
                     const char *boot_device, DisplayState *ds,
718 b5ff2d6e bellard
                     const char *kernel_filename, const char *kernel_cmdline,
719 3dbbdc25 bellard
                     const char *initrd_filename,
720 a049de61 bellard
                     int pci_enabled, const char *cpu_model)
721 80cabfad bellard
{
722 80cabfad bellard
    char buf[1024];
723 642a4f96 ths
    int ret, linux_boot, i;
724 970ac5a3 bellard
    ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
725 00f82b8a aurel32
    ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
726 970ac5a3 bellard
    int bios_size, isa_bios_size, vga_bios_size;
727 46e50e9d bellard
    PCIBus *pci_bus;
728 5c3ff3a7 pbrook
    int piix3_devfn = -1;
729 59b8ad81 bellard
    CPUState *env;
730 a41b2ff2 pbrook
    NICInfo *nd;
731 d537cf6c pbrook
    qemu_irq *cpu_irq;
732 d537cf6c pbrook
    qemu_irq *i8259;
733 e4bcb14c ths
    int index;
734 e4bcb14c ths
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
735 e4bcb14c ths
    BlockDriverState *fd[MAX_FD];
736 d592d303 bellard
737 00f82b8a aurel32
    if (ram_size >= 0xe0000000 ) {
738 00f82b8a aurel32
        above_4g_mem_size = ram_size - 0xe0000000;
739 00f82b8a aurel32
        below_4g_mem_size = 0xe0000000;
740 00f82b8a aurel32
    } else {
741 00f82b8a aurel32
        below_4g_mem_size = ram_size;
742 00f82b8a aurel32
    }
743 00f82b8a aurel32
744 0ecdffbb aurel32
    qemu_register_boot_set(pc_boot_set);
745 0ecdffbb aurel32
746 80cabfad bellard
    linux_boot = (kernel_filename != NULL);
747 80cabfad bellard
748 59b8ad81 bellard
    /* init CPUs */
749 a049de61 bellard
    if (cpu_model == NULL) {
750 a049de61 bellard
#ifdef TARGET_X86_64
751 a049de61 bellard
        cpu_model = "qemu64";
752 a049de61 bellard
#else
753 a049de61 bellard
        cpu_model = "qemu32";
754 a049de61 bellard
#endif
755 a049de61 bellard
    }
756 a049de61 bellard
    
757 59b8ad81 bellard
    for(i = 0; i < smp_cpus; i++) {
758 aaed909a bellard
        env = cpu_init(cpu_model);
759 aaed909a bellard
        if (!env) {
760 aaed909a bellard
            fprintf(stderr, "Unable to find x86 CPU definition\n");
761 aaed909a bellard
            exit(1);
762 aaed909a bellard
        }
763 59b8ad81 bellard
        if (i != 0)
764 ce5232c5 bellard
            env->halted = 1;
765 59b8ad81 bellard
        if (smp_cpus > 1) {
766 59b8ad81 bellard
            /* XXX: enable it in all cases */
767 59b8ad81 bellard
            env->cpuid_features |= CPUID_APIC;
768 59b8ad81 bellard
        }
769 5cc1d1e6 bellard
        register_savevm("cpu", i, 5, cpu_save, cpu_load, env);
770 59b8ad81 bellard
        qemu_register_reset(main_cpu_reset, env);
771 59b8ad81 bellard
        if (pci_enabled) {
772 59b8ad81 bellard
            apic_init(env);
773 59b8ad81 bellard
        }
774 59b8ad81 bellard
    }
775 59b8ad81 bellard
776 26fb5e48 aurel32
    vmport_init();
777 26fb5e48 aurel32
778 80cabfad bellard
    /* allocate RAM */
779 970ac5a3 bellard
    ram_addr = qemu_ram_alloc(ram_size);
780 00f82b8a aurel32
    cpu_register_physical_memory(0, below_4g_mem_size, ram_addr);
781 00f82b8a aurel32
782 00f82b8a aurel32
    /* above 4giga memory allocation */
783 00f82b8a aurel32
    if (above_4g_mem_size > 0) {
784 00f82b8a aurel32
        cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
785 00f82b8a aurel32
                                     ram_addr + below_4g_mem_size);
786 00f82b8a aurel32
    }
787 80cabfad bellard
788 970ac5a3 bellard
    /* allocate VGA RAM */
789 970ac5a3 bellard
    vga_ram_addr = qemu_ram_alloc(vga_ram_size);
790 7587cf44 bellard
791 970ac5a3 bellard
    /* BIOS load */
792 1192dad8 j_mayer
    if (bios_name == NULL)
793 1192dad8 j_mayer
        bios_name = BIOS_FILENAME;
794 1192dad8 j_mayer
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
795 7587cf44 bellard
    bios_size = get_image_size(buf);
796 5fafdf24 ths
    if (bios_size <= 0 ||
797 970ac5a3 bellard
        (bios_size % 65536) != 0) {
798 7587cf44 bellard
        goto bios_error;
799 7587cf44 bellard
    }
800 970ac5a3 bellard
    bios_offset = qemu_ram_alloc(bios_size);
801 7587cf44 bellard
    ret = load_image(buf, phys_ram_base + bios_offset);
802 7587cf44 bellard
    if (ret != bios_size) {
803 7587cf44 bellard
    bios_error:
804 970ac5a3 bellard
        fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
805 80cabfad bellard
        exit(1);
806 80cabfad bellard
    }
807 7587cf44 bellard
808 80cabfad bellard
    /* VGA BIOS load */
809 de9258a8 bellard
    if (cirrus_vga_enabled) {
810 de9258a8 bellard
        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME);
811 de9258a8 bellard
    } else {
812 de9258a8 bellard
        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
813 de9258a8 bellard
    }
814 970ac5a3 bellard
    vga_bios_size = get_image_size(buf);
815 5fafdf24 ths
    if (vga_bios_size <= 0 || vga_bios_size > 65536)
816 970ac5a3 bellard
        goto vga_bios_error;
817 970ac5a3 bellard
    vga_bios_offset = qemu_ram_alloc(65536);
818 970ac5a3 bellard
819 7587cf44 bellard
    ret = load_image(buf, phys_ram_base + vga_bios_offset);
820 970ac5a3 bellard
    if (ret != vga_bios_size) {
821 970ac5a3 bellard
    vga_bios_error:
822 970ac5a3 bellard
        fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf);
823 970ac5a3 bellard
        exit(1);
824 970ac5a3 bellard
    }
825 970ac5a3 bellard
826 80cabfad bellard
    /* setup basic memory access */
827 5fafdf24 ths
    cpu_register_physical_memory(0xc0000, 0x10000,
828 7587cf44 bellard
                                 vga_bios_offset | IO_MEM_ROM);
829 7587cf44 bellard
830 7587cf44 bellard
    /* map the last 128KB of the BIOS in ISA space */
831 7587cf44 bellard
    isa_bios_size = bios_size;
832 7587cf44 bellard
    if (isa_bios_size > (128 * 1024))
833 7587cf44 bellard
        isa_bios_size = 128 * 1024;
834 5fafdf24 ths
    cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
835 7587cf44 bellard
                                 IO_MEM_UNASSIGNED);
836 5fafdf24 ths
    cpu_register_physical_memory(0x100000 - isa_bios_size,
837 5fafdf24 ths
                                 isa_bios_size,
838 7587cf44 bellard
                                 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
839 9ae02555 ths
840 970ac5a3 bellard
    {
841 970ac5a3 bellard
        ram_addr_t option_rom_offset;
842 970ac5a3 bellard
        int size, offset;
843 970ac5a3 bellard
844 970ac5a3 bellard
        offset = 0;
845 970ac5a3 bellard
        for (i = 0; i < nb_option_roms; i++) {
846 970ac5a3 bellard
            size = get_image_size(option_rom[i]);
847 970ac5a3 bellard
            if (size < 0) {
848 5fafdf24 ths
                fprintf(stderr, "Could not load option rom '%s'\n",
849 970ac5a3 bellard
                        option_rom[i]);
850 970ac5a3 bellard
                exit(1);
851 970ac5a3 bellard
            }
852 970ac5a3 bellard
            if (size > (0x10000 - offset))
853 970ac5a3 bellard
                goto option_rom_error;
854 970ac5a3 bellard
            option_rom_offset = qemu_ram_alloc(size);
855 970ac5a3 bellard
            ret = load_image(option_rom[i], phys_ram_base + option_rom_offset);
856 970ac5a3 bellard
            if (ret != size) {
857 970ac5a3 bellard
            option_rom_error:
858 970ac5a3 bellard
                fprintf(stderr, "Too many option ROMS\n");
859 970ac5a3 bellard
                exit(1);
860 970ac5a3 bellard
            }
861 970ac5a3 bellard
            size = (size + 4095) & ~4095;
862 970ac5a3 bellard
            cpu_register_physical_memory(0xd0000 + offset,
863 970ac5a3 bellard
                                         size, option_rom_offset | IO_MEM_ROM);
864 970ac5a3 bellard
            offset += size;
865 970ac5a3 bellard
        }
866 9ae02555 ths
    }
867 9ae02555 ths
868 7587cf44 bellard
    /* map all the bios at the top of memory */
869 5fafdf24 ths
    cpu_register_physical_memory((uint32_t)(-bios_size),
870 7587cf44 bellard
                                 bios_size, bios_offset | IO_MEM_ROM);
871 3b46e624 ths
872 80cabfad bellard
    bochs_bios_init();
873 80cabfad bellard
874 642a4f96 ths
    if (linux_boot)
875 642a4f96 ths
        load_linux(kernel_filename, initrd_filename, kernel_cmdline);
876 80cabfad bellard
877 a5b38b51 aurel32
    cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
878 d537cf6c pbrook
    i8259 = i8259_init(cpu_irq[0]);
879 d537cf6c pbrook
    ferr_irq = i8259[13];
880 d537cf6c pbrook
881 69b91039 bellard
    if (pci_enabled) {
882 d537cf6c pbrook
        pci_bus = i440fx_init(&i440fx_state, i8259);
883 8f1c91d8 ths
        piix3_devfn = piix3_init(pci_bus, -1);
884 46e50e9d bellard
    } else {
885 46e50e9d bellard
        pci_bus = NULL;
886 69b91039 bellard
    }
887 69b91039 bellard
888 80cabfad bellard
    /* init basic PC hardware */
889 b41a2cd1 bellard
    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
890 80cabfad bellard
891 f929aad6 bellard
    register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
892 f929aad6 bellard
893 1f04275e bellard
    if (cirrus_vga_enabled) {
894 1f04275e bellard
        if (pci_enabled) {
895 5fafdf24 ths
            pci_cirrus_vga_init(pci_bus,
896 5fafdf24 ths
                                ds, phys_ram_base + vga_ram_addr,
897 970ac5a3 bellard
                                vga_ram_addr, vga_ram_size);
898 1f04275e bellard
        } else {
899 5fafdf24 ths
            isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr,
900 970ac5a3 bellard
                                vga_ram_addr, vga_ram_size);
901 1f04275e bellard
        }
902 d34cab9f ths
    } else if (vmsvga_enabled) {
903 d34cab9f ths
        if (pci_enabled)
904 45e4522e balrog
            pci_vmsvga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
905 45e4522e balrog
                            vga_ram_addr, vga_ram_size);
906 d34cab9f ths
        else
907 d34cab9f ths
            fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
908 1f04275e bellard
    } else {
909 89b6b508 bellard
        if (pci_enabled) {
910 5fafdf24 ths
            pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
911 970ac5a3 bellard
                         vga_ram_addr, vga_ram_size, 0, 0);
912 89b6b508 bellard
        } else {
913 5fafdf24 ths
            isa_vga_init(ds, phys_ram_base + vga_ram_addr,
914 970ac5a3 bellard
                         vga_ram_addr, vga_ram_size);
915 89b6b508 bellard
        }
916 1f04275e bellard
    }
917 80cabfad bellard
918 d537cf6c pbrook
    rtc_state = rtc_init(0x70, i8259[8]);
919 80cabfad bellard
920 e1a23744 bellard
    register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
921 e1a23744 bellard
    register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
922 e1a23744 bellard
923 d592d303 bellard
    if (pci_enabled) {
924 d592d303 bellard
        ioapic = ioapic_init();
925 d592d303 bellard
    }
926 d537cf6c pbrook
    pit = pit_init(0x40, i8259[0]);
927 fd06c375 bellard
    pcspk_init(pit);
928 d592d303 bellard
    if (pci_enabled) {
929 d592d303 bellard
        pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
930 d592d303 bellard
    }
931 b41a2cd1 bellard
932 8d11df9e bellard
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
933 8d11df9e bellard
        if (serial_hds[i]) {
934 b6cd0ea1 aurel32
            serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
935 b6cd0ea1 aurel32
                        serial_hds[i]);
936 8d11df9e bellard
        }
937 8d11df9e bellard
    }
938 b41a2cd1 bellard
939 6508fe59 bellard
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
940 6508fe59 bellard
        if (parallel_hds[i]) {
941 d537cf6c pbrook
            parallel_init(parallel_io[i], i8259[parallel_irq[i]],
942 d537cf6c pbrook
                          parallel_hds[i]);
943 6508fe59 bellard
        }
944 6508fe59 bellard
    }
945 6508fe59 bellard
946 a41b2ff2 pbrook
    for(i = 0; i < nb_nics; i++) {
947 a41b2ff2 pbrook
        nd = &nd_table[i];
948 a41b2ff2 pbrook
        if (!nd->model) {
949 a41b2ff2 pbrook
            if (pci_enabled) {
950 a41b2ff2 pbrook
                nd->model = "ne2k_pci";
951 a41b2ff2 pbrook
            } else {
952 a41b2ff2 pbrook
                nd->model = "ne2k_isa";
953 a41b2ff2 pbrook
            }
954 69b91039 bellard
        }
955 a41b2ff2 pbrook
        if (strcmp(nd->model, "ne2k_isa") == 0) {
956 d537cf6c pbrook
            pc_init_ne2k_isa(nd, i8259);
957 a41b2ff2 pbrook
        } else if (pci_enabled) {
958 c4a7060c blueswir1
            if (strcmp(nd->model, "?") == 0)
959 c4a7060c blueswir1
                fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
960 abcebc7e ths
            pci_nic_init(pci_bus, nd, -1);
961 c4a7060c blueswir1
        } else if (strcmp(nd->model, "?") == 0) {
962 c4a7060c blueswir1
            fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
963 c4a7060c blueswir1
            exit(1);
964 a41b2ff2 pbrook
        } else {
965 a41b2ff2 pbrook
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
966 a41b2ff2 pbrook
            exit(1);
967 69b91039 bellard
        }
968 a41b2ff2 pbrook
    }
969 b41a2cd1 bellard
970 e4bcb14c ths
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
971 e4bcb14c ths
        fprintf(stderr, "qemu: too many IDE bus\n");
972 e4bcb14c ths
        exit(1);
973 e4bcb14c ths
    }
974 e4bcb14c ths
975 e4bcb14c ths
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
976 e4bcb14c ths
        index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
977 e4bcb14c ths
        if (index != -1)
978 e4bcb14c ths
            hd[i] = drives_table[index].bdrv;
979 e4bcb14c ths
        else
980 e4bcb14c ths
            hd[i] = NULL;
981 e4bcb14c ths
    }
982 e4bcb14c ths
983 a41b2ff2 pbrook
    if (pci_enabled) {
984 e4bcb14c ths
        pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
985 a41b2ff2 pbrook
    } else {
986 e4bcb14c ths
        for(i = 0; i < MAX_IDE_BUS; i++) {
987 d537cf6c pbrook
            isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
988 e4bcb14c ths
                         hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
989 69b91039 bellard
        }
990 b41a2cd1 bellard
    }
991 69b91039 bellard
992 d537cf6c pbrook
    i8042_init(i8259[1], i8259[12], 0x60);
993 7c29d0c0 bellard
    DMA_init(0);
994 6a36d84e bellard
#ifdef HAS_AUDIO
995 d537cf6c pbrook
    audio_init(pci_enabled ? pci_bus : NULL, i8259);
996 fb065187 bellard
#endif
997 80cabfad bellard
998 e4bcb14c ths
    for(i = 0; i < MAX_FD; i++) {
999 e4bcb14c ths
        index = drive_get_index(IF_FLOPPY, 0, i);
1000 e4bcb14c ths
        if (index != -1)
1001 e4bcb14c ths
            fd[i] = drives_table[index].bdrv;
1002 e4bcb14c ths
        else
1003 e4bcb14c ths
            fd[i] = NULL;
1004 e4bcb14c ths
    }
1005 e4bcb14c ths
    floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1006 b41a2cd1 bellard
1007 00f82b8a aurel32
    cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1008 69b91039 bellard
1009 bb36d470 bellard
    if (pci_enabled && usb_enabled) {
1010 afcc3cdf ths
        usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1011 bb36d470 bellard
    }
1012 bb36d470 bellard
1013 6515b203 bellard
    if (pci_enabled && acpi_enabled) {
1014 3fffc223 ths
        uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1015 0ff596d0 pbrook
        i2c_bus *smbus;
1016 0ff596d0 pbrook
1017 0ff596d0 pbrook
        /* TODO: Populate SPD eeprom data.  */
1018 cf7a2fe2 aurel32
        smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1019 3fffc223 ths
        for (i = 0; i < 8; i++) {
1020 0ff596d0 pbrook
            smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
1021 3fffc223 ths
        }
1022 6515b203 bellard
    }
1023 3b46e624 ths
1024 a5954d5c bellard
    if (i440fx_state) {
1025 a5954d5c bellard
        i440fx_init_memory_mappings(i440fx_state);
1026 a5954d5c bellard
    }
1027 e4bcb14c ths
1028 7d8406be pbrook
    if (pci_enabled) {
1029 e4bcb14c ths
        int max_bus;
1030 e4bcb14c ths
        int bus, unit;
1031 7d8406be pbrook
        void *scsi;
1032 96d30e48 ths
1033 e4bcb14c ths
        max_bus = drive_get_max_bus(IF_SCSI);
1034 e4bcb14c ths
1035 e4bcb14c ths
        for (bus = 0; bus <= max_bus; bus++) {
1036 e4bcb14c ths
            scsi = lsi_scsi_init(pci_bus, -1);
1037 e4bcb14c ths
            for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
1038 e4bcb14c ths
                index = drive_get_index(IF_SCSI, bus, unit);
1039 e4bcb14c ths
                if (index == -1)
1040 e4bcb14c ths
                    continue;
1041 e4bcb14c ths
                lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
1042 e4bcb14c ths
            }
1043 e4bcb14c ths
        }
1044 7d8406be pbrook
    }
1045 80cabfad bellard
}
1046 b5ff2d6e bellard
1047 00f82b8a aurel32
static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
1048 b881c2c6 blueswir1
                        const char *boot_device, DisplayState *ds,
1049 5fafdf24 ths
                        const char *kernel_filename,
1050 3dbbdc25 bellard
                        const char *kernel_cmdline,
1051 94fc95cd j_mayer
                        const char *initrd_filename,
1052 94fc95cd j_mayer
                        const char *cpu_model)
1053 3dbbdc25 bellard
{
1054 b881c2c6 blueswir1
    pc_init1(ram_size, vga_ram_size, boot_device, ds,
1055 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1056 a049de61 bellard
             initrd_filename, 1, cpu_model);
1057 3dbbdc25 bellard
}
1058 3dbbdc25 bellard
1059 00f82b8a aurel32
static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
1060 b881c2c6 blueswir1
                        const char *boot_device, DisplayState *ds,
1061 5fafdf24 ths
                        const char *kernel_filename,
1062 3dbbdc25 bellard
                        const char *kernel_cmdline,
1063 94fc95cd j_mayer
                        const char *initrd_filename,
1064 94fc95cd j_mayer
                        const char *cpu_model)
1065 3dbbdc25 bellard
{
1066 b881c2c6 blueswir1
    pc_init1(ram_size, vga_ram_size, boot_device, ds,
1067 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1068 a049de61 bellard
             initrd_filename, 0, cpu_model);
1069 3dbbdc25 bellard
}
1070 3dbbdc25 bellard
1071 b5ff2d6e bellard
QEMUMachine pc_machine = {
1072 b5ff2d6e bellard
    "pc",
1073 b5ff2d6e bellard
    "Standard PC",
1074 3dbbdc25 bellard
    pc_init_pci,
1075 7fb4fdcf balrog
    VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1076 3dbbdc25 bellard
};
1077 3dbbdc25 bellard
1078 3dbbdc25 bellard
QEMUMachine isapc_machine = {
1079 3dbbdc25 bellard
    "isapc",
1080 3dbbdc25 bellard
    "ISA-only PC",
1081 3dbbdc25 bellard
    pc_init_isa,
1082 7fb4fdcf balrog
    VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1083 b5ff2d6e bellard
};