Revision 5cc7a967
| b/hw/ppc/spapr_pci.c | ||
|---|---|---|
| 432 | 432 |
qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
| 433 | 433 |
} |
| 434 | 434 |
|
| 435 |
static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) |
|
| 436 |
{
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|
| 437 |
sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); |
|
| 438 |
PCIINTxRoute route; |
|
| 439 |
|
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| 440 |
route.mode = PCI_INTX_ENABLED; |
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| 441 |
route.irq = sphb->lsi_table[pin].irq; |
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| 442 |
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return route; |
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| 444 |
} |
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| 445 |
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| 435 | 446 |
/* |
| 436 | 447 |
* MSI/MSIX memory region implementation. |
| 437 | 448 |
* The handler handles both MSI and MSIX. |
| ... | ... | |
| 610 | 621 |
|
| 611 | 622 |
pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); |
| 612 | 623 |
|
| 624 |
pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); |
|
| 625 |
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| 613 | 626 |
QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); |
| 614 | 627 |
|
| 615 | 628 |
/* Initialize the LSI table */ |
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