exec: Make stw_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
exec: Make stl_phys_notdirty input an AddressSpace
exec: Make stl_*_phys input an AddressSpace
exec: Make stq_*_phys input an AddressSpace
exec: Make lduw_*_phys input an AddressSpace
exec: Make ldq/ldub_*_phys input an AddressSpace
exec: Make ldl_*_phys input an AddressSpace
exec: On AS changes, only flush affected CPU TLBs
cpu: Add per-cpu address space
memory: Add MemoryListener to typedefs.h
exec: Make memory_region_section_get_iotlb use section AS
exec: Always initialize MemorySection address spaces
exec: Make iotlb_to_region input an AS
exec: Make tb_invalidate_phys_addr input an AS
No functional change.
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140208' into staging
target-arm queue: * more A64 Neon instructions * AArch32 VCVTB and VCVTT ARMv8 instructions * fixes to inaccuracies in GIC emulation * libvixl disassembler for A64...
Merge remote-tracking branch 'remotes/kvaneesh/for-upstream' into staging
memory: fix limiting of translation at a page boundary
Commit 360e607 (address_space_translate: do not cross page boundaries,2014-01-30) broke MMIO accesses in cases where the section is shorterthan the full register width. This can happen for example with the...
Merge remote-tracking branch 'remotes/mwalle/tags/lm32-fixes/20140204' into staging
target-lm32: fixes
arm_gic: Support setting/getting binary point reg
Add a binary_point field to the gic emulation structure and supportsetting/getting this register now when we have it. We don't actuallysupport interrupt grouping yet, oh well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
vmstate: Add uint32 2D-array support
Add support for saving VMState of 2D arrays of uint32 values.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
arm_gic: Add GICC_APRn state to the GICState
The GICC_APRn registers are not currently supported by the ARM GIC v2.0emulation. This patch adds the missing state.
Note that we also change the number of APRs to use a define GIC_NR_APRSbased on the maximum number of preemption levels. This patch also adds...
rules.mak: Support .cc as a C++ source file suffix
The A64 disassembler libvixl uses .cc as its suffix forC++ source files, so add support for it (we already support.cpp).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
rules.mak: Link with C++ if we have a C++ compiler
If we have a C++ compiler available, link with it, because we might belinking some C++ files in. This allows us to include C++ object filesin the QEMU binary proper.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
disas: Add subset of libvixl sources for A64 disassembler
Add the subset of the libvixl sources that are needed for theA64 disassembler support. These sources come fromhttps://github.com/armvixl/vixl commit 578645f14e122d2bwhich is VIXL release 1.1.
disas/libvixl: Fix upstream libvixl compilation issues
Fix various minor issues with upstream libvixl so that it will compilesuccessfully on the platforms QEMU cares about: * remove unused GBytes constant (it clashes with the glib headers) * fix suffixes on constants to use 'LL' for 64 bit constants so...
disas: Implement disassembly output for A64
Use libvixl to implement disassembly output in debuglogs for A64, for use with both AArch64 hosts and targets.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>[PMM: * added support for target disassembly...
util/fifo8: implement push/pop of multiple bytes
The patch adds functions fifo8_push_all() and fifo8_pop_buf() whichcan be used respectively to push the content of a memory buffer to thefifo and to pop multiple bytes obtaining a pointer to the fifo backing...
util/fifo8: clear fifo head upon reset
To improve the predictability of fifo8_pop_buf(), the fifo head is setto the start of data buffer upon a reset so that the first call to thefunction will be able to retrieve all data in the fifo.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>...
hw/net: add support for Allwinner EMAC Fast Ethernet controller
This patch adds support for the Fast Ethernet MAC found on AllwinnerSoCs, together with a basic emulation of Realtek RTL8201CP PHY.
Since there is no public documentation of the Allwinner controller, the...
hw/arm/allwinner-a10: initialize EMAC
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
arm/zynq: Add software system reset via SCLR
Support software-driven system reset via the register in the SCLR.
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement 2-register misc compares, ABS, NEG
Implement the simple 2-register-misc operations we can sharewith the scalar-two-register-misc code. (SUQADD, USQADD, SQABS,SQNEG also fall into this category, but aren't implemented inthe scalar-2-register case yet either.)...
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
Implement the 2-reg-misc CNT, NOT and RBIT instructions.
target-arm: A64: Add narrowing 2-reg-misc instructions
Add the narrowing integer instructions in the 2-reg-misc class.
target-arm: A64: Add 2-reg-misc REV* instructions
Add the byte-reverse operations REV64, REV32 and REV16 from thetwo-reg-misc group.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group.
target-arm: Add support for AArch32 64bit VCVTB and VCVTT
Add support for the AArch32 floating-point half-precision to double-precision conversion VCVTB and VCVTT instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>[PMM: fixed a minor missing-braces style issue]...
arm_gic: Fix GIC pending behavior
The existing implementation of the pending behavior in gic_set_irq,gic_complete_irq, and the distributor pending set/clear registers doesnot follow the semantics of the GICv2.0 specs, but may implement the11MPCore support. Therefore, maintain the existing semantics for...
arm_gic: Keep track of SGI sources
Right now the arm gic emulation doesn't keep track of the source of anSGI (which apparently Linux guests don't use, or they're fine withassuming CPU 0 always).
Add the necessary matrix on the GICState structure and maintain the data...
target-arm: A64: Implement scalar pairwise ops
Implement the instructions in the scalar pairwise group (C3.6.8).
target-arm: A64: Implement remaining integer scalar-3-same insns
Implement the remaining integer instructions in the scalar-three-reg-samegroup: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL,SQDMULH, SQRDMULH.
target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
Implement the simple 64 bit integer operations from the SIMDscalar 2-register misc group (C3.6.12): the comparisons againstzero, plus ABS and NEG.
target-arm: A64: Add skeleton decode for SIMD 2-reg misc group
Add a skeleton decode for the SIMD 2-reg misc group.
target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
Implement the SIMD 3-reg-same instructions SQADD, UQADD,SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL,SQRSHL, UQRSHL; these are all simple calls to existingNeon helpers. We also enable SSHL, USHL, SRSHL and URSHL...
target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns
Implement the SIMD 3-reg-same instructions where the size == 3 caseis reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX,UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL,...
target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
Implement the pairwise integer operations in the 3-reg-same SIMD group:ADDP, SMAXP, SMINP, UMAXP and UMINP.
tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR
We have macros for marking TCGv values as unused, checking if theyare unused and comparing them to each other. However these only existfor TCGv_i32 and TCGv_i64; add them for TCGv_ptr as well....
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20140204-1' into staging
migration/next for 20140204
Merge remote-tracking branch 'remotes/kraxel/tags/pull-roms-1' into staging
Update seabios to 1.7.4
Merge remote-tracking branch 'remotes/stefanha/tags/qtest-for-peter' into staging
qtest resource cleanup patches
Merge remote-tracking branch 'remotes/kvm/uq/master' into staging
Merge remote-tracking branch 'remotes/spice/tags/pull-spice-2' into staging
misc spice patches
Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-02-02' into staging
trivial patches for 2014-02-02
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging
Block pull request
lm32_sys: dump cpu state if test case fails
This will ease debugging the test cases.
Signed-off-by: Michael Walle <michael@walle.cc>
target-lm32: stop VM on illegal or unknown instruction
Instead of translating the instruction to a no-op, pause the VM and displaya message to the user.
As a side effect, this also works for instructions where the operands areonly known at runtime.
hw/lm32: print error if cpu model is not found
QEMU crashed if a the given cpu_model is not found.
Signed-off-by: Michael Walle <michael@walle.cc>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
lm32_sys: print test result on stderr
Do not use qemu_log().
target-lm32: add breakpoint/watchpoint support
This patch adds in-target breakpoint and watchpoint support.
Merge remote-tracking branch 'remotes/borntraeger/tags/kvm-s390-20140131' into staging
This patch set contains the sclp defines and events for cpu hotplug,the initial sclp defines (without code yet) for standby memory (somesort of memory hotplug) as well as a cleanup of the kvm register...
lm32_uart/lm32_juart: use qemu_chr_fe_write_all()
qemu_chr_fe_write() may return EAGAIN. Therefore, useqemu_chr_fe_write_all().
milkymist-vgafb: swap pixel data in source buffer
In commit fc97bb5ba3e7239c0b6d24095df6784868dfebbf the lduw_raw() call waseliminated. But we are reading from the target buffer a 16-bit value, whichis in big-endian format. Therefore, use lduw_be_p() to read the value....
target-lm32: kill cpu_abort() calls
Instead of killing QEMU, translate instructions which are not available onthe CPU model as a noop and issue a log message at translation time.
On the real hardware CPU unknown opcodes results in undefined behaviour....
target-lm32: move model features to LM32CPU
This allows us to completely remove CPULM32State from DisasContext.Instead, copy the fields we need to DisasContext.
Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Michael Walle <michael@walle.cc>
lm32_sys: increase test case name length limit
The new MMU tests use longer names.
tests: lm32: new rule for single test cases
Introduce new target "check_%" to run individual test caes, eg. make check_mmu
milkymist-uart: use qemu_chr_fe_write_all() instead of qemu_chr_fe_write()
qemu_chr_fe_write() is capable of returning 0to indicate EAGAIN (and friends) and we don'thandle this.
Just change it to qemu_chr_fe_write_all() to fix.
Reported-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
Merge remote-tracking branch 'remotes/mcayland/qemu-openbios' into staging
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Don't abort on memory allocation error
It is better to fail migration in case of failure toallocate new cache item
Signed-off-by: Orit Wasserman <owasserm@redhat.com>Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>Signed-off-by: Juan Quintela <quintela@redhat.com>
Don't abort on out of memory when creating page cache
XBZRLE cache size should not be larger than guest memory size
Add check for cache size smaller than page size
Signed-off-by: Orit Wasserman <owasserm@redhat.com>Reviewed-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Juan Quintela <quintela@redhat.com>
migration:fix free XBZRLE decoded_buf wrong
When qemu do live migration with xbzrle, qemu malloc decoded_bufat destination end but free it at source end. It will crash qemuby double free error in some scenarios. Splitting the XBZRLE structurefor clear logic distinguishing src/dst side....
Set xbzrle buffers to NULL after freeing them to avoid double free errors
Signed-off-by: Orit Wasserman <owasserm@redhat.com>Reviewed-by: Juan Quintela <quintela@redhat.com>Reviewed-by: Eric Blake <eblake@redhat.com>Signed-off-by: Juan Quintela <quintela@redhat.com>
exec: fix ram_list dirty map optimization
The ae2810c4bb3b383176e8e1b33931b16c01483aab patch introducedoptimization for ram_list.dirty_memory update. However it can onlywork correctly if hpratio is 1 as the @bitmap parameter stores 1 bitsper system page size (may vary, 4K or 64K on PPC64) and...
vmstate: Make VMSTATE_STRUCT_POINTER take type, not ptr-to-type
The VMSTATE_STRUCT_POINTER macros are a bit odd in that theymust be passed an argument "FooType *" rather than just takingthe FooType. They're only used in one place, so it's easy totidy this up. This also lets us use the macro to replace the...
KVM: fix coexistence of KVM and Hyper-V leaves
kvm_arch_init_vcpu's initialization of the KVM leaves at 0x40000100is broken, because KVM_CPUID_FEATURES is left at 0x40000001. Moveit to 0x40000101 if Hyper-V is enabled.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
kvm: make availability of Hyper-V enlightenments dependent on KVM_CAP_HYPERV
The MS docs specify HV_X64_MSR_HYPERCALL as a mandatory interface,thus we must provide the MSRs even if the user only specifiedfeatures that, like relaxed timing, in principle don't require them....
kvm: make hyperv hypercall and guest os id MSRs migratable.
Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com>Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
kvm: make hyperv vapic assist page migratable
kvm: add support for hyper-v timers
http://msdn.microsoft.com/en-us/library/windows/hardware/ff541625%28v=vs.85%29.aspx
This code is generic for activating reference time counter or virtual reference time stamp counter
Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com>...
target-i386: Eliminate CONFIG_KVM #ifdefs
The compiler is already able to eliminate the kvm_arch_get_supported_cpuid()calls in kvm_cpu_fill_host() and filter_features_for_kvm(), so we caneliminate the CONFIG_KVM #ifdefs there.
Also, kvm_cpu_fill_host() and host_cpuid() don't need to check...
target-i386: Don't change x86_def_t struct on cpu_x86_register()
As eventually the x86_def_t data is going to be provided by the CPUclass, it's better to not touch it, and handle the special cases on theX86CPU object itself.
Current behavior of the code should stay exactly the same....
target-i386: Move KVM default-vendor hack to instance_init
As we will not have a cpu_x86_find_by_name() function anymore,move the KVM default-vendor hack to instance_init.
Unfortunately we can't move that code to class_init because it dependson KVM being initialized....
target-i386: kvm_cpu_fill_host(): Kill unused code
Those host_cpuid() calls are useless. They are leftovers from when theold code using host_cpuid() was removed.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target-i386: kvm_cpu_fill_host(): No need to check level
There's no need to check level (CPUID0.EAX) before callingkvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX), because:
target-i386: kvm_cpu_fill_host(): No need to check CPU vendor
There's no need to check CPU vendor before callingkvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX), because:
target-i386: kvm_cpu_fill_host(): No need to check xlevel2
There's no need to check CPU xlevel2 before callingkvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX), because:
target-i386: kvm_cpu_fill_host(): Set all feature words at end of function
Reorder the code so all the code that sets x86_cpu_def->features is atthe end of the function.
target-i386: kvm_cpu_fill_host(): Fill feature words in a loop
Now that the kvm_cpu_fill_host() code is simplified, we can simply setthe feature word array using a simple loop.
target-i386: kvm_check_features_against_host(): Kill feature word array
We don't need the ft[] array on kvm_check_features_against_host()anymore, as we can simply use the feature_word_info[] array, that haseverything we need.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>...
kvm: print suberror on all internal errors
KVM introduced internal error exit reason and suberror at the same time,and later extended it with internal error data.QEMU does not report suberror on hosts between these two events becausewe check for the extension. (half a year in 2009, but it is misleading)...
qtest: unlink QEMU pid file after startup
After starting the QEMU process and initializing the QMP connection, wecan read the pid file and unlink it.
Just stash away the pid instead of the pid filename. This way we canavoid pid file leaks since running tests may abort(3) without cleanup....
qtest: unlink UNIX domain sockets after connecting
UNIX domain sockets are leaked when tests call abort(3) (indirectly viaglib assert functions).
Unlink the files immediately after the connection has been establishedto avoid leaks.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Update seabios binaries to 1.7.4
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
roms: remove explicit MAKEFLAGS from recursive make invocations
When using $(MAKE) within a makefile, we shouldn't be explicitlyincluding $(MAKEFLAGS) on the command-line. It causes problemswhen that makefile is recursively invoked. When the roms/Makefile...
Update seabios submodule to 1.7.4
Not that many changes as we already have a git snapshot pretty closeto final 1.7.4 in the tree. Most notably change is the vgabios changewhich fixes the windows guest regression.
Full git shortlog:
Gerd Hoffmann (2):...
cris: Remove the CRIS PIC glue
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
linux-user: Fix trampoline code for CRIS
__put_user can write bytes, words (2 bytes) or longwords (4 bytes).Here obviously words should have been written, but bytes were written,so values like 0x9c5f were truncated to 0x5f.
Fix this by changing retcode from uint8_t to to uint16_t in...
axis-dev88: Connect the PIC upstream IRQs directly to the CPU