Revision 5d45de97

b/target-microblaze/translate.c
1317 1317
    /* Memory barrier.  */
1318 1318
    mbar = (dc->ir >> 16) & 31;
1319 1319
    if (mbar == 2 && dc->imm == 4) {
1320
        /* mbar IMM & 16 decodes to sleep.  */
1321
        if (dc->rd & 16) {
1322
            TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
1323
            TCGv_i32 tmp_1 = tcg_const_i32(1);
1324

  
1325
            LOG_DIS("sleep\n");
1326

  
1327
            t_sync_flags(dc);
1328
            tcg_gen_st_i32(tmp_1, cpu_env,
1329
                           -offsetof(MicroBlazeCPU, env)
1330
                           +offsetof(CPUState, halted));
1331
            tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
1332
            gen_helper_raise_exception(cpu_env, tmp_hlt);
1333
            tcg_temp_free_i32(tmp_hlt);
1334
            tcg_temp_free_i32(tmp_1);
1335
            return;
1336
        }
1320 1337
        LOG_DIS("mbar %d\n", dc->rd);
1321 1338
        /* Break the TB.  */
1322 1339
        dc->cpustate_changed = 1;

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