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1 | 81fdc5f8 | ths | /*
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2 | 81fdc5f8 | ths | * CRIS helper routines.
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3 | 81fdc5f8 | ths | *
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4 | 81fdc5f8 | ths | * Copyright (c) 2007 AXIS Communications AB
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5 | 81fdc5f8 | ths | * Written by Edgar E. Iglesias.
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6 | 81fdc5f8 | ths | *
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7 | 81fdc5f8 | ths | * This library is free software; you can redistribute it and/or
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8 | 81fdc5f8 | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 81fdc5f8 | ths | * License as published by the Free Software Foundation; either
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10 | 81fdc5f8 | ths | * version 2 of the License, or (at your option) any later version.
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11 | 81fdc5f8 | ths | *
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12 | 81fdc5f8 | ths | * This library is distributed in the hope that it will be useful,
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13 | 81fdc5f8 | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 81fdc5f8 | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 81fdc5f8 | ths | * Lesser General Public License for more details.
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16 | 81fdc5f8 | ths | *
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17 | 81fdc5f8 | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 81fdc5f8 | ths | * License along with this library; if not, write to the Free Software
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19 | 81fdc5f8 | ths | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 81fdc5f8 | ths | */
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21 | 81fdc5f8 | ths | |
22 | 81fdc5f8 | ths | #include <stdio.h> |
23 | 81fdc5f8 | ths | #include <string.h> |
24 | 81fdc5f8 | ths | |
25 | 81fdc5f8 | ths | #include "config.h" |
26 | 81fdc5f8 | ths | #include "cpu.h" |
27 | 81fdc5f8 | ths | #include "mmu.h" |
28 | 81fdc5f8 | ths | #include "exec-all.h" |
29 | 941db528 | ths | #include "host-utils.h" |
30 | 81fdc5f8 | ths | |
31 | e62b5b13 | edgar_igl | #define D(x)
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32 | e62b5b13 | edgar_igl | |
33 | 81fdc5f8 | ths | #if defined(CONFIG_USER_ONLY)
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34 | 81fdc5f8 | ths | |
35 | 81fdc5f8 | ths | void do_interrupt (CPUState *env)
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36 | 81fdc5f8 | ths | { |
37 | bbaf29c7 | edgar_igl | env->exception_index = -1;
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38 | bbaf29c7 | edgar_igl | env->pregs[PR_ERP] = env->pc; |
39 | 81fdc5f8 | ths | } |
40 | 81fdc5f8 | ths | |
41 | 81fdc5f8 | ths | int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
42 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
43 | 81fdc5f8 | ths | { |
44 | bbaf29c7 | edgar_igl | env->exception_index = 0xaa;
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45 | 30abcfc7 | edgar_igl | env->pregs[PR_EDA] = address; |
46 | bbaf29c7 | edgar_igl | cpu_dump_state(env, stderr, fprintf, 0);
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47 | bbaf29c7 | edgar_igl | return 1; |
48 | 81fdc5f8 | ths | } |
49 | 81fdc5f8 | ths | |
50 | 81fdc5f8 | ths | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
51 | 81fdc5f8 | ths | { |
52 | bbaf29c7 | edgar_igl | return addr;
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53 | 81fdc5f8 | ths | } |
54 | 81fdc5f8 | ths | |
55 | 81fdc5f8 | ths | #else /* !CONFIG_USER_ONLY */ |
56 | 81fdc5f8 | ths | |
57 | e62b5b13 | edgar_igl | |
58 | e62b5b13 | edgar_igl | static void cris_shift_ccs(CPUState *env) |
59 | e62b5b13 | edgar_igl | { |
60 | e62b5b13 | edgar_igl | uint32_t ccs; |
61 | e62b5b13 | edgar_igl | /* Apply the ccs shift. */
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62 | e62b5b13 | edgar_igl | ccs = env->pregs[PR_CCS]; |
63 | b41f7df0 | edgar_igl | ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff; |
64 | e62b5b13 | edgar_igl | env->pregs[PR_CCS] = ccs; |
65 | e62b5b13 | edgar_igl | } |
66 | e62b5b13 | edgar_igl | |
67 | 81fdc5f8 | ths | int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
68 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
69 | 81fdc5f8 | ths | { |
70 | 81fdc5f8 | ths | struct cris_mmu_result_t res;
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71 | 81fdc5f8 | ths | int prot, miss;
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72 | e62b5b13 | edgar_igl | int r = -1; |
73 | 81fdc5f8 | ths | target_ulong phy; |
74 | 81fdc5f8 | ths | |
75 | b41f7df0 | edgar_igl | D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
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76 | 81fdc5f8 | ths | address &= TARGET_PAGE_MASK; |
77 | 81fdc5f8 | ths | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
78 | 6ebbf390 | j_mayer | miss = cris_mmu_translate(&res, env, address, rw, mmu_idx); |
79 | 81fdc5f8 | ths | if (miss)
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80 | 81fdc5f8 | ths | { |
81 | ef29a70d | edgar_igl | if (env->exception_index == EXCP_MMU_FAULT)
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82 | ef29a70d | edgar_igl | cpu_abort(env, |
83 | ef29a70d | edgar_igl | "CRIS: Illegal recursive bus fault."
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84 | ef29a70d | edgar_igl | "addr=%x rw=%d\n",
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85 | ef29a70d | edgar_igl | address, rw); |
86 | ef29a70d | edgar_igl | |
87 | e62b5b13 | edgar_igl | env->exception_index = EXCP_MMU_FAULT; |
88 | e62b5b13 | edgar_igl | env->fault_vector = res.bf_vec; |
89 | e62b5b13 | edgar_igl | r = 1;
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90 | 81fdc5f8 | ths | } |
91 | 81fdc5f8 | ths | else
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92 | 81fdc5f8 | ths | { |
93 | 81fdc5f8 | ths | phy = res.phy; |
94 | b41f7df0 | edgar_igl | prot = res.prot; |
95 | b41f7df0 | edgar_igl | address &= TARGET_PAGE_MASK; |
96 | e62b5b13 | edgar_igl | r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu); |
97 | 81fdc5f8 | ths | } |
98 | b41f7df0 | edgar_igl | if (r > 0) |
99 | cf1d97f0 | edgar_igl | D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x"
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100 | cf1d97f0 | edgar_igl | " phy=%x ismmu=%d vec=%x pc=%x\n",
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101 | cf1d97f0 | edgar_igl | __func__, r, env->interrupt_request, |
102 | cf1d97f0 | edgar_igl | address, res.phy, is_softmmu, res.bf_vec, env->pc)); |
103 | e62b5b13 | edgar_igl | return r;
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104 | 81fdc5f8 | ths | } |
105 | 81fdc5f8 | ths | |
106 | 81fdc5f8 | ths | void do_interrupt(CPUState *env)
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107 | 81fdc5f8 | ths | { |
108 | e62b5b13 | edgar_igl | int ex_vec = -1; |
109 | 81fdc5f8 | ths | |
110 | ef29a70d | edgar_igl | D(fprintf (logfile, "exception index=%d interrupt_req=%d\n",
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111 | b41f7df0 | edgar_igl | env->exception_index, |
112 | b41f7df0 | edgar_igl | env->interrupt_request)); |
113 | 81fdc5f8 | ths | |
114 | 81fdc5f8 | ths | switch (env->exception_index)
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115 | 81fdc5f8 | ths | { |
116 | 81fdc5f8 | ths | case EXCP_BREAK:
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117 | e62b5b13 | edgar_igl | /* These exceptions are genereated by the core itself.
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118 | e62b5b13 | edgar_igl | ERP should point to the insn following the brk. */
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119 | e62b5b13 | edgar_igl | ex_vec = env->trap_vector; |
120 | 9004627f | edgar_igl | env->pregs[PR_ERP] = env->pc + 2;
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121 | 81fdc5f8 | ths | break;
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122 | e62b5b13 | edgar_igl | |
123 | e62b5b13 | edgar_igl | case EXCP_MMU_FAULT:
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124 | e62b5b13 | edgar_igl | ex_vec = env->fault_vector; |
125 | b41f7df0 | edgar_igl | env->pregs[PR_ERP] = env->pc; |
126 | 81fdc5f8 | ths | break;
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127 | 81fdc5f8 | ths | |
128 | 81fdc5f8 | ths | default:
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129 | b41f7df0 | edgar_igl | /* Is the core accepting interrupts? */
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130 | b41f7df0 | edgar_igl | if (!(env->pregs[PR_CCS] & I_FLAG))
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131 | b41f7df0 | edgar_igl | return;
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132 | b41f7df0 | edgar_igl | /* The interrupt controller gives us the
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133 | b41f7df0 | edgar_igl | vector. */
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134 | b41f7df0 | edgar_igl | ex_vec = env->interrupt_vector; |
135 | b41f7df0 | edgar_igl | /* Normal interrupts are taken between
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136 | b41f7df0 | edgar_igl | TB's. env->pc is valid here. */
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137 | b41f7df0 | edgar_igl | env->pregs[PR_ERP] = env->pc; |
138 | b41f7df0 | edgar_igl | break;
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139 | b41f7df0 | edgar_igl | } |
140 | b41f7df0 | edgar_igl | |
141 | cf1d97f0 | edgar_igl | if (env->dslot) {
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142 | cf1d97f0 | edgar_igl | D(fprintf(logfile, "excp isr=%x PC=%x ds=%d SP=%x"
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143 | cf1d97f0 | edgar_igl | " ERP=%x pid=%x ccs=%x cc=%d %x\n",
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144 | cf1d97f0 | edgar_igl | ex_vec, env->pc, env->dslot, |
145 | ef29a70d | edgar_igl | env->regs[R_SP], |
146 | b41f7df0 | edgar_igl | env->pregs[PR_ERP], env->pregs[PR_PID], |
147 | b41f7df0 | edgar_igl | env->pregs[PR_CCS], |
148 | b41f7df0 | edgar_igl | env->cc_op, env->cc_mask)); |
149 | cf1d97f0 | edgar_igl | /* We loose the btarget, btaken state here so rexec the
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150 | cf1d97f0 | edgar_igl | branch. */
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151 | cf1d97f0 | edgar_igl | env->pregs[PR_ERP] -= env->dslot; |
152 | cf1d97f0 | edgar_igl | /* Exception starts with dslot cleared. */
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153 | cf1d97f0 | edgar_igl | env->dslot = 0;
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154 | 81fdc5f8 | ths | } |
155 | b41f7df0 | edgar_igl | |
156 | e62b5b13 | edgar_igl | env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
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157 | b41f7df0 | edgar_igl | |
158 | b41f7df0 | edgar_igl | if (env->pregs[PR_CCS] & U_FLAG) {
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159 | b41f7df0 | edgar_igl | /* Swap stack pointers. */
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160 | b41f7df0 | edgar_igl | env->pregs[PR_USP] = env->regs[R_SP]; |
161 | b41f7df0 | edgar_igl | env->regs[R_SP] = env->ksp; |
162 | b41f7df0 | edgar_igl | } |
163 | b41f7df0 | edgar_igl | |
164 | b41f7df0 | edgar_igl | /* Apply the CRIS CCS shift. Clears U if set. */
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165 | e62b5b13 | edgar_igl | cris_shift_ccs(env); |
166 | b41f7df0 | edgar_igl | D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
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167 | b41f7df0 | edgar_igl | __func__, env->pc, ex_vec, |
168 | b41f7df0 | edgar_igl | env->pregs[PR_CCS], |
169 | b41f7df0 | edgar_igl | env->pregs[PR_PID], |
170 | b41f7df0 | edgar_igl | env->pregs[PR_ERP])); |
171 | 81fdc5f8 | ths | } |
172 | 81fdc5f8 | ths | |
173 | 81fdc5f8 | ths | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
174 | 81fdc5f8 | ths | { |
175 | 81fdc5f8 | ths | uint32_t phy = addr; |
176 | 81fdc5f8 | ths | struct cris_mmu_result_t res;
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177 | 81fdc5f8 | ths | int miss;
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178 | 81fdc5f8 | ths | miss = cris_mmu_translate(&res, env, addr, 0, 0); |
179 | 81fdc5f8 | ths | if (!miss)
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180 | 81fdc5f8 | ths | phy = res.phy; |
181 | e62b5b13 | edgar_igl | D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
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182 | 81fdc5f8 | ths | return phy;
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183 | 81fdc5f8 | ths | } |
184 | 81fdc5f8 | ths | #endif |