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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%eax",
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    "%ecx",
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    "%edx",
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    "%ebx",
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    "%esp",
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    "%ebp",
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    "%esi",
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    "%edi",
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};
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int tcg_target_reg_alloc_order[] = {
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    TCG_REG_EAX,
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    TCG_REG_EDX,
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    TCG_REG_ECX,
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    TCG_REG_EBX,
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    TCG_REG_ESI,
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    TCG_REG_EDI,
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    TCG_REG_EBP,
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};
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const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
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const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
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static uint8_t *tb_ret_addr;
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static void patch_reloc(uint8_t *code_ptr, int type, 
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                        tcg_target_long value, tcg_target_long addend)
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{
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    value += addend;
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    switch(type) {
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    case R_386_32:
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        *(uint32_t *)code_ptr = value;
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        break;
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    case R_386_PC32:
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        *(uint32_t *)code_ptr = value - (long)code_ptr;
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        break;
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    default:
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        tcg_abort();
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    }
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}
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags)
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{
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    flags &= TCG_CALL_TYPE_MASK;
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    switch(flags) {
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    case TCG_CALL_TYPE_STD:
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        return 0;
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    case TCG_CALL_TYPE_REGPARM_1:
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    case TCG_CALL_TYPE_REGPARM_2:
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    case TCG_CALL_TYPE_REGPARM:
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        return flags - TCG_CALL_TYPE_REGPARM_1 + 1;
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    default:
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        tcg_abort();
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    }
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}
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/* parse target specific constraints */
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int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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    const char *ct_str;
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    ct_str = *pct_str;
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    switch(ct_str[0]) {
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    case 'a':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
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        break;
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    case 'b':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
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        break;
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    case 'c':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
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        break;
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    case 'd':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
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        break;
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    case 'S':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
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        break;
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    case 'D':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
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        break;
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    case 'q':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xf);
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        break;
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    case 'r':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xff);
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        break;
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        /* qemu_ld/st address constraint */
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    case 'L':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xff);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
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        break;
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    default:
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        return -1;
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    }
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    ct_str++;
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    *pct_str = ct_str;
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    return 0;
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}
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val,
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                                         const TCGArgConstraint *arg_ct)
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{
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    int ct;
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    ct = arg_ct->ct;
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    if (ct & TCG_CT_CONST)
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        return 1;
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    else
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        return 0;
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}
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#define ARITH_ADD 0
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#define ARITH_OR  1
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#define ARITH_ADC 2
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#define ARITH_SBB 3
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#define ARITH_AND 4
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#define ARITH_SUB 5
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#define ARITH_XOR 6
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#define ARITH_CMP 7
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#define SHIFT_SHL 4
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#define SHIFT_SHR 5
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#define SHIFT_SAR 7
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#define JCC_JMP (-1)
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#define JCC_JO  0x0
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#define JCC_JNO 0x1
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#define JCC_JB  0x2
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#define JCC_JAE 0x3
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#define JCC_JE  0x4
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#define JCC_JNE 0x5
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#define JCC_JBE 0x6
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#define JCC_JA  0x7
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#define JCC_JS  0x8
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#define JCC_JNS 0x9
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#define JCC_JP  0xa
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#define JCC_JNP 0xb
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#define JCC_JL  0xc
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#define JCC_JGE 0xd
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#define JCC_JLE 0xe
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#define JCC_JG  0xf
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#define P_EXT   0x100 /* 0x0f opcode prefix */
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static const uint8_t tcg_cond_to_jcc[10] = {
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    [TCG_COND_EQ] = JCC_JE,
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    [TCG_COND_NE] = JCC_JNE,
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    [TCG_COND_LT] = JCC_JL,
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    [TCG_COND_GE] = JCC_JGE,
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    [TCG_COND_LE] = JCC_JLE,
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    [TCG_COND_GT] = JCC_JG,
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    [TCG_COND_LTU] = JCC_JB,
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    [TCG_COND_GEU] = JCC_JAE,
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    [TCG_COND_LEU] = JCC_JBE,
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    [TCG_COND_GTU] = JCC_JA,
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};
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static inline void tcg_out_opc(TCGContext *s, int opc)
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{
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    if (opc & P_EXT)
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        tcg_out8(s, 0x0f);
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    tcg_out8(s, opc);
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}
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static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
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{
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    tcg_out_opc(s, opc);
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    tcg_out8(s, 0xc0 | (r << 3) | rm);
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}
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/* rm == -1 means no register index */
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static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, 
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                                        int32_t offset)
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{
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    tcg_out_opc(s, opc);
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    if (rm == -1) {
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        tcg_out8(s, 0x05 | (r << 3));
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        tcg_out32(s, offset);
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    } else if (offset == 0 && rm != TCG_REG_EBP) {
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        if (rm == TCG_REG_ESP) {
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            tcg_out8(s, 0x04 | (r << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x00 | (r << 3) | rm);
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        }
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    } else if ((int8_t)offset == offset) {
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        if (rm == TCG_REG_ESP) {
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            tcg_out8(s, 0x44 | (r << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x40 | (r << 3) | rm);
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        }
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        tcg_out8(s, offset);
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    } else {
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        if (rm == TCG_REG_ESP) {
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            tcg_out8(s, 0x84 | (r << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x80 | (r << 3) | rm);
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        }
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        tcg_out32(s, offset);
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    }
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}
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static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
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{
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    if (arg != ret)
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        tcg_out_modrm(s, 0x8b, ret, arg);
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}
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static inline void tcg_out_movi(TCGContext *s, TCGType type,
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                                int ret, int32_t arg)
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{
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    if (arg == 0) {
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        /* xor r0,r0 */
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        tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret);
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    } else {
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        tcg_out8(s, 0xb8 + ret);
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        tcg_out32(s, arg);
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    }
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}
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static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
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                              int arg1, tcg_target_long arg2)
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{
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    /* movl */
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    tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
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}
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static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
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                              int arg1, tcg_target_long arg2)
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{
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    /* movl */
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    tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
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}
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static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
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{
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    if (val == (int8_t)val) {
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        tcg_out_modrm(s, 0x83, c, r0);
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        tcg_out8(s, val);
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    } else {
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        tcg_out_modrm(s, 0x81, c, r0);
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        tcg_out32(s, val);
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    }
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}
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void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
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{
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    if (val != 0)
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        tgen_arithi(s, ARITH_ADD, reg, val);
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}
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static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
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{
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    int32_t val, val1;
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    TCGLabel *l = &s->labels[label_index];
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    if (l->has_value) {
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        val = l->u.value - (tcg_target_long)s->code_ptr;
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        val1 = val - 2;
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        if ((int8_t)val1 == val1) {
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            if (opc == -1)
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                tcg_out8(s, 0xeb);
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            else
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                tcg_out8(s, 0x70 + opc);
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            tcg_out8(s, val1);
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        } else {
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            if (opc == -1) {
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                tcg_out8(s, 0xe9);
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                tcg_out32(s, val - 5);
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            } else {
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                tcg_out8(s, 0x0f);
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                tcg_out8(s, 0x80 + opc);
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                tcg_out32(s, val - 6);
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            }
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        }
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    } else {
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        if (opc == -1) {
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            tcg_out8(s, 0xe9);
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        } else {
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            tcg_out8(s, 0x0f);
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            tcg_out8(s, 0x80 + opc);
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        }
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        tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
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        s->code_ptr += 4;
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    }
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}
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static void tcg_out_brcond(TCGContext *s, int cond, 
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                           TCGArg arg1, TCGArg arg2, int const_arg2,
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                           int label_index)
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{
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    if (const_arg2) {
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        if (arg2 == 0) {
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            /* test r, r */
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            tcg_out_modrm(s, 0x85, arg1, arg1);
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        } else {
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            tgen_arithi(s, ARITH_CMP, arg1, arg2);
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        }
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    } else {
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        tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3), arg2, arg1);
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    }
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    tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
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}
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/* XXX: we implement it at the target level to avoid having to
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   handle cross basic blocks temporaries */
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static void tcg_out_brcond2(TCGContext *s,
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                            const TCGArg *args, const int *const_args)
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{
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    int label_next;
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    label_next = gen_new_label();
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    switch(args[4]) {
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    case TCG_COND_EQ:
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        tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
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        tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
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        break;
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    case TCG_COND_NE:
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        tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
358 bb210e78 bellard
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
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        break;
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    case TCG_COND_LT:
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        tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
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        tcg_out_jxx(s, JCC_JNE, label_next);
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        tcg_out_brcond(s, TCG_COND_LT, args[0], args[2], const_args[2], args[5]);
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        break;
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    case TCG_COND_LE:
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        tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
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        tcg_out_jxx(s, JCC_JNE, label_next);
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        tcg_out_brcond(s, TCG_COND_LE, args[0], args[2], const_args[2], args[5]);
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        break;
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    case TCG_COND_GT:
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        tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
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        tcg_out_jxx(s, JCC_JNE, label_next);
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        tcg_out_brcond(s, TCG_COND_GT, args[0], args[2], const_args[2], args[5]);
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        break;
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    case TCG_COND_GE:
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        tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
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        tcg_out_jxx(s, JCC_JNE, label_next);
378 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GE, args[0], args[2], const_args[2], args[5]);
379 c896fe29 bellard
        break;
380 c896fe29 bellard
    case TCG_COND_LTU:
381 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
382 affa3264 bellard
        tcg_out_jxx(s, JCC_JNE, label_next);
383 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
384 c896fe29 bellard
        break;
385 c896fe29 bellard
    case TCG_COND_LEU:
386 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
387 affa3264 bellard
        tcg_out_jxx(s, JCC_JNE, label_next);
388 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
389 c896fe29 bellard
        break;
390 c896fe29 bellard
    case TCG_COND_GTU:
391 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
392 affa3264 bellard
        tcg_out_jxx(s, JCC_JNE, label_next);
393 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
394 c896fe29 bellard
        break;
395 c896fe29 bellard
    case TCG_COND_GEU:
396 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
397 affa3264 bellard
        tcg_out_jxx(s, JCC_JNE, label_next);
398 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
399 c896fe29 bellard
        break;
400 c896fe29 bellard
    default:
401 c896fe29 bellard
        tcg_abort();
402 c896fe29 bellard
    }
403 c896fe29 bellard
    tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
404 c896fe29 bellard
}
405 c896fe29 bellard
406 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
407 c896fe29 bellard
extern void __ldb_mmu(void);
408 c896fe29 bellard
extern void __ldw_mmu(void);
409 c896fe29 bellard
extern void __ldl_mmu(void);
410 c896fe29 bellard
extern void __ldq_mmu(void);
411 c896fe29 bellard
412 c896fe29 bellard
extern void __stb_mmu(void);
413 c896fe29 bellard
extern void __stw_mmu(void);
414 c896fe29 bellard
extern void __stl_mmu(void);
415 c896fe29 bellard
extern void __stq_mmu(void);
416 c896fe29 bellard
417 c896fe29 bellard
static void *qemu_ld_helpers[4] = {
418 c896fe29 bellard
    __ldb_mmu,
419 c896fe29 bellard
    __ldw_mmu,
420 c896fe29 bellard
    __ldl_mmu,
421 c896fe29 bellard
    __ldq_mmu,
422 c896fe29 bellard
};
423 c896fe29 bellard
424 c896fe29 bellard
static void *qemu_st_helpers[4] = {
425 c896fe29 bellard
    __stb_mmu,
426 c896fe29 bellard
    __stw_mmu,
427 c896fe29 bellard
    __stl_mmu,
428 c896fe29 bellard
    __stq_mmu,
429 c896fe29 bellard
};
430 c896fe29 bellard
#endif
431 c896fe29 bellard
432 c896fe29 bellard
/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
433 c896fe29 bellard
   EAX. It will be useful once fixed registers globals are less
434 c896fe29 bellard
   common. */
435 c896fe29 bellard
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
436 c896fe29 bellard
                            int opc)
437 c896fe29 bellard
{
438 c896fe29 bellard
    int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
439 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
440 c896fe29 bellard
    uint8_t *label1_ptr, *label2_ptr;
441 c896fe29 bellard
#endif
442 c896fe29 bellard
#if TARGET_LONG_BITS == 64
443 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
444 c896fe29 bellard
    uint8_t *label3_ptr;
445 c896fe29 bellard
#endif
446 c896fe29 bellard
    int addr_reg2;
447 c896fe29 bellard
#endif
448 c896fe29 bellard
449 c896fe29 bellard
    data_reg = *args++;
450 c896fe29 bellard
    if (opc == 3)
451 c896fe29 bellard
        data_reg2 = *args++;
452 c896fe29 bellard
    else
453 c896fe29 bellard
        data_reg2 = 0;
454 c896fe29 bellard
    addr_reg = *args++;
455 c896fe29 bellard
#if TARGET_LONG_BITS == 64
456 c896fe29 bellard
    addr_reg2 = *args++;
457 c896fe29 bellard
#endif
458 c896fe29 bellard
    mem_index = *args;
459 c896fe29 bellard
    s_bits = opc & 3;
460 c896fe29 bellard
461 c896fe29 bellard
    r0 = TCG_REG_EAX;
462 c896fe29 bellard
    r1 = TCG_REG_EDX;
463 c896fe29 bellard
464 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
465 c896fe29 bellard
    tcg_out_mov(s, r1, addr_reg); 
466 c896fe29 bellard
467 c896fe29 bellard
    tcg_out_mov(s, r0, addr_reg); 
468 c896fe29 bellard
 
469 c896fe29 bellard
    tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
470 c896fe29 bellard
    tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 
471 c896fe29 bellard
    
472 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
473 c896fe29 bellard
    tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
474 c896fe29 bellard
    
475 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
476 c896fe29 bellard
    tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
477 c896fe29 bellard
478 c896fe29 bellard
    tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
479 c896fe29 bellard
    tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
480 c896fe29 bellard
    tcg_out8(s, (5 << 3) | r1);
481 c896fe29 bellard
    tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
482 c896fe29 bellard
483 c896fe29 bellard
    /* cmp 0(r1), r0 */
484 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
485 c896fe29 bellard
    
486 c896fe29 bellard
    tcg_out_mov(s, r0, addr_reg);
487 c896fe29 bellard
    
488 c896fe29 bellard
#if TARGET_LONG_BITS == 32
489 c896fe29 bellard
    /* je label1 */
490 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
491 c896fe29 bellard
    label1_ptr = s->code_ptr;
492 c896fe29 bellard
    s->code_ptr++;
493 c896fe29 bellard
#else
494 c896fe29 bellard
    /* jne label3 */
495 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JNE);
496 c896fe29 bellard
    label3_ptr = s->code_ptr;
497 c896fe29 bellard
    s->code_ptr++;
498 c896fe29 bellard
    
499 c896fe29 bellard
    /* cmp 4(r1), addr_reg2 */
500 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
501 c896fe29 bellard
502 c896fe29 bellard
    /* je label1 */
503 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
504 c896fe29 bellard
    label1_ptr = s->code_ptr;
505 c896fe29 bellard
    s->code_ptr++;
506 c896fe29 bellard
    
507 c896fe29 bellard
    /* label3: */
508 c896fe29 bellard
    *label3_ptr = s->code_ptr - label3_ptr - 1;
509 c896fe29 bellard
#endif
510 c896fe29 bellard
511 c896fe29 bellard
    /* XXX: move that code at the end of the TB */
512 c896fe29 bellard
#if TARGET_LONG_BITS == 32
513 c896fe29 bellard
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index);
514 c896fe29 bellard
#else
515 c896fe29 bellard
    tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
516 c896fe29 bellard
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
517 c896fe29 bellard
#endif
518 c896fe29 bellard
    tcg_out8(s, 0xe8);
519 c896fe29 bellard
    tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] - 
520 c896fe29 bellard
              (tcg_target_long)s->code_ptr - 4);
521 c896fe29 bellard
522 c896fe29 bellard
    switch(opc) {
523 c896fe29 bellard
    case 0 | 4:
524 c896fe29 bellard
        /* movsbl */
525 c896fe29 bellard
        tcg_out_modrm(s, 0xbe | P_EXT, data_reg, TCG_REG_EAX);
526 c896fe29 bellard
        break;
527 c896fe29 bellard
    case 1 | 4:
528 c896fe29 bellard
        /* movswl */
529 c896fe29 bellard
        tcg_out_modrm(s, 0xbf | P_EXT, data_reg, TCG_REG_EAX);
530 c896fe29 bellard
        break;
531 c896fe29 bellard
    case 0:
532 c896fe29 bellard
    case 1:
533 c896fe29 bellard
    case 2:
534 c896fe29 bellard
    default:
535 c896fe29 bellard
        tcg_out_mov(s, data_reg, TCG_REG_EAX);
536 c896fe29 bellard
        break;
537 c896fe29 bellard
    case 3:
538 c896fe29 bellard
        if (data_reg == TCG_REG_EDX) {
539 c896fe29 bellard
            tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */
540 c896fe29 bellard
            tcg_out_mov(s, data_reg2, TCG_REG_EAX);
541 c896fe29 bellard
        } else {
542 c896fe29 bellard
            tcg_out_mov(s, data_reg, TCG_REG_EAX);
543 c896fe29 bellard
            tcg_out_mov(s, data_reg2, TCG_REG_EDX);
544 c896fe29 bellard
        }
545 c896fe29 bellard
        break;
546 c896fe29 bellard
    }
547 c896fe29 bellard
548 c896fe29 bellard
    /* jmp label2 */
549 c896fe29 bellard
    tcg_out8(s, 0xeb);
550 c896fe29 bellard
    label2_ptr = s->code_ptr;
551 c896fe29 bellard
    s->code_ptr++;
552 c896fe29 bellard
    
553 c896fe29 bellard
    /* label1: */
554 c896fe29 bellard
    *label1_ptr = s->code_ptr - label1_ptr - 1;
555 c896fe29 bellard
556 c896fe29 bellard
    /* add x(r1), r0 */
557 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) - 
558 c896fe29 bellard
                         offsetof(CPUTLBEntry, addr_read));
559 c896fe29 bellard
#else
560 c896fe29 bellard
    r0 = addr_reg;
561 c896fe29 bellard
#endif
562 c896fe29 bellard
563 c896fe29 bellard
#ifdef TARGET_WORDS_BIGENDIAN
564 c896fe29 bellard
    bswap = 1;
565 c896fe29 bellard
#else
566 c896fe29 bellard
    bswap = 0;
567 c896fe29 bellard
#endif
568 c896fe29 bellard
    switch(opc) {
569 c896fe29 bellard
    case 0:
570 c896fe29 bellard
        /* movzbl */
571 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
572 c896fe29 bellard
        break;
573 c896fe29 bellard
    case 0 | 4:
574 c896fe29 bellard
        /* movsbl */
575 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbe | P_EXT, data_reg, r0, 0);
576 c896fe29 bellard
        break;
577 c896fe29 bellard
    case 1:
578 c896fe29 bellard
        /* movzwl */
579 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
580 c896fe29 bellard
        if (bswap) {
581 c896fe29 bellard
            /* rolw $8, data_reg */
582 c896fe29 bellard
            tcg_out8(s, 0x66); 
583 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, data_reg);
584 c896fe29 bellard
            tcg_out8(s, 8);
585 c896fe29 bellard
        }
586 c896fe29 bellard
        break;
587 c896fe29 bellard
    case 1 | 4:
588 c896fe29 bellard
        /* movswl */
589 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbf | P_EXT, data_reg, r0, 0);
590 c896fe29 bellard
        if (bswap) {
591 c896fe29 bellard
            /* rolw $8, data_reg */
592 c896fe29 bellard
            tcg_out8(s, 0x66); 
593 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, data_reg);
594 c896fe29 bellard
            tcg_out8(s, 8);
595 c896fe29 bellard
596 c896fe29 bellard
            /* movswl data_reg, data_reg */
597 c896fe29 bellard
            tcg_out_modrm(s, 0xbf | P_EXT, data_reg, data_reg);
598 c896fe29 bellard
        }
599 c896fe29 bellard
        break;
600 c896fe29 bellard
    case 2:
601 c896fe29 bellard
        /* movl (r0), data_reg */
602 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
603 c896fe29 bellard
        if (bswap) {
604 c896fe29 bellard
            /* bswap */
605 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
606 c896fe29 bellard
        }
607 c896fe29 bellard
        break;
608 c896fe29 bellard
    case 3:
609 c896fe29 bellard
        /* XXX: could be nicer */
610 c896fe29 bellard
        if (r0 == data_reg) {
611 c896fe29 bellard
            r1 = TCG_REG_EDX;
612 c896fe29 bellard
            if (r1 == data_reg)
613 c896fe29 bellard
                r1 = TCG_REG_EAX;
614 c896fe29 bellard
            tcg_out_mov(s, r1, r0);
615 c896fe29 bellard
            r0 = r1;
616 c896fe29 bellard
        }
617 c896fe29 bellard
        if (!bswap) {
618 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
619 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 4);
620 c896fe29 bellard
        } else {
621 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 4);
622 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
623 c896fe29 bellard
624 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 0);
625 c896fe29 bellard
            /* bswap */
626 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + data_reg2) | P_EXT);
627 c896fe29 bellard
        }
628 c896fe29 bellard
        break;
629 c896fe29 bellard
    default:
630 c896fe29 bellard
        tcg_abort();
631 c896fe29 bellard
    }
632 c896fe29 bellard
633 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
634 c896fe29 bellard
    /* label2: */
635 c896fe29 bellard
    *label2_ptr = s->code_ptr - label2_ptr - 1;
636 c896fe29 bellard
#endif
637 c896fe29 bellard
}
638 c896fe29 bellard
639 c896fe29 bellard
640 c896fe29 bellard
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
641 c896fe29 bellard
                            int opc)
642 c896fe29 bellard
{
643 c896fe29 bellard
    int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
644 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
645 c896fe29 bellard
    uint8_t *label1_ptr, *label2_ptr;
646 c896fe29 bellard
#endif
647 c896fe29 bellard
#if TARGET_LONG_BITS == 64
648 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
649 c896fe29 bellard
    uint8_t *label3_ptr;
650 c896fe29 bellard
#endif
651 c896fe29 bellard
    int addr_reg2;
652 c896fe29 bellard
#endif
653 c896fe29 bellard
654 c896fe29 bellard
    data_reg = *args++;
655 c896fe29 bellard
    if (opc == 3)
656 c896fe29 bellard
        data_reg2 = *args++;
657 c896fe29 bellard
    else
658 c896fe29 bellard
        data_reg2 = 0;
659 c896fe29 bellard
    addr_reg = *args++;
660 c896fe29 bellard
#if TARGET_LONG_BITS == 64
661 c896fe29 bellard
    addr_reg2 = *args++;
662 c896fe29 bellard
#endif
663 c896fe29 bellard
    mem_index = *args;
664 c896fe29 bellard
665 c896fe29 bellard
    s_bits = opc;
666 c896fe29 bellard
667 c896fe29 bellard
    r0 = TCG_REG_EAX;
668 c896fe29 bellard
    r1 = TCG_REG_EDX;
669 c896fe29 bellard
670 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
671 c896fe29 bellard
    tcg_out_mov(s, r1, addr_reg); 
672 c896fe29 bellard
673 c896fe29 bellard
    tcg_out_mov(s, r0, addr_reg); 
674 c896fe29 bellard
 
675 c896fe29 bellard
    tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
676 c896fe29 bellard
    tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 
677 c896fe29 bellard
    
678 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
679 c896fe29 bellard
    tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
680 c896fe29 bellard
    
681 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
682 c896fe29 bellard
    tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
683 c896fe29 bellard
684 c896fe29 bellard
    tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
685 c896fe29 bellard
    tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
686 c896fe29 bellard
    tcg_out8(s, (5 << 3) | r1);
687 c896fe29 bellard
    tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
688 c896fe29 bellard
689 c896fe29 bellard
    /* cmp 0(r1), r0 */
690 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
691 c896fe29 bellard
    
692 c896fe29 bellard
    tcg_out_mov(s, r0, addr_reg);
693 c896fe29 bellard
    
694 c896fe29 bellard
#if TARGET_LONG_BITS == 32
695 c896fe29 bellard
    /* je label1 */
696 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
697 c896fe29 bellard
    label1_ptr = s->code_ptr;
698 c896fe29 bellard
    s->code_ptr++;
699 c896fe29 bellard
#else
700 c896fe29 bellard
    /* jne label3 */
701 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JNE);
702 c896fe29 bellard
    label3_ptr = s->code_ptr;
703 c896fe29 bellard
    s->code_ptr++;
704 c896fe29 bellard
    
705 c896fe29 bellard
    /* cmp 4(r1), addr_reg2 */
706 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
707 c896fe29 bellard
708 c896fe29 bellard
    /* je label1 */
709 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
710 c896fe29 bellard
    label1_ptr = s->code_ptr;
711 c896fe29 bellard
    s->code_ptr++;
712 c896fe29 bellard
    
713 c896fe29 bellard
    /* label3: */
714 c896fe29 bellard
    *label3_ptr = s->code_ptr - label3_ptr - 1;
715 c896fe29 bellard
#endif
716 c896fe29 bellard
717 c896fe29 bellard
    /* XXX: move that code at the end of the TB */
718 c896fe29 bellard
#if TARGET_LONG_BITS == 32
719 c896fe29 bellard
    if (opc == 3) {
720 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_EDX, data_reg);
721 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_ECX, data_reg2);
722 c896fe29 bellard
        tcg_out8(s, 0x6a); /* push Ib */
723 c896fe29 bellard
        tcg_out8(s, mem_index);
724 c896fe29 bellard
        tcg_out8(s, 0xe8);
725 c896fe29 bellard
        tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - 
726 c896fe29 bellard
                  (tcg_target_long)s->code_ptr - 4);
727 c896fe29 bellard
        tcg_out_addi(s, TCG_REG_ESP, 4);
728 c896fe29 bellard
    } else {
729 c896fe29 bellard
        switch(opc) {
730 c896fe29 bellard
        case 0:
731 c896fe29 bellard
            /* movzbl */
732 c896fe29 bellard
            tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_EDX, data_reg);
733 c896fe29 bellard
            break;
734 c896fe29 bellard
        case 1:
735 c896fe29 bellard
            /* movzwl */
736 c896fe29 bellard
            tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_EDX, data_reg);
737 c896fe29 bellard
            break;
738 c896fe29 bellard
        case 2:
739 c896fe29 bellard
            tcg_out_mov(s, TCG_REG_EDX, data_reg);
740 c896fe29 bellard
            break;
741 c896fe29 bellard
        }
742 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
743 c896fe29 bellard
        tcg_out8(s, 0xe8);
744 c896fe29 bellard
        tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - 
745 c896fe29 bellard
                  (tcg_target_long)s->code_ptr - 4);
746 c896fe29 bellard
    }
747 c896fe29 bellard
#else
748 c896fe29 bellard
    if (opc == 3) {
749 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
750 c896fe29 bellard
        tcg_out8(s, 0x6a); /* push Ib */
751 c896fe29 bellard
        tcg_out8(s, mem_index);
752 c896fe29 bellard
        tcg_out_opc(s, 0x50 + data_reg2); /* push */
753 c896fe29 bellard
        tcg_out_opc(s, 0x50 + data_reg); /* push */
754 c896fe29 bellard
        tcg_out8(s, 0xe8);
755 c896fe29 bellard
        tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - 
756 c896fe29 bellard
                  (tcg_target_long)s->code_ptr - 4);
757 c896fe29 bellard
        tcg_out_addi(s, TCG_REG_ESP, 12);
758 c896fe29 bellard
    } else {
759 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
760 c896fe29 bellard
        switch(opc) {
761 c896fe29 bellard
        case 0:
762 c896fe29 bellard
            /* movzbl */
763 c896fe29 bellard
            tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_ECX, data_reg);
764 c896fe29 bellard
            break;
765 c896fe29 bellard
        case 1:
766 c896fe29 bellard
            /* movzwl */
767 c896fe29 bellard
            tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_ECX, data_reg);
768 c896fe29 bellard
            break;
769 c896fe29 bellard
        case 2:
770 c896fe29 bellard
            tcg_out_mov(s, TCG_REG_ECX, data_reg);
771 c896fe29 bellard
            break;
772 c896fe29 bellard
        }
773 c896fe29 bellard
        tcg_out8(s, 0x6a); /* push Ib */
774 c896fe29 bellard
        tcg_out8(s, mem_index);
775 c896fe29 bellard
        tcg_out8(s, 0xe8);
776 c896fe29 bellard
        tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - 
777 c896fe29 bellard
                  (tcg_target_long)s->code_ptr - 4);
778 c896fe29 bellard
        tcg_out_addi(s, TCG_REG_ESP, 4);
779 c896fe29 bellard
    }
780 c896fe29 bellard
#endif
781 c896fe29 bellard
    
782 c896fe29 bellard
    /* jmp label2 */
783 c896fe29 bellard
    tcg_out8(s, 0xeb);
784 c896fe29 bellard
    label2_ptr = s->code_ptr;
785 c896fe29 bellard
    s->code_ptr++;
786 c896fe29 bellard
    
787 c896fe29 bellard
    /* label1: */
788 c896fe29 bellard
    *label1_ptr = s->code_ptr - label1_ptr - 1;
789 c896fe29 bellard
790 c896fe29 bellard
    /* add x(r1), r0 */
791 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) - 
792 c896fe29 bellard
                         offsetof(CPUTLBEntry, addr_write));
793 c896fe29 bellard
#else
794 c896fe29 bellard
    r0 = addr_reg;
795 c896fe29 bellard
#endif
796 c896fe29 bellard
797 c896fe29 bellard
#ifdef TARGET_WORDS_BIGENDIAN
798 c896fe29 bellard
    bswap = 1;
799 c896fe29 bellard
#else
800 c896fe29 bellard
    bswap = 0;
801 c896fe29 bellard
#endif
802 c896fe29 bellard
    switch(opc) {
803 c896fe29 bellard
    case 0:
804 c896fe29 bellard
        /* movb */
805 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x88, data_reg, r0, 0);
806 c896fe29 bellard
        break;
807 c896fe29 bellard
    case 1:
808 c896fe29 bellard
        if (bswap) {
809 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg);
810 c896fe29 bellard
            tcg_out8(s, 0x66); /* rolw $8, %ecx */
811 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, r1);
812 c896fe29 bellard
            tcg_out8(s, 8);
813 c896fe29 bellard
            data_reg = r1;
814 c896fe29 bellard
        }
815 c896fe29 bellard
        /* movw */
816 c896fe29 bellard
        tcg_out8(s, 0x66);
817 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
818 c896fe29 bellard
        break;
819 c896fe29 bellard
    case 2:
820 c896fe29 bellard
        if (bswap) {
821 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg);
822 c896fe29 bellard
            /* bswap data_reg */
823 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT);
824 c896fe29 bellard
            data_reg = r1;
825 c896fe29 bellard
        }
826 c896fe29 bellard
        /* movl */
827 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
828 c896fe29 bellard
        break;
829 c896fe29 bellard
    case 3:
830 c896fe29 bellard
        if (bswap) {
831 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg2);
832 c896fe29 bellard
            /* bswap data_reg */
833 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT);
834 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x89, r1, r0, 0);
835 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg);
836 c896fe29 bellard
            /* bswap data_reg */
837 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT);
838 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x89, r1, r0, 4);
839 c896fe29 bellard
        } else {
840 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
841 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x89, data_reg2, r0, 4);
842 c896fe29 bellard
        }
843 c896fe29 bellard
        break;
844 c896fe29 bellard
    default:
845 c896fe29 bellard
        tcg_abort();
846 c896fe29 bellard
    }
847 c896fe29 bellard
848 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
849 c896fe29 bellard
    /* label2: */
850 c896fe29 bellard
    *label2_ptr = s->code_ptr - label2_ptr - 1;
851 c896fe29 bellard
#endif
852 c896fe29 bellard
}
853 c896fe29 bellard
854 c896fe29 bellard
static inline void tcg_out_op(TCGContext *s, int opc, 
855 c896fe29 bellard
                              const TCGArg *args, const int *const_args)
856 c896fe29 bellard
{
857 c896fe29 bellard
    int c;
858 c896fe29 bellard
    
859 c896fe29 bellard
    switch(opc) {
860 c896fe29 bellard
    case INDEX_op_exit_tb:
861 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
862 b03cce8e bellard
        tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
863 b03cce8e bellard
        tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
864 c896fe29 bellard
        break;
865 c896fe29 bellard
    case INDEX_op_goto_tb:
866 c896fe29 bellard
        if (s->tb_jmp_offset) {
867 c896fe29 bellard
            /* direct jump method */
868 c896fe29 bellard
            tcg_out8(s, 0xe9); /* jmp im */
869 c896fe29 bellard
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
870 c896fe29 bellard
            tcg_out32(s, 0);
871 c896fe29 bellard
        } else {
872 c896fe29 bellard
            /* indirect jump method */
873 c896fe29 bellard
            /* jmp Ev */
874 c896fe29 bellard
            tcg_out_modrm_offset(s, 0xff, 4, -1, 
875 c896fe29 bellard
                                 (tcg_target_long)(s->tb_next + args[0]));
876 c896fe29 bellard
        }
877 c896fe29 bellard
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
878 c896fe29 bellard
        break;
879 c896fe29 bellard
    case INDEX_op_call:
880 c896fe29 bellard
        if (const_args[0]) {
881 c896fe29 bellard
            tcg_out8(s, 0xe8);
882 c896fe29 bellard
            tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
883 c896fe29 bellard
        } else {
884 c896fe29 bellard
            tcg_out_modrm(s, 0xff, 2, args[0]);
885 c896fe29 bellard
        }
886 c896fe29 bellard
        break;
887 c896fe29 bellard
    case INDEX_op_jmp:
888 c896fe29 bellard
        if (const_args[0]) {
889 c896fe29 bellard
            tcg_out8(s, 0xe9);
890 c896fe29 bellard
            tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
891 c896fe29 bellard
        } else {
892 c896fe29 bellard
            tcg_out_modrm(s, 0xff, 4, args[0]);
893 c896fe29 bellard
        }
894 c896fe29 bellard
        break;
895 c896fe29 bellard
    case INDEX_op_br:
896 c896fe29 bellard
        tcg_out_jxx(s, JCC_JMP, args[0]);
897 c896fe29 bellard
        break;
898 c896fe29 bellard
    case INDEX_op_movi_i32:
899 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
900 c896fe29 bellard
        break;
901 c896fe29 bellard
    case INDEX_op_ld8u_i32:
902 c896fe29 bellard
        /* movzbl */
903 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
904 c896fe29 bellard
        break;
905 c896fe29 bellard
    case INDEX_op_ld8s_i32:
906 c896fe29 bellard
        /* movsbl */
907 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
908 c896fe29 bellard
        break;
909 c896fe29 bellard
    case INDEX_op_ld16u_i32:
910 c896fe29 bellard
        /* movzwl */
911 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
912 c896fe29 bellard
        break;
913 c896fe29 bellard
    case INDEX_op_ld16s_i32:
914 c896fe29 bellard
        /* movswl */
915 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
916 c896fe29 bellard
        break;
917 c896fe29 bellard
    case INDEX_op_ld_i32:
918 c896fe29 bellard
        /* movl */
919 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
920 c896fe29 bellard
        break;
921 c896fe29 bellard
    case INDEX_op_st8_i32:
922 c896fe29 bellard
        /* movb */
923 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]);
924 c896fe29 bellard
        break;
925 c896fe29 bellard
    case INDEX_op_st16_i32:
926 c896fe29 bellard
        /* movw */
927 c896fe29 bellard
        tcg_out8(s, 0x66);
928 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
929 c896fe29 bellard
        break;
930 c896fe29 bellard
    case INDEX_op_st_i32:
931 c896fe29 bellard
        /* movl */
932 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
933 c896fe29 bellard
        break;
934 c896fe29 bellard
    case INDEX_op_sub_i32:
935 c896fe29 bellard
        c = ARITH_SUB;
936 c896fe29 bellard
        goto gen_arith;
937 c896fe29 bellard
    case INDEX_op_and_i32:
938 c896fe29 bellard
        c = ARITH_AND;
939 c896fe29 bellard
        goto gen_arith;
940 c896fe29 bellard
    case INDEX_op_or_i32:
941 c896fe29 bellard
        c = ARITH_OR;
942 c896fe29 bellard
        goto gen_arith;
943 c896fe29 bellard
    case INDEX_op_xor_i32:
944 c896fe29 bellard
        c = ARITH_XOR;
945 c896fe29 bellard
        goto gen_arith;
946 c896fe29 bellard
    case INDEX_op_add_i32:
947 c896fe29 bellard
        c = ARITH_ADD;
948 c896fe29 bellard
    gen_arith:
949 c896fe29 bellard
        if (const_args[2]) {
950 c896fe29 bellard
            tgen_arithi(s, c, args[0], args[2]);
951 c896fe29 bellard
        } else {
952 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
953 c896fe29 bellard
        }
954 c896fe29 bellard
        break;
955 c896fe29 bellard
    case INDEX_op_mul_i32:
956 c896fe29 bellard
        if (const_args[2]) {
957 c896fe29 bellard
            int32_t val;
958 c896fe29 bellard
            val = args[2];
959 c896fe29 bellard
            if (val == (int8_t)val) {
960 c896fe29 bellard
                tcg_out_modrm(s, 0x6b, args[0], args[0]);
961 c896fe29 bellard
                tcg_out8(s, val);
962 c896fe29 bellard
            } else {
963 c896fe29 bellard
                tcg_out_modrm(s, 0x69, args[0], args[0]);
964 c896fe29 bellard
                tcg_out32(s, val);
965 c896fe29 bellard
            }
966 c896fe29 bellard
        } else {
967 c896fe29 bellard
            tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
968 c896fe29 bellard
        }
969 c896fe29 bellard
        break;
970 c896fe29 bellard
    case INDEX_op_mulu2_i32:
971 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 4, args[3]);
972 c896fe29 bellard
        break;
973 c896fe29 bellard
    case INDEX_op_div2_i32:
974 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 7, args[4]);
975 c896fe29 bellard
        break;
976 c896fe29 bellard
    case INDEX_op_divu2_i32:
977 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 6, args[4]);
978 c896fe29 bellard
        break;
979 c896fe29 bellard
    case INDEX_op_shl_i32:
980 c896fe29 bellard
        c = SHIFT_SHL;
981 c896fe29 bellard
    gen_shift32:
982 c896fe29 bellard
        if (const_args[2]) {
983 c896fe29 bellard
            if (args[2] == 1) {
984 c896fe29 bellard
                tcg_out_modrm(s, 0xd1, c, args[0]);
985 c896fe29 bellard
            } else {
986 c896fe29 bellard
                tcg_out_modrm(s, 0xc1, c, args[0]);
987 c896fe29 bellard
                tcg_out8(s, args[2]);
988 c896fe29 bellard
            }
989 c896fe29 bellard
        } else {
990 c896fe29 bellard
            tcg_out_modrm(s, 0xd3, c, args[0]);
991 c896fe29 bellard
        }
992 c896fe29 bellard
        break;
993 c896fe29 bellard
    case INDEX_op_shr_i32:
994 c896fe29 bellard
        c = SHIFT_SHR;
995 c896fe29 bellard
        goto gen_shift32;
996 c896fe29 bellard
    case INDEX_op_sar_i32:
997 c896fe29 bellard
        c = SHIFT_SAR;
998 c896fe29 bellard
        goto gen_shift32;
999 c896fe29 bellard
        
1000 c896fe29 bellard
    case INDEX_op_add2_i32:
1001 c896fe29 bellard
        if (const_args[4]) 
1002 c896fe29 bellard
            tgen_arithi(s, ARITH_ADD, args[0], args[4]);
1003 c896fe29 bellard
        else
1004 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (ARITH_ADD << 3), args[4], args[0]);
1005 c896fe29 bellard
        if (const_args[5]) 
1006 c896fe29 bellard
            tgen_arithi(s, ARITH_ADC, args[1], args[5]);
1007 c896fe29 bellard
        else
1008 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (ARITH_ADC << 3), args[5], args[1]);
1009 c896fe29 bellard
        break;
1010 c896fe29 bellard
    case INDEX_op_sub2_i32:
1011 c896fe29 bellard
        if (const_args[4]) 
1012 c896fe29 bellard
            tgen_arithi(s, ARITH_SUB, args[0], args[4]);
1013 c896fe29 bellard
        else
1014 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (ARITH_SUB << 3), args[4], args[0]);
1015 c896fe29 bellard
        if (const_args[5]) 
1016 c896fe29 bellard
            tgen_arithi(s, ARITH_SBB, args[1], args[5]);
1017 c896fe29 bellard
        else
1018 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (ARITH_SBB << 3), args[5], args[1]);
1019 c896fe29 bellard
        break;
1020 c896fe29 bellard
    case INDEX_op_brcond_i32:
1021 c896fe29 bellard
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
1022 c896fe29 bellard
        break;
1023 c896fe29 bellard
    case INDEX_op_brcond2_i32:
1024 c896fe29 bellard
        tcg_out_brcond2(s, args, const_args);
1025 c896fe29 bellard
        break;
1026 c896fe29 bellard
1027 c896fe29 bellard
    case INDEX_op_qemu_ld8u:
1028 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 0);
1029 c896fe29 bellard
        break;
1030 c896fe29 bellard
    case INDEX_op_qemu_ld8s:
1031 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 0 | 4);
1032 c896fe29 bellard
        break;
1033 c896fe29 bellard
    case INDEX_op_qemu_ld16u:
1034 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 1);
1035 c896fe29 bellard
        break;
1036 c896fe29 bellard
    case INDEX_op_qemu_ld16s:
1037 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 1 | 4);
1038 c896fe29 bellard
        break;
1039 c896fe29 bellard
    case INDEX_op_qemu_ld32u:
1040 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 2);
1041 c896fe29 bellard
        break;
1042 c896fe29 bellard
    case INDEX_op_qemu_ld64:
1043 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 3);
1044 c896fe29 bellard
        break;
1045 c896fe29 bellard
        
1046 c896fe29 bellard
    case INDEX_op_qemu_st8:
1047 c896fe29 bellard
        tcg_out_qemu_st(s, args, 0);
1048 c896fe29 bellard
        break;
1049 c896fe29 bellard
    case INDEX_op_qemu_st16:
1050 c896fe29 bellard
        tcg_out_qemu_st(s, args, 1);
1051 c896fe29 bellard
        break;
1052 c896fe29 bellard
    case INDEX_op_qemu_st32:
1053 c896fe29 bellard
        tcg_out_qemu_st(s, args, 2);
1054 c896fe29 bellard
        break;
1055 c896fe29 bellard
    case INDEX_op_qemu_st64:
1056 c896fe29 bellard
        tcg_out_qemu_st(s, args, 3);
1057 c896fe29 bellard
        break;
1058 c896fe29 bellard
1059 c896fe29 bellard
    default:
1060 c896fe29 bellard
        tcg_abort();
1061 c896fe29 bellard
    }
1062 c896fe29 bellard
}
1063 c896fe29 bellard
1064 c896fe29 bellard
static const TCGTargetOpDef x86_op_defs[] = {
1065 c896fe29 bellard
    { INDEX_op_exit_tb, { } },
1066 c896fe29 bellard
    { INDEX_op_goto_tb, { } },
1067 c896fe29 bellard
    { INDEX_op_call, { "ri" } },
1068 c896fe29 bellard
    { INDEX_op_jmp, { "ri" } },
1069 c896fe29 bellard
    { INDEX_op_br, { } },
1070 c896fe29 bellard
    { INDEX_op_mov_i32, { "r", "r" } },
1071 c896fe29 bellard
    { INDEX_op_movi_i32, { "r" } },
1072 c896fe29 bellard
    { INDEX_op_ld8u_i32, { "r", "r" } },
1073 c896fe29 bellard
    { INDEX_op_ld8s_i32, { "r", "r" } },
1074 c896fe29 bellard
    { INDEX_op_ld16u_i32, { "r", "r" } },
1075 c896fe29 bellard
    { INDEX_op_ld16s_i32, { "r", "r" } },
1076 c896fe29 bellard
    { INDEX_op_ld_i32, { "r", "r" } },
1077 c896fe29 bellard
    { INDEX_op_st8_i32, { "q", "r" } },
1078 c896fe29 bellard
    { INDEX_op_st16_i32, { "r", "r" } },
1079 c896fe29 bellard
    { INDEX_op_st_i32, { "r", "r" } },
1080 c896fe29 bellard
1081 c896fe29 bellard
    { INDEX_op_add_i32, { "r", "0", "ri" } },
1082 c896fe29 bellard
    { INDEX_op_sub_i32, { "r", "0", "ri" } },
1083 c896fe29 bellard
    { INDEX_op_mul_i32, { "r", "0", "ri" } },
1084 c896fe29 bellard
    { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
1085 c896fe29 bellard
    { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1086 c896fe29 bellard
    { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1087 c896fe29 bellard
    { INDEX_op_and_i32, { "r", "0", "ri" } },
1088 c896fe29 bellard
    { INDEX_op_or_i32, { "r", "0", "ri" } },
1089 c896fe29 bellard
    { INDEX_op_xor_i32, { "r", "0", "ri" } },
1090 c896fe29 bellard
1091 c896fe29 bellard
    { INDEX_op_shl_i32, { "r", "0", "ci" } },
1092 c896fe29 bellard
    { INDEX_op_shr_i32, { "r", "0", "ci" } },
1093 c896fe29 bellard
    { INDEX_op_sar_i32, { "r", "0", "ci" } },
1094 c896fe29 bellard
1095 c896fe29 bellard
    { INDEX_op_brcond_i32, { "r", "ri" } },
1096 c896fe29 bellard
1097 c896fe29 bellard
    { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1098 c896fe29 bellard
    { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1099 c896fe29 bellard
    { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1100 c896fe29 bellard
1101 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1102 c896fe29 bellard
    { INDEX_op_qemu_ld8u, { "r", "L" } },
1103 c896fe29 bellard
    { INDEX_op_qemu_ld8s, { "r", "L" } },
1104 c896fe29 bellard
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1105 c896fe29 bellard
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1106 c896fe29 bellard
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1107 c896fe29 bellard
    { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1108 c896fe29 bellard
1109 c896fe29 bellard
    { INDEX_op_qemu_st8, { "cb", "L" } },
1110 c896fe29 bellard
    { INDEX_op_qemu_st16, { "L", "L" } },
1111 c896fe29 bellard
    { INDEX_op_qemu_st32, { "L", "L" } },
1112 c896fe29 bellard
    { INDEX_op_qemu_st64, { "L", "L", "L" } },
1113 c896fe29 bellard
#else
1114 c896fe29 bellard
    { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1115 c896fe29 bellard
    { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1116 c896fe29 bellard
    { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1117 c896fe29 bellard
    { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1118 c896fe29 bellard
    { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1119 c896fe29 bellard
    { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
1120 c896fe29 bellard
1121 c896fe29 bellard
    { INDEX_op_qemu_st8, { "cb", "L", "L" } },
1122 c896fe29 bellard
    { INDEX_op_qemu_st16, { "L", "L", "L" } },
1123 c896fe29 bellard
    { INDEX_op_qemu_st32, { "L", "L", "L" } },
1124 c896fe29 bellard
    { INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
1125 c896fe29 bellard
#endif
1126 c896fe29 bellard
    { -1 },
1127 c896fe29 bellard
};
1128 c896fe29 bellard
1129 b03cce8e bellard
static int tcg_target_callee_save_regs[] = {
1130 b03cce8e bellard
    /*    TCG_REG_EBP, */ /* currently used for the global env, so no
1131 b03cce8e bellard
                             need to save */
1132 b03cce8e bellard
    TCG_REG_EBX,
1133 b03cce8e bellard
    TCG_REG_ESI,
1134 b03cce8e bellard
    TCG_REG_EDI,
1135 b03cce8e bellard
};
1136 b03cce8e bellard
1137 b03cce8e bellard
static inline void tcg_out_push(TCGContext *s, int reg)
1138 b03cce8e bellard
{
1139 b03cce8e bellard
    tcg_out_opc(s, 0x50 + reg);
1140 b03cce8e bellard
}
1141 b03cce8e bellard
1142 b03cce8e bellard
static inline void tcg_out_pop(TCGContext *s, int reg)
1143 b03cce8e bellard
{
1144 b03cce8e bellard
    tcg_out_opc(s, 0x58 + reg);
1145 b03cce8e bellard
}
1146 b03cce8e bellard
1147 b03cce8e bellard
/* Generate global QEMU prologue and epilogue code */
1148 b03cce8e bellard
void tcg_target_qemu_prologue(TCGContext *s)
1149 b03cce8e bellard
{
1150 b03cce8e bellard
    int i, frame_size, push_size, stack_addend;
1151 b03cce8e bellard
    
1152 b03cce8e bellard
    /* TB prologue */
1153 b03cce8e bellard
    /* save all callee saved registers */
1154 b03cce8e bellard
    for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1155 b03cce8e bellard
        tcg_out_push(s, tcg_target_callee_save_regs[i]);
1156 b03cce8e bellard
    }
1157 b03cce8e bellard
    /* reserve some stack space */
1158 b03cce8e bellard
    push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
1159 b03cce8e bellard
    frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1160 b03cce8e bellard
    frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) & 
1161 b03cce8e bellard
        ~(TCG_TARGET_STACK_ALIGN - 1);
1162 b03cce8e bellard
    stack_addend = frame_size - push_size;
1163 b03cce8e bellard
    tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
1164 b03cce8e bellard
1165 b03cce8e bellard
    tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp *%eax */
1166 b03cce8e bellard
    
1167 b03cce8e bellard
    /* TB epilogue */
1168 b03cce8e bellard
    tb_ret_addr = s->code_ptr;
1169 b03cce8e bellard
    tcg_out_addi(s, TCG_REG_ESP, stack_addend);
1170 b03cce8e bellard
    for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1171 b03cce8e bellard
        tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1172 b03cce8e bellard
    }
1173 b03cce8e bellard
    tcg_out8(s, 0xc3); /* ret */
1174 b03cce8e bellard
}
1175 b03cce8e bellard
1176 c896fe29 bellard
void tcg_target_init(TCGContext *s)
1177 c896fe29 bellard
{
1178 c896fe29 bellard
    /* fail safe */
1179 c896fe29 bellard
    if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1180 c896fe29 bellard
        tcg_abort();
1181 c896fe29 bellard
1182 c896fe29 bellard
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
1183 c896fe29 bellard
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1184 c896fe29 bellard
                     (1 << TCG_REG_EAX) | 
1185 c896fe29 bellard
                     (1 << TCG_REG_EDX) | 
1186 c896fe29 bellard
                     (1 << TCG_REG_ECX));
1187 c896fe29 bellard
    
1188 c896fe29 bellard
    tcg_regset_clear(s->reserved_regs);
1189 c896fe29 bellard
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
1190 c896fe29 bellard
1191 c896fe29 bellard
    tcg_add_target_add_op_defs(x86_op_defs);
1192 c896fe29 bellard
}