root / hw / pci / shpc.c @ 5d87e4b7
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1 | b4a42f81 | Paolo Bonzini | #include "qemu-common.h" |
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2 | 1dc324d2 | Michael S. Tsirkin | #include <strings.h> |
3 | 1dc324d2 | Michael S. Tsirkin | #include <stdint.h> |
4 | 1de7afc9 | Paolo Bonzini | #include "qemu/range.h" |
5 | b4a42f81 | Paolo Bonzini | #include "qemu/error-report.h" |
6 | c759b24f | Michael S. Tsirkin | #include "hw/pci/shpc.h" |
7 | c759b24f | Michael S. Tsirkin | #include "hw/pci/pci.h" |
8 | 06aac7bd | Michael S. Tsirkin | #include "hw/pci/pci_bus.h" |
9 | c759b24f | Michael S. Tsirkin | #include "hw/pci/msi.h" |
10 | 1dc324d2 | Michael S. Tsirkin | |
11 | 1dc324d2 | Michael S. Tsirkin | /* TODO: model power only and disabled slot states. */
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12 | 1dc324d2 | Michael S. Tsirkin | /* TODO: handle SERR and wakeups */
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13 | 1dc324d2 | Michael S. Tsirkin | /* TODO: consider enabling 66MHz support */
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14 | 1dc324d2 | Michael S. Tsirkin | |
15 | 1dc324d2 | Michael S. Tsirkin | /* TODO: remove fully only on state DISABLED and LED off.
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16 | 1dc324d2 | Michael S. Tsirkin | * track state to properly record this. */
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17 | 1dc324d2 | Michael S. Tsirkin | |
18 | 1dc324d2 | Michael S. Tsirkin | /* SHPC Working Register Set */
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19 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_BASE_OFFSET 0x00 /* 4 bytes */ |
20 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */ |
21 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOTS_66 0x08 /* 4 bytes. */ |
22 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_NSLOTS 0x0C /* 1 byte */ |
23 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_FIRST_DEV 0x0D /* 1 byte */ |
24 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_PHYS_SLOT 0x0E /* 2 byte */ |
25 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_PHYS_NUM_MAX 0x7ff |
26 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_PHYS_NUM_UP 0x2000 |
27 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_PHYS_MRL 0x4000 |
28 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_PHYS_BUTTON 0x8000 |
29 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SEC_BUS 0x10 /* 2 bytes */ |
30 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SEC_BUS_33 0x0 |
31 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SEC_BUS_66 0x1 /* Unused */ |
32 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SEC_BUS_MASK 0x7 |
33 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_MSI_CTL 0x12 /* 1 byte */ |
34 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_PROG_IFC 0x13 /* 1 byte */ |
35 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_PROG_IFC_1_0 0x1 |
36 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_CODE 0x14 /* 1 byte */ |
37 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_TRGT 0x15 /* 1 byte */ |
38 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_TRGT_MIN 0x1 |
39 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_TRGT_MAX 0x1f |
40 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_STATUS 0x16 /* 2 bytes */ |
41 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_STATUS_BUSY 0x1 |
42 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_STATUS_MRL_OPEN 0x2 |
43 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_STATUS_INVALID_CMD 0x4 |
44 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_STATUS_INVALID_MODE 0x8 |
45 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_INT_LOCATOR 0x18 /* 4 bytes */ |
46 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_INT_COMMAND 0x1 |
47 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */ |
48 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SERR_INT 0x20 /* 4 bytes */ |
49 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_INT_DIS 0x1 |
50 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SERR_DIS 0x2 |
51 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_INT_DIS 0x4 |
52 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_ARB_SERR_DIS 0x8 |
53 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CMD_DETECTED 0x10000 |
54 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_ARB_DETECTED 0x20000 |
55 | 1dc324d2 | Michael S. Tsirkin | /* 4 bytes * slot # (start from 0) */
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56 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) |
57 | 1dc324d2 | Michael S. Tsirkin | /* 2 bytes */
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58 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s)) |
59 | 1dc324d2 | Michael S. Tsirkin | |
60 | 1dc324d2 | Michael S. Tsirkin | /* Same slot state masks are used for command and status registers */
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61 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATE_MASK 0x03 |
62 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATE_SHIFT \
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63 | 1dc324d2 | Michael S. Tsirkin | (ffs(SHPC_SLOT_STATE_MASK) - 1)
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64 | 1dc324d2 | Michael S. Tsirkin | |
65 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_STATE_NO 0x0 |
66 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_STATE_PWRONLY 0x1 |
67 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_STATE_ENABLED 0x2 |
68 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_STATE_DISABLED 0x3 |
69 | 1dc324d2 | Michael S. Tsirkin | |
70 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_PWR_LED_MASK 0xC |
71 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_PWR_LED_SHIFT \
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72 | 1dc324d2 | Michael S. Tsirkin | (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
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73 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_ATTN_LED_MASK 0x30 |
74 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_ATTN_LED_SHIFT \
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75 | 1dc324d2 | Michael S. Tsirkin | (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
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76 | 1dc324d2 | Michael S. Tsirkin | |
77 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_LED_NO 0x0 |
78 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_LED_ON 0x1 |
79 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_LED_BLINK 0x2 |
80 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_LED_OFF 0x3 |
81 | 1dc324d2 | Michael S. Tsirkin | |
82 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_PWR_FAULT 0x40 |
83 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_BUTTON 0x80 |
84 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_MRL_OPEN 0x100 |
85 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_66 0x200 |
86 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00 |
87 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3 |
88 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_PRSNT_25W 0x1 |
89 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_PRSNT_15W 0x2 |
90 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0 |
91 | 1dc324d2 | Michael S. Tsirkin | |
92 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000 |
93 | 1dc324d2 | Michael S. Tsirkin | |
94 | 1dc324d2 | Michael S. Tsirkin | |
95 | 1dc324d2 | Michael S. Tsirkin | /* 1 byte */
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96 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s)) |
97 | 1dc324d2 | Michael S. Tsirkin | /* 1 byte */
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98 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s)) |
99 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_EVENT_PRESENCE 0x01 |
100 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02 |
101 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_EVENT_BUTTON 0x04 |
102 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_EVENT_MRL 0x08 |
103 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10 |
104 | 1dc324d2 | Michael S. Tsirkin | /* Bits below are used for Serr/Int disable only */
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105 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20 |
106 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40 |
107 | 1dc324d2 | Michael S. Tsirkin | |
108 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_MIN_SLOTS 1 |
109 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_MAX_SLOTS 31 |
110 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
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111 | 1dc324d2 | Michael S. Tsirkin | |
112 | 1dc324d2 | Michael S. Tsirkin | /* SHPC Slot identifiers */
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113 | 1dc324d2 | Michael S. Tsirkin | |
114 | 1dc324d2 | Michael S. Tsirkin | /* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
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115 | 1dc324d2 | Michael S. Tsirkin | and give the rest of them physical *and* pci numbers starting from 1, so
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116 | 1dc324d2 | Michael S. Tsirkin | they match logical numbers. Note: this means that multiple slots must have
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117 | 1dc324d2 | Michael S. Tsirkin | different chassis number values, to make chassis+physical slot unique.
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118 | 1dc324d2 | Michael S. Tsirkin | TODO: make this configurable? */
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119 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1) |
120 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_LOGICAL_TO_IDX(target) ((target) - 1) |
121 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_IDX_TO_PCI(slot) ((slot) + 1) |
122 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1) |
123 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1) |
124 | 1dc324d2 | Michael S. Tsirkin | |
125 | 1dc324d2 | Michael S. Tsirkin | static int roundup_pow_of_two(int x) |
126 | 1dc324d2 | Michael S. Tsirkin | { |
127 | 1dc324d2 | Michael S. Tsirkin | x |= (x >> 1);
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128 | 1dc324d2 | Michael S. Tsirkin | x |= (x >> 2);
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129 | 1dc324d2 | Michael S. Tsirkin | x |= (x >> 4);
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130 | 1dc324d2 | Michael S. Tsirkin | x |= (x >> 8);
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131 | 1dc324d2 | Michael S. Tsirkin | x |= (x >> 16);
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132 | 1dc324d2 | Michael S. Tsirkin | return x + 1; |
133 | 1dc324d2 | Michael S. Tsirkin | } |
134 | 1dc324d2 | Michael S. Tsirkin | |
135 | 1dc324d2 | Michael S. Tsirkin | static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk) |
136 | 1dc324d2 | Michael S. Tsirkin | { |
137 | 1dc324d2 | Michael S. Tsirkin | uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot); |
138 | 1dc324d2 | Michael S. Tsirkin | return (pci_get_word(status) & msk) >> (ffs(msk) - 1); |
139 | 1dc324d2 | Michael S. Tsirkin | } |
140 | 1dc324d2 | Michael S. Tsirkin | |
141 | 1dc324d2 | Michael S. Tsirkin | static void shpc_set_status(SHPCDevice *shpc, |
142 | 1dc324d2 | Michael S. Tsirkin | int slot, uint8_t value, uint16_t msk)
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143 | 1dc324d2 | Michael S. Tsirkin | { |
144 | 1dc324d2 | Michael S. Tsirkin | uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot); |
145 | 1dc324d2 | Michael S. Tsirkin | pci_word_test_and_clear_mask(status, msk); |
146 | 1dc324d2 | Michael S. Tsirkin | pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
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147 | 1dc324d2 | Michael S. Tsirkin | } |
148 | 1dc324d2 | Michael S. Tsirkin | |
149 | 1dc324d2 | Michael S. Tsirkin | static void shpc_interrupt_update(PCIDevice *d) |
150 | 1dc324d2 | Michael S. Tsirkin | { |
151 | 1dc324d2 | Michael S. Tsirkin | SHPCDevice *shpc = d->shpc; |
152 | 1dc324d2 | Michael S. Tsirkin | int slot;
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153 | 1dc324d2 | Michael S. Tsirkin | int level = 0; |
154 | 1dc324d2 | Michael S. Tsirkin | uint32_t serr_int; |
155 | 1dc324d2 | Michael S. Tsirkin | uint32_t int_locator = 0;
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156 | 1dc324d2 | Michael S. Tsirkin | |
157 | 1dc324d2 | Michael S. Tsirkin | /* Update interrupt locator register */
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158 | 1dc324d2 | Michael S. Tsirkin | for (slot = 0; slot < shpc->nslots; ++slot) { |
159 | 1dc324d2 | Michael S. Tsirkin | uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)]; |
160 | 1dc324d2 | Michael S. Tsirkin | uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)]; |
161 | 1dc324d2 | Michael S. Tsirkin | uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
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162 | 1dc324d2 | Michael S. Tsirkin | if (event & ~disable) {
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163 | 1dc324d2 | Michael S. Tsirkin | int_locator |= mask; |
164 | 1dc324d2 | Michael S. Tsirkin | } |
165 | 1dc324d2 | Michael S. Tsirkin | } |
166 | 1dc324d2 | Michael S. Tsirkin | serr_int = pci_get_long(shpc->config + SHPC_SERR_INT); |
167 | 1dc324d2 | Michael S. Tsirkin | if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
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168 | 1dc324d2 | Michael S. Tsirkin | int_locator |= SHPC_INT_COMMAND; |
169 | 1dc324d2 | Michael S. Tsirkin | } |
170 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator); |
171 | 1dc324d2 | Michael S. Tsirkin | level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0; |
172 | 1dc324d2 | Michael S. Tsirkin | if (msi_enabled(d) && shpc->msi_requested != level)
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173 | 1dc324d2 | Michael S. Tsirkin | msi_notify(d, 0);
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174 | 1dc324d2 | Michael S. Tsirkin | else
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175 | 1dc324d2 | Michael S. Tsirkin | qemu_set_irq(d->irq[0], level);
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176 | 1dc324d2 | Michael S. Tsirkin | shpc->msi_requested = level; |
177 | 1dc324d2 | Michael S. Tsirkin | } |
178 | 1dc324d2 | Michael S. Tsirkin | |
179 | 1dc324d2 | Michael S. Tsirkin | static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed) |
180 | 1dc324d2 | Michael S. Tsirkin | { |
181 | 1dc324d2 | Michael S. Tsirkin | switch (speed) {
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182 | 1dc324d2 | Michael S. Tsirkin | case SHPC_SEC_BUS_33:
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183 | 1dc324d2 | Michael S. Tsirkin | shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK; |
184 | 1dc324d2 | Michael S. Tsirkin | shpc->config[SHPC_SEC_BUS] |= speed; |
185 | 1dc324d2 | Michael S. Tsirkin | break;
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186 | 1dc324d2 | Michael S. Tsirkin | default:
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187 | 1dc324d2 | Michael S. Tsirkin | pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS, |
188 | 1dc324d2 | Michael S. Tsirkin | SHPC_CMD_STATUS_INVALID_MODE); |
189 | 1dc324d2 | Michael S. Tsirkin | } |
190 | 1dc324d2 | Michael S. Tsirkin | } |
191 | 1dc324d2 | Michael S. Tsirkin | |
192 | 1dc324d2 | Michael S. Tsirkin | void shpc_reset(PCIDevice *d)
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193 | 1dc324d2 | Michael S. Tsirkin | { |
194 | 1dc324d2 | Michael S. Tsirkin | SHPCDevice *shpc = d->shpc; |
195 | 1dc324d2 | Michael S. Tsirkin | int nslots = shpc->nslots;
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196 | 1dc324d2 | Michael S. Tsirkin | int i;
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197 | 1dc324d2 | Michael S. Tsirkin | memset(shpc->config, 0, SHPC_SIZEOF(d));
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198 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(shpc->config + SHPC_NSLOTS, nslots); |
199 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(shpc->config + SHPC_SLOTS_33, nslots); |
200 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
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201 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
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202 | 1dc324d2 | Michael S. Tsirkin | pci_set_word(shpc->config + SHPC_PHYS_SLOT, |
203 | 1dc324d2 | Michael S. Tsirkin | SHPC_IDX_TO_PHYSICAL(0) |
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204 | 1dc324d2 | Michael S. Tsirkin | SHPC_PHYS_NUM_UP | |
205 | 1dc324d2 | Michael S. Tsirkin | SHPC_PHYS_MRL | |
206 | 1dc324d2 | Michael S. Tsirkin | SHPC_PHYS_BUTTON); |
207 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS | |
208 | 1dc324d2 | Michael S. Tsirkin | SHPC_SERR_DIS | |
209 | 1dc324d2 | Michael S. Tsirkin | SHPC_CMD_INT_DIS | |
210 | 1dc324d2 | Michael S. Tsirkin | SHPC_ARB_SERR_DIS); |
211 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0); |
212 | 1dc324d2 | Michael S. Tsirkin | pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33); |
213 | 1dc324d2 | Michael S. Tsirkin | for (i = 0; i < shpc->nslots; ++i) { |
214 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i), |
215 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_PRESENCE | |
216 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_ISOLATED_FAULT | |
217 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_BUTTON | |
218 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_MRL | |
219 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_CONNECTED_FAULT | |
220 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_MRL_SERR_DIS | |
221 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS); |
222 | 1dc324d2 | Michael S. Tsirkin | if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) { |
223 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); |
224 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
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225 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W, |
226 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_STATUS_PRSNT_MASK); |
227 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK); |
228 | 1dc324d2 | Michael S. Tsirkin | } else {
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229 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); |
230 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
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231 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY, |
232 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_STATUS_PRSNT_MASK); |
233 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK); |
234 | 1dc324d2 | Michael S. Tsirkin | } |
235 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
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236 | 1dc324d2 | Michael S. Tsirkin | } |
237 | 1dc324d2 | Michael S. Tsirkin | shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33); |
238 | 1dc324d2 | Michael S. Tsirkin | shpc->msi_requested = 0;
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239 | 1dc324d2 | Michael S. Tsirkin | shpc_interrupt_update(d); |
240 | 1dc324d2 | Michael S. Tsirkin | } |
241 | 1dc324d2 | Michael S. Tsirkin | |
242 | 1dc324d2 | Michael S. Tsirkin | static void shpc_invalid_command(SHPCDevice *shpc) |
243 | 1dc324d2 | Michael S. Tsirkin | { |
244 | 1dc324d2 | Michael S. Tsirkin | pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS, |
245 | 1dc324d2 | Michael S. Tsirkin | SHPC_CMD_STATUS_INVALID_CMD); |
246 | 1dc324d2 | Michael S. Tsirkin | } |
247 | 1dc324d2 | Michael S. Tsirkin | |
248 | 1dc324d2 | Michael S. Tsirkin | static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot) |
249 | 1dc324d2 | Michael S. Tsirkin | { |
250 | 1dc324d2 | Michael S. Tsirkin | int devfn;
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251 | 1dc324d2 | Michael S. Tsirkin | int pci_slot = SHPC_IDX_TO_PCI(slot);
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252 | 1dc324d2 | Michael S. Tsirkin | for (devfn = PCI_DEVFN(pci_slot, 0); |
253 | 1dc324d2 | Michael S. Tsirkin | devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
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254 | 1dc324d2 | Michael S. Tsirkin | ++devfn) { |
255 | 1dc324d2 | Michael S. Tsirkin | PCIDevice *affected_dev = shpc->sec_bus->devices[devfn]; |
256 | 1dc324d2 | Michael S. Tsirkin | if (affected_dev) {
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257 | 1dc324d2 | Michael S. Tsirkin | qdev_free(&affected_dev->qdev); |
258 | 1dc324d2 | Michael S. Tsirkin | } |
259 | 1dc324d2 | Michael S. Tsirkin | } |
260 | 1dc324d2 | Michael S. Tsirkin | } |
261 | 1dc324d2 | Michael S. Tsirkin | |
262 | 1dc324d2 | Michael S. Tsirkin | static void shpc_slot_command(SHPCDevice *shpc, uint8_t target, |
263 | 1dc324d2 | Michael S. Tsirkin | uint8_t state, uint8_t power, uint8_t attn) |
264 | 1dc324d2 | Michael S. Tsirkin | { |
265 | 1dc324d2 | Michael S. Tsirkin | uint8_t current_state; |
266 | 1dc324d2 | Michael S. Tsirkin | int slot = SHPC_LOGICAL_TO_IDX(target);
|
267 | 1dc324d2 | Michael S. Tsirkin | if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
|
268 | 1dc324d2 | Michael S. Tsirkin | shpc_invalid_command(shpc); |
269 | 1dc324d2 | Michael S. Tsirkin | return;
|
270 | 1dc324d2 | Michael S. Tsirkin | } |
271 | 1dc324d2 | Michael S. Tsirkin | current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); |
272 | 1dc324d2 | Michael S. Tsirkin | if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
|
273 | 1dc324d2 | Michael S. Tsirkin | shpc_invalid_command(shpc); |
274 | 1dc324d2 | Michael S. Tsirkin | return;
|
275 | 1dc324d2 | Michael S. Tsirkin | } |
276 | 1dc324d2 | Michael S. Tsirkin | |
277 | 1dc324d2 | Michael S. Tsirkin | switch (power) {
|
278 | 1dc324d2 | Michael S. Tsirkin | case SHPC_LED_NO:
|
279 | 1dc324d2 | Michael S. Tsirkin | break;
|
280 | 1dc324d2 | Michael S. Tsirkin | default:
|
281 | 1dc324d2 | Michael S. Tsirkin | /* TODO: send event to monitor */
|
282 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK); |
283 | 1dc324d2 | Michael S. Tsirkin | } |
284 | 1dc324d2 | Michael S. Tsirkin | switch (attn) {
|
285 | 1dc324d2 | Michael S. Tsirkin | case SHPC_LED_NO:
|
286 | 1dc324d2 | Michael S. Tsirkin | break;
|
287 | 1dc324d2 | Michael S. Tsirkin | default:
|
288 | 1dc324d2 | Michael S. Tsirkin | /* TODO: send event to monitor */
|
289 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK); |
290 | 1dc324d2 | Michael S. Tsirkin | } |
291 | 1dc324d2 | Michael S. Tsirkin | |
292 | 1dc324d2 | Michael S. Tsirkin | if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
|
293 | 1dc324d2 | Michael S. Tsirkin | (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) { |
294 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); |
295 | 1dc324d2 | Michael S. Tsirkin | } else if ((current_state == SHPC_STATE_ENABLED || |
296 | 1dc324d2 | Michael S. Tsirkin | current_state == SHPC_STATE_PWRONLY) && |
297 | 1dc324d2 | Michael S. Tsirkin | state == SHPC_STATE_DISABLED) { |
298 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); |
299 | 1dc324d2 | Michael S. Tsirkin | power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK); |
300 | 1dc324d2 | Michael S. Tsirkin | /* TODO: track what monitor requested. */
|
301 | 1dc324d2 | Michael S. Tsirkin | /* Look at LED to figure out whether it's ok to remove the device. */
|
302 | 1dc324d2 | Michael S. Tsirkin | if (power == SHPC_LED_OFF) {
|
303 | 1dc324d2 | Michael S. Tsirkin | shpc_free_devices_in_slot(shpc, slot); |
304 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
|
305 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY, |
306 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_STATUS_PRSNT_MASK); |
307 | 1dc324d2 | Michael S. Tsirkin | shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= |
308 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_BUTTON | |
309 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_MRL | |
310 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_PRESENCE; |
311 | 1dc324d2 | Michael S. Tsirkin | } |
312 | 1dc324d2 | Michael S. Tsirkin | } |
313 | 1dc324d2 | Michael S. Tsirkin | } |
314 | 1dc324d2 | Michael S. Tsirkin | |
315 | 1dc324d2 | Michael S. Tsirkin | static void shpc_command(SHPCDevice *shpc) |
316 | 1dc324d2 | Michael S. Tsirkin | { |
317 | 1dc324d2 | Michael S. Tsirkin | uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE); |
318 | 1dc324d2 | Michael S. Tsirkin | uint8_t speed; |
319 | 1dc324d2 | Michael S. Tsirkin | uint8_t target; |
320 | 1dc324d2 | Michael S. Tsirkin | uint8_t attn; |
321 | 1dc324d2 | Michael S. Tsirkin | uint8_t power; |
322 | 1dc324d2 | Michael S. Tsirkin | uint8_t state; |
323 | 1dc324d2 | Michael S. Tsirkin | int i;
|
324 | 1dc324d2 | Michael S. Tsirkin | |
325 | 1dc324d2 | Michael S. Tsirkin | /* Clear status from the previous command. */
|
326 | 1dc324d2 | Michael S. Tsirkin | pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS, |
327 | 1dc324d2 | Michael S. Tsirkin | SHPC_CMD_STATUS_BUSY | |
328 | 1dc324d2 | Michael S. Tsirkin | SHPC_CMD_STATUS_MRL_OPEN | |
329 | 1dc324d2 | Michael S. Tsirkin | SHPC_CMD_STATUS_INVALID_CMD | |
330 | 1dc324d2 | Michael S. Tsirkin | SHPC_CMD_STATUS_INVALID_MODE); |
331 | 1dc324d2 | Michael S. Tsirkin | switch (code) {
|
332 | 1dc324d2 | Michael S. Tsirkin | case 0x00 ... 0x3f: |
333 | 1dc324d2 | Michael S. Tsirkin | target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX; |
334 | 1dc324d2 | Michael S. Tsirkin | state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; |
335 | 1dc324d2 | Michael S. Tsirkin | power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT; |
336 | 1dc324d2 | Michael S. Tsirkin | attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT; |
337 | 1dc324d2 | Michael S. Tsirkin | shpc_slot_command(shpc, target, state, power, attn); |
338 | 1dc324d2 | Michael S. Tsirkin | break;
|
339 | 1dc324d2 | Michael S. Tsirkin | case 0x40 ... 0x47: |
340 | 1dc324d2 | Michael S. Tsirkin | speed = code & SHPC_SEC_BUS_MASK; |
341 | 1dc324d2 | Michael S. Tsirkin | shpc_set_sec_bus_speed(shpc, speed); |
342 | 1dc324d2 | Michael S. Tsirkin | break;
|
343 | 1dc324d2 | Michael S. Tsirkin | case 0x48: |
344 | 1dc324d2 | Michael S. Tsirkin | /* Power only all slots */
|
345 | 1dc324d2 | Michael S. Tsirkin | /* first verify no slots are enabled */
|
346 | 1dc324d2 | Michael S. Tsirkin | for (i = 0; i < shpc->nslots; ++i) { |
347 | 1dc324d2 | Michael S. Tsirkin | state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); |
348 | 1dc324d2 | Michael S. Tsirkin | if (state == SHPC_STATE_ENABLED) {
|
349 | 1dc324d2 | Michael S. Tsirkin | shpc_invalid_command(shpc); |
350 | 1dc324d2 | Michael S. Tsirkin | goto done;
|
351 | 1dc324d2 | Michael S. Tsirkin | } |
352 | 1dc324d2 | Michael S. Tsirkin | } |
353 | 1dc324d2 | Michael S. Tsirkin | for (i = 0; i < shpc->nslots; ++i) { |
354 | 1dc324d2 | Michael S. Tsirkin | if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
|
355 | 1dc324d2 | Michael S. Tsirkin | shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, |
356 | 1dc324d2 | Michael S. Tsirkin | SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO); |
357 | 1dc324d2 | Michael S. Tsirkin | } else {
|
358 | 1dc324d2 | Michael S. Tsirkin | shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, |
359 | 1dc324d2 | Michael S. Tsirkin | SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO); |
360 | 1dc324d2 | Michael S. Tsirkin | } |
361 | 1dc324d2 | Michael S. Tsirkin | } |
362 | 1dc324d2 | Michael S. Tsirkin | break;
|
363 | 1dc324d2 | Michael S. Tsirkin | case 0x49: |
364 | 1dc324d2 | Michael S. Tsirkin | /* Enable all slots */
|
365 | 1dc324d2 | Michael S. Tsirkin | /* TODO: Spec says this shall fail if some are already enabled.
|
366 | 1dc324d2 | Michael S. Tsirkin | * This doesn't make sense - why not? a spec bug? */
|
367 | 1dc324d2 | Michael S. Tsirkin | for (i = 0; i < shpc->nslots; ++i) { |
368 | 1dc324d2 | Michael S. Tsirkin | state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); |
369 | 1dc324d2 | Michael S. Tsirkin | if (state == SHPC_STATE_ENABLED) {
|
370 | 1dc324d2 | Michael S. Tsirkin | shpc_invalid_command(shpc); |
371 | 1dc324d2 | Michael S. Tsirkin | goto done;
|
372 | 1dc324d2 | Michael S. Tsirkin | } |
373 | 1dc324d2 | Michael S. Tsirkin | } |
374 | 1dc324d2 | Michael S. Tsirkin | for (i = 0; i < shpc->nslots; ++i) { |
375 | 1dc324d2 | Michael S. Tsirkin | if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
|
376 | 1dc324d2 | Michael S. Tsirkin | shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, |
377 | 1dc324d2 | Michael S. Tsirkin | SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO); |
378 | 1dc324d2 | Michael S. Tsirkin | } else {
|
379 | 1dc324d2 | Michael S. Tsirkin | shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, |
380 | 1dc324d2 | Michael S. Tsirkin | SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO); |
381 | 1dc324d2 | Michael S. Tsirkin | } |
382 | 1dc324d2 | Michael S. Tsirkin | } |
383 | 1dc324d2 | Michael S. Tsirkin | break;
|
384 | 1dc324d2 | Michael S. Tsirkin | default:
|
385 | 1dc324d2 | Michael S. Tsirkin | shpc_invalid_command(shpc); |
386 | 1dc324d2 | Michael S. Tsirkin | break;
|
387 | 1dc324d2 | Michael S. Tsirkin | } |
388 | 1dc324d2 | Michael S. Tsirkin | done:
|
389 | 1dc324d2 | Michael S. Tsirkin | pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED); |
390 | 1dc324d2 | Michael S. Tsirkin | } |
391 | 1dc324d2 | Michael S. Tsirkin | |
392 | 1dc324d2 | Michael S. Tsirkin | static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l) |
393 | 1dc324d2 | Michael S. Tsirkin | { |
394 | 1dc324d2 | Michael S. Tsirkin | SHPCDevice *shpc = d->shpc; |
395 | 1dc324d2 | Michael S. Tsirkin | int i;
|
396 | 1dc324d2 | Michael S. Tsirkin | if (addr >= SHPC_SIZEOF(d)) {
|
397 | 1dc324d2 | Michael S. Tsirkin | return;
|
398 | 1dc324d2 | Michael S. Tsirkin | } |
399 | 1dc324d2 | Michael S. Tsirkin | l = MIN(l, SHPC_SIZEOF(d) - addr); |
400 | 1dc324d2 | Michael S. Tsirkin | |
401 | 1dc324d2 | Michael S. Tsirkin | /* TODO: code duplicated from pci.c */
|
402 | 1dc324d2 | Michael S. Tsirkin | for (i = 0; i < l; val >>= 8, ++i) { |
403 | 1dc324d2 | Michael S. Tsirkin | unsigned a = addr + i;
|
404 | 1dc324d2 | Michael S. Tsirkin | uint8_t wmask = shpc->wmask[a]; |
405 | 1dc324d2 | Michael S. Tsirkin | uint8_t w1cmask = shpc->w1cmask[a]; |
406 | 1dc324d2 | Michael S. Tsirkin | assert(!(wmask & w1cmask)); |
407 | 1dc324d2 | Michael S. Tsirkin | shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask); |
408 | 1dc324d2 | Michael S. Tsirkin | shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
|
409 | 1dc324d2 | Michael S. Tsirkin | } |
410 | 1dc324d2 | Michael S. Tsirkin | if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) { |
411 | 1dc324d2 | Michael S. Tsirkin | shpc_command(shpc); |
412 | 1dc324d2 | Michael S. Tsirkin | } |
413 | 1dc324d2 | Michael S. Tsirkin | shpc_interrupt_update(d); |
414 | 1dc324d2 | Michael S. Tsirkin | } |
415 | 1dc324d2 | Michael S. Tsirkin | |
416 | 1dc324d2 | Michael S. Tsirkin | static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l) |
417 | 1dc324d2 | Michael S. Tsirkin | { |
418 | 1dc324d2 | Michael S. Tsirkin | uint64_t val = 0x0;
|
419 | 1dc324d2 | Michael S. Tsirkin | if (addr >= SHPC_SIZEOF(d)) {
|
420 | 1dc324d2 | Michael S. Tsirkin | return val;
|
421 | 1dc324d2 | Michael S. Tsirkin | } |
422 | 1dc324d2 | Michael S. Tsirkin | l = MIN(l, SHPC_SIZEOF(d) - addr); |
423 | 1dc324d2 | Michael S. Tsirkin | memcpy(&val, d->shpc->config + addr, l); |
424 | 1dc324d2 | Michael S. Tsirkin | return val;
|
425 | 1dc324d2 | Michael S. Tsirkin | } |
426 | 1dc324d2 | Michael S. Tsirkin | |
427 | 1dc324d2 | Michael S. Tsirkin | /* SHPC Bridge Capability */
|
428 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CAP_LENGTH 0x08 |
429 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */ |
430 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */ |
431 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */ |
432 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CAP_CSP_MASK 0x4 |
433 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_CAP_CIP_MASK 0x8 |
434 | 1dc324d2 | Michael S. Tsirkin | |
435 | 1dc324d2 | Michael S. Tsirkin | static uint8_t shpc_cap_dword(PCIDevice *d)
|
436 | 1dc324d2 | Michael S. Tsirkin | { |
437 | 1dc324d2 | Michael S. Tsirkin | return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
|
438 | 1dc324d2 | Michael S. Tsirkin | } |
439 | 1dc324d2 | Michael S. Tsirkin | |
440 | 1dc324d2 | Michael S. Tsirkin | /* Update dword data capability register */
|
441 | 1dc324d2 | Michael S. Tsirkin | static void shpc_cap_update_dword(PCIDevice *d) |
442 | 1dc324d2 | Michael S. Tsirkin | { |
443 | 1dc324d2 | Michael S. Tsirkin | unsigned data;
|
444 | 1dc324d2 | Michael S. Tsirkin | data = shpc_read(d, shpc_cap_dword(d) * 4, 4); |
445 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data); |
446 | 1dc324d2 | Michael S. Tsirkin | } |
447 | 1dc324d2 | Michael S. Tsirkin | |
448 | 1dc324d2 | Michael S. Tsirkin | /* Add SHPC capability to the config space for the device. */
|
449 | 1dc324d2 | Michael S. Tsirkin | static int shpc_cap_add_config(PCIDevice *d) |
450 | 1dc324d2 | Michael S. Tsirkin | { |
451 | 1dc324d2 | Michael S. Tsirkin | uint8_t *config; |
452 | 1dc324d2 | Michael S. Tsirkin | int config_offset;
|
453 | 1dc324d2 | Michael S. Tsirkin | config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC, |
454 | 1dc324d2 | Michael S. Tsirkin | 0, SHPC_CAP_LENGTH);
|
455 | 1dc324d2 | Michael S. Tsirkin | if (config_offset < 0) { |
456 | 1dc324d2 | Michael S. Tsirkin | return config_offset;
|
457 | 1dc324d2 | Michael S. Tsirkin | } |
458 | 1dc324d2 | Michael S. Tsirkin | config = d->config + config_offset; |
459 | 1dc324d2 | Michael S. Tsirkin | |
460 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
|
461 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(config + SHPC_CAP_CxP, 0);
|
462 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
|
463 | 1dc324d2 | Michael S. Tsirkin | d->shpc->cap = config_offset; |
464 | 1dc324d2 | Michael S. Tsirkin | /* Make dword select and data writeable. */
|
465 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
|
466 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
|
467 | 1dc324d2 | Michael S. Tsirkin | return 0; |
468 | 1dc324d2 | Michael S. Tsirkin | } |
469 | 1dc324d2 | Michael S. Tsirkin | |
470 | a8170e5e | Avi Kivity | static uint64_t shpc_mmio_read(void *opaque, hwaddr addr, |
471 | 1dc324d2 | Michael S. Tsirkin | unsigned size)
|
472 | 1dc324d2 | Michael S. Tsirkin | { |
473 | 1dc324d2 | Michael S. Tsirkin | return shpc_read(opaque, addr, size);
|
474 | 1dc324d2 | Michael S. Tsirkin | } |
475 | 1dc324d2 | Michael S. Tsirkin | |
476 | a8170e5e | Avi Kivity | static void shpc_mmio_write(void *opaque, hwaddr addr, |
477 | 1dc324d2 | Michael S. Tsirkin | uint64_t val, unsigned size)
|
478 | 1dc324d2 | Michael S. Tsirkin | { |
479 | 1dc324d2 | Michael S. Tsirkin | shpc_write(opaque, addr, val, size); |
480 | 1dc324d2 | Michael S. Tsirkin | } |
481 | 1dc324d2 | Michael S. Tsirkin | |
482 | 1dc324d2 | Michael S. Tsirkin | static const MemoryRegionOps shpc_mmio_ops = { |
483 | 1dc324d2 | Michael S. Tsirkin | .read = shpc_mmio_read, |
484 | 1dc324d2 | Michael S. Tsirkin | .write = shpc_mmio_write, |
485 | 1dc324d2 | Michael S. Tsirkin | .endianness = DEVICE_LITTLE_ENDIAN, |
486 | 1dc324d2 | Michael S. Tsirkin | .valid = { |
487 | 1dc324d2 | Michael S. Tsirkin | /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
|
488 | 1dc324d2 | Michael S. Tsirkin | * It's easier to suppport all sizes than worry about it. */
|
489 | 1dc324d2 | Michael S. Tsirkin | .min_access_size = 1,
|
490 | 1dc324d2 | Michael S. Tsirkin | .max_access_size = 4,
|
491 | 1dc324d2 | Michael S. Tsirkin | }, |
492 | 1dc324d2 | Michael S. Tsirkin | }; |
493 | 1dc324d2 | Michael S. Tsirkin | |
494 | 1dc324d2 | Michael S. Tsirkin | static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev, |
495 | 1dc324d2 | Michael S. Tsirkin | PCIHotplugState hotplug_state) |
496 | 1dc324d2 | Michael S. Tsirkin | { |
497 | 1dc324d2 | Michael S. Tsirkin | int pci_slot = PCI_SLOT(affected_dev->devfn);
|
498 | 1dc324d2 | Michael S. Tsirkin | uint8_t state; |
499 | 1dc324d2 | Michael S. Tsirkin | uint8_t led; |
500 | 1dc324d2 | Michael S. Tsirkin | PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); |
501 | 1dc324d2 | Michael S. Tsirkin | SHPCDevice *shpc = d->shpc; |
502 | 1dc324d2 | Michael S. Tsirkin | int slot = SHPC_PCI_TO_IDX(pci_slot);
|
503 | 1dc324d2 | Michael S. Tsirkin | if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) { |
504 | 1dc324d2 | Michael S. Tsirkin | error_report("Unsupported PCI slot %d for standard hotplug "
|
505 | 1dc324d2 | Michael S. Tsirkin | "controller. Valid slots are between %d and %d.",
|
506 | 1dc324d2 | Michael S. Tsirkin | pci_slot, SHPC_IDX_TO_PCI(0),
|
507 | 1dc324d2 | Michael S. Tsirkin | SHPC_IDX_TO_PCI(shpc->nslots) - 1);
|
508 | 1dc324d2 | Michael S. Tsirkin | return -1; |
509 | 1dc324d2 | Michael S. Tsirkin | } |
510 | 1dc324d2 | Michael S. Tsirkin | /* Don't send event when device is enabled during qemu machine creation:
|
511 | 1dc324d2 | Michael S. Tsirkin | * it is present on boot, no hotplug event is necessary. We do send an
|
512 | 1dc324d2 | Michael S. Tsirkin | * event when the device is disabled later. */
|
513 | 1dc324d2 | Michael S. Tsirkin | if (hotplug_state == PCI_COLDPLUG_ENABLED) {
|
514 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
|
515 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W, |
516 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_STATUS_PRSNT_MASK); |
517 | 1dc324d2 | Michael S. Tsirkin | return 0; |
518 | 1dc324d2 | Michael S. Tsirkin | } |
519 | 1dc324d2 | Michael S. Tsirkin | if (hotplug_state == PCI_HOTPLUG_DISABLED) {
|
520 | 1dc324d2 | Michael S. Tsirkin | shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON; |
521 | 1dc324d2 | Michael S. Tsirkin | state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); |
522 | 1dc324d2 | Michael S. Tsirkin | led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK); |
523 | 1dc324d2 | Michael S. Tsirkin | if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
|
524 | 1dc324d2 | Michael S. Tsirkin | shpc_free_devices_in_slot(shpc, slot); |
525 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
|
526 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY, |
527 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_STATUS_PRSNT_MASK); |
528 | 1dc324d2 | Michael S. Tsirkin | shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= |
529 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_MRL | |
530 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_PRESENCE; |
531 | 1dc324d2 | Michael S. Tsirkin | } |
532 | 1dc324d2 | Michael S. Tsirkin | } else {
|
533 | 1dc324d2 | Michael S. Tsirkin | /* This could be a cancellation of the previous removal.
|
534 | 1dc324d2 | Michael S. Tsirkin | * We check MRL state to figure out. */
|
535 | 1dc324d2 | Michael S. Tsirkin | if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
|
536 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
|
537 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W, |
538 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_STATUS_PRSNT_MASK); |
539 | 1dc324d2 | Michael S. Tsirkin | shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= |
540 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_BUTTON | |
541 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_MRL | |
542 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_PRESENCE; |
543 | 1dc324d2 | Michael S. Tsirkin | } else {
|
544 | 1dc324d2 | Michael S. Tsirkin | /* Press attention button to cancel removal */
|
545 | 1dc324d2 | Michael S. Tsirkin | shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= |
546 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_BUTTON; |
547 | 1dc324d2 | Michael S. Tsirkin | } |
548 | 1dc324d2 | Michael S. Tsirkin | } |
549 | 1dc324d2 | Michael S. Tsirkin | shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
|
550 | 1dc324d2 | Michael S. Tsirkin | shpc_interrupt_update(d); |
551 | 1dc324d2 | Michael S. Tsirkin | return 0; |
552 | 1dc324d2 | Michael S. Tsirkin | } |
553 | 1dc324d2 | Michael S. Tsirkin | |
554 | 1dc324d2 | Michael S. Tsirkin | /* Initialize the SHPC structure in bridge's BAR. */
|
555 | 1dc324d2 | Michael S. Tsirkin | int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset) |
556 | 1dc324d2 | Michael S. Tsirkin | { |
557 | 1dc324d2 | Michael S. Tsirkin | int i, ret;
|
558 | 1dc324d2 | Michael S. Tsirkin | int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */ |
559 | 1dc324d2 | Michael S. Tsirkin | SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
|
560 | 1dc324d2 | Michael S. Tsirkin | shpc->sec_bus = sec_bus; |
561 | 1dc324d2 | Michael S. Tsirkin | ret = shpc_cap_add_config(d); |
562 | 1dc324d2 | Michael S. Tsirkin | if (ret) {
|
563 | 1dc324d2 | Michael S. Tsirkin | g_free(d->shpc); |
564 | 1dc324d2 | Michael S. Tsirkin | return ret;
|
565 | 1dc324d2 | Michael S. Tsirkin | } |
566 | 1dc324d2 | Michael S. Tsirkin | if (nslots < SHPC_MIN_SLOTS) {
|
567 | 1dc324d2 | Michael S. Tsirkin | return 0; |
568 | 1dc324d2 | Michael S. Tsirkin | } |
569 | 1dc324d2 | Michael S. Tsirkin | if (nslots > SHPC_MAX_SLOTS ||
|
570 | 1dc324d2 | Michael S. Tsirkin | SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) { |
571 | 1dc324d2 | Michael S. Tsirkin | /* TODO: report an error mesage that makes sense. */
|
572 | 1dc324d2 | Michael S. Tsirkin | return -EINVAL;
|
573 | 1dc324d2 | Michael S. Tsirkin | } |
574 | 1dc324d2 | Michael S. Tsirkin | shpc->nslots = nslots; |
575 | 1dc324d2 | Michael S. Tsirkin | shpc->config = g_malloc0(SHPC_SIZEOF(d)); |
576 | 1dc324d2 | Michael S. Tsirkin | shpc->cmask = g_malloc0(SHPC_SIZEOF(d)); |
577 | 1dc324d2 | Michael S. Tsirkin | shpc->wmask = g_malloc0(SHPC_SIZEOF(d)); |
578 | 1dc324d2 | Michael S. Tsirkin | shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d)); |
579 | 1dc324d2 | Michael S. Tsirkin | |
580 | 1dc324d2 | Michael S. Tsirkin | shpc_reset(d); |
581 | 1dc324d2 | Michael S. Tsirkin | |
582 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset); |
583 | 1dc324d2 | Michael S. Tsirkin | |
584 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
|
585 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); |
586 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); |
587 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(shpc->wmask + SHPC_SERR_INT, |
588 | 1dc324d2 | Michael S. Tsirkin | SHPC_INT_DIS | |
589 | 1dc324d2 | Michael S. Tsirkin | SHPC_SERR_DIS | |
590 | 1dc324d2 | Michael S. Tsirkin | SHPC_CMD_INT_DIS | |
591 | 1dc324d2 | Michael S. Tsirkin | SHPC_ARB_SERR_DIS); |
592 | 1dc324d2 | Michael S. Tsirkin | pci_set_long(shpc->w1cmask + SHPC_SERR_INT, |
593 | 1dc324d2 | Michael S. Tsirkin | SHPC_CMD_DETECTED | |
594 | 1dc324d2 | Michael S. Tsirkin | SHPC_ARB_DETECTED); |
595 | 1dc324d2 | Michael S. Tsirkin | for (i = 0; i < nslots; ++i) { |
596 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(shpc->wmask + |
597 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_SERR_INT_DIS(d, i), |
598 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_PRESENCE | |
599 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_ISOLATED_FAULT | |
600 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_BUTTON | |
601 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_MRL | |
602 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_CONNECTED_FAULT | |
603 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_MRL_SERR_DIS | |
604 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS); |
605 | 1dc324d2 | Michael S. Tsirkin | pci_set_byte(shpc->w1cmask + |
606 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_LATCH(i), |
607 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_PRESENCE | |
608 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_ISOLATED_FAULT | |
609 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_BUTTON | |
610 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_MRL | |
611 | 1dc324d2 | Michael S. Tsirkin | SHPC_SLOT_EVENT_CONNECTED_FAULT); |
612 | 1dc324d2 | Michael S. Tsirkin | } |
613 | 1dc324d2 | Michael S. Tsirkin | |
614 | 1dc324d2 | Michael S. Tsirkin | /* TODO: init cmask */
|
615 | 40c5dce9 | Paolo Bonzini | memory_region_init_io(&shpc->mmio, OBJECT(d), &shpc_mmio_ops, |
616 | 40c5dce9 | Paolo Bonzini | d, "shpc-mmio", SHPC_SIZEOF(d));
|
617 | 1dc324d2 | Michael S. Tsirkin | shpc_cap_update_dword(d); |
618 | 1dc324d2 | Michael S. Tsirkin | memory_region_add_subregion(bar, offset, &shpc->mmio); |
619 | 1dc324d2 | Michael S. Tsirkin | pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev); |
620 | 1dc324d2 | Michael S. Tsirkin | |
621 | 1dc324d2 | Michael S. Tsirkin | d->cap_present |= QEMU_PCI_CAP_SHPC; |
622 | 1dc324d2 | Michael S. Tsirkin | return 0; |
623 | 1dc324d2 | Michael S. Tsirkin | } |
624 | 1dc324d2 | Michael S. Tsirkin | |
625 | 1dc324d2 | Michael S. Tsirkin | int shpc_bar_size(PCIDevice *d)
|
626 | 1dc324d2 | Michael S. Tsirkin | { |
627 | 1dc324d2 | Michael S. Tsirkin | return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
|
628 | 1dc324d2 | Michael S. Tsirkin | } |
629 | 1dc324d2 | Michael S. Tsirkin | |
630 | 1dc324d2 | Michael S. Tsirkin | void shpc_cleanup(PCIDevice *d, MemoryRegion *bar)
|
631 | 1dc324d2 | Michael S. Tsirkin | { |
632 | 1dc324d2 | Michael S. Tsirkin | SHPCDevice *shpc = d->shpc; |
633 | 1dc324d2 | Michael S. Tsirkin | d->cap_present &= ~QEMU_PCI_CAP_SHPC; |
634 | 1dc324d2 | Michael S. Tsirkin | memory_region_del_subregion(bar, &shpc->mmio); |
635 | 1dc324d2 | Michael S. Tsirkin | /* TODO: cleanup config space changes? */
|
636 | 1dc324d2 | Michael S. Tsirkin | g_free(shpc->config); |
637 | 1dc324d2 | Michael S. Tsirkin | g_free(shpc->cmask); |
638 | 1dc324d2 | Michael S. Tsirkin | g_free(shpc->wmask); |
639 | 1dc324d2 | Michael S. Tsirkin | g_free(shpc->w1cmask); |
640 | 1dc324d2 | Michael S. Tsirkin | memory_region_destroy(&shpc->mmio); |
641 | 1dc324d2 | Michael S. Tsirkin | g_free(shpc); |
642 | 1dc324d2 | Michael S. Tsirkin | } |
643 | 1dc324d2 | Michael S. Tsirkin | |
644 | 1dc324d2 | Michael S. Tsirkin | void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
645 | 1dc324d2 | Michael S. Tsirkin | { |
646 | 1dc324d2 | Michael S. Tsirkin | if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
|
647 | 1dc324d2 | Michael S. Tsirkin | return;
|
648 | 1dc324d2 | Michael S. Tsirkin | } |
649 | 1dc324d2 | Michael S. Tsirkin | if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) { |
650 | 1dc324d2 | Michael S. Tsirkin | unsigned dword_data;
|
651 | 1dc324d2 | Michael S. Tsirkin | dword_data = pci_get_long(d->shpc->config + d->shpc->cap |
652 | 1dc324d2 | Michael S. Tsirkin | + SHPC_CAP_DWORD_DATA); |
653 | 1dc324d2 | Michael S. Tsirkin | shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4); |
654 | 1dc324d2 | Michael S. Tsirkin | } |
655 | 1dc324d2 | Michael S. Tsirkin | /* Update cap dword data in case guest is going to read it. */
|
656 | 1dc324d2 | Michael S. Tsirkin | shpc_cap_update_dword(d); |
657 | 1dc324d2 | Michael S. Tsirkin | } |
658 | 1dc324d2 | Michael S. Tsirkin | |
659 | 1dc324d2 | Michael S. Tsirkin | static void shpc_save(QEMUFile *f, void *pv, size_t size) |
660 | 1dc324d2 | Michael S. Tsirkin | { |
661 | 1dc324d2 | Michael S. Tsirkin | PCIDevice *d = container_of(pv, PCIDevice, shpc); |
662 | 1dc324d2 | Michael S. Tsirkin | qemu_put_buffer(f, d->shpc->config, SHPC_SIZEOF(d)); |
663 | 1dc324d2 | Michael S. Tsirkin | } |
664 | 1dc324d2 | Michael S. Tsirkin | |
665 | 1dc324d2 | Michael S. Tsirkin | static int shpc_load(QEMUFile *f, void *pv, size_t size) |
666 | 1dc324d2 | Michael S. Tsirkin | { |
667 | 1dc324d2 | Michael S. Tsirkin | PCIDevice *d = container_of(pv, PCIDevice, shpc); |
668 | 1dc324d2 | Michael S. Tsirkin | int ret = qemu_get_buffer(f, d->shpc->config, SHPC_SIZEOF(d));
|
669 | 1dc324d2 | Michael S. Tsirkin | if (ret != SHPC_SIZEOF(d)) {
|
670 | 1dc324d2 | Michael S. Tsirkin | return -EINVAL;
|
671 | 1dc324d2 | Michael S. Tsirkin | } |
672 | 1dc324d2 | Michael S. Tsirkin | /* Make sure we don't lose notifications. An extra interrupt is harmless. */
|
673 | 1dc324d2 | Michael S. Tsirkin | d->shpc->msi_requested = 0;
|
674 | 1dc324d2 | Michael S. Tsirkin | shpc_interrupt_update(d); |
675 | 1dc324d2 | Michael S. Tsirkin | return 0; |
676 | 1dc324d2 | Michael S. Tsirkin | } |
677 | 1dc324d2 | Michael S. Tsirkin | |
678 | 1dc324d2 | Michael S. Tsirkin | VMStateInfo shpc_vmstate_info = { |
679 | 1dc324d2 | Michael S. Tsirkin | .name = "shpc",
|
680 | 1dc324d2 | Michael S. Tsirkin | .get = shpc_load, |
681 | 1dc324d2 | Michael S. Tsirkin | .put = shpc_save, |
682 | 1dc324d2 | Michael S. Tsirkin | }; |