root / hw / pci / pci.c @ 5d87e4b7
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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "hw/pci/pci.h" |
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#include "hw/pci/pci_bridge.h" |
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#include "hw/pci/pci_bus.h" |
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#include "hw/pci/pci_host.h" |
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#include "monitor/monitor.h" |
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#include "net/net.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/loader.h" |
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#include "qemu/range.h" |
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#include "qmp-commands.h" |
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#include "hw/pci/msi.h" |
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#include "hw/pci/msix.h" |
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#include "exec/address-spaces.h" |
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define PCI_DPRINTF(format, ...) do { } while (0) |
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#endif
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
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static char *pcibus_get_dev_path(DeviceState *dev); |
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static char *pcibus_get_fw_dev_path(DeviceState *dev); |
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static int pcibus_reset(BusState *qbus); |
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static Property pci_props[] = {
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DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
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DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
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DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), |
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DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
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QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
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DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
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QEMU_PCI_CAP_SERR_BITNR, true),
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DEFINE_PROP_END_OF_LIST() |
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}; |
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static void pci_bus_class_init(ObjectClass *klass, void *data) |
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{ |
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BusClass *k = BUS_CLASS(klass); |
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k->print_dev = pcibus_dev_print; |
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k->get_dev_path = pcibus_get_dev_path; |
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k->get_fw_dev_path = pcibus_get_fw_dev_path; |
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k->reset = pcibus_reset; |
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} |
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static const TypeInfo pci_bus_info = { |
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.name = TYPE_PCI_BUS, |
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.parent = TYPE_BUS, |
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.instance_size = sizeof(PCIBus),
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.class_init = pci_bus_class_init, |
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}; |
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static const TypeInfo pcie_bus_info = { |
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.name = TYPE_PCIE_BUS, |
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.parent = TYPE_PCI_BUS, |
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}; |
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static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); |
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static void pci_update_mappings(PCIDevice *d); |
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static void pci_set_irq(void *opaque, int irq_num, int level); |
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static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); |
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static void pci_del_option_rom(PCIDevice *pdev); |
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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static QLIST_HEAD(, PCIHostState) pci_host_bridges;
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static const VMStateDescription vmstate_pcibus = { |
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.name = "PCIBUS",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_EQUAL(nirq, PCIBus), |
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VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static int pci_bar(PCIDevice *d, int reg) |
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{ |
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uint8_t type; |
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if (reg != PCI_ROM_SLOT)
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return PCI_BASE_ADDRESS_0 + reg * 4; |
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type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
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return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
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} |
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static inline int pci_irq_state(PCIDevice *d, int irq_num) |
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{ |
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return (d->irq_state >> irq_num) & 0x1; |
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} |
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static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) |
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{ |
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d->irq_state &= ~(0x1 << irq_num);
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d->irq_state |= level << irq_num; |
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} |
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static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) |
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{ |
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PCIBus *bus; |
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for (;;) {
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bus = pci_dev->bus; |
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irq_num = bus->map_irq(pci_dev, irq_num); |
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if (bus->set_irq)
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break;
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pci_dev = bus->parent_dev; |
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} |
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bus->irq_count[irq_num] += change; |
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bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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} |
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int pci_bus_get_irq_level(PCIBus *bus, int irq_num) |
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{ |
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assert(irq_num >= 0);
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assert(irq_num < bus->nirq); |
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return !!bus->irq_count[irq_num];
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} |
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/* Update interrupt status bit in config space on interrupt
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* state change. */
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static void pci_update_irq_status(PCIDevice *dev) |
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{ |
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if (dev->irq_state) {
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dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; |
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} else {
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dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
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} |
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} |
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void pci_device_deassert_intx(PCIDevice *dev)
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{ |
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int i;
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for (i = 0; i < PCI_NUM_PINS; ++i) { |
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qemu_set_irq(dev->irq[i], 0);
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} |
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} |
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/*
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* This function is called on #RST and FLR.
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* FLR if PCI_EXP_DEVCTL_BCR_FLR is set
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*/
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void pci_device_reset(PCIDevice *dev)
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{ |
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int r;
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qdev_reset_all(&dev->qdev); |
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dev->irq_state = 0;
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pci_update_irq_status(dev); |
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pci_device_deassert_intx(dev); |
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/* Clear all writable bits */
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pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, |
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pci_get_word(dev->wmask + PCI_COMMAND) | |
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pci_get_word(dev->w1cmask + PCI_COMMAND)); |
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pci_word_test_and_clear_mask(dev->config + PCI_STATUS, |
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pci_get_word(dev->wmask + PCI_STATUS) | |
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pci_get_word(dev->w1cmask + PCI_STATUS)); |
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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dev->config[PCI_INTERRUPT_LINE] = 0x0;
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for (r = 0; r < PCI_NUM_REGIONS; ++r) { |
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PCIIORegion *region = &dev->io_regions[r]; |
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if (!region->size) {
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continue;
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} |
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if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
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region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
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pci_set_quad(dev->config + pci_bar(dev, r), region->type); |
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} else {
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pci_set_long(dev->config + pci_bar(dev, r), region->type); |
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} |
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} |
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pci_update_mappings(dev); |
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msi_reset(dev); |
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msix_reset(dev); |
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} |
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/*
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* Trigger pci bus reset under a given bus.
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* To be called on RST# assert.
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*/
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void pci_bus_reset(PCIBus *bus)
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{ |
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int i;
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for (i = 0; i < bus->nirq; i++) { |
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bus->irq_count[i] = 0;
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} |
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for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
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if (bus->devices[i]) {
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pci_device_reset(bus->devices[i]); |
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} |
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} |
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} |
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static int pcibus_reset(BusState *qbus) |
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{ |
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pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); |
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/* topology traverse is done by pci_bus_reset().
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Tell qbus/qdev walker not to traverse the tree */
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return 1; |
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} |
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static void pci_host_bus_register(PCIBus *bus, DeviceState *parent) |
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{ |
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PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent); |
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QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); |
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} |
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PCIBus *pci_find_primary_bus(void)
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{ |
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PCIBus *primary_bus = NULL;
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PCIHostState *host; |
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QLIST_FOREACH(host, &pci_host_bridges, next) { |
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if (primary_bus) {
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/* We have multiple root buses, refuse to select a primary */
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return NULL; |
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} |
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primary_bus = host->bus; |
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} |
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return primary_bus;
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} |
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PCIBus *pci_device_root_bus(const PCIDevice *d)
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{ |
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PCIBus *bus = d->bus; |
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while ((d = bus->parent_dev) != NULL) { |
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bus = d->bus; |
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} |
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return bus;
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} |
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const char *pci_root_bus_path(PCIDevice *dev) |
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{ |
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PCIBus *rootbus = pci_device_root_bus(dev); |
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PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); |
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); |
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assert(!rootbus->parent_dev); |
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assert(host_bridge->bus == rootbus); |
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if (hc->root_bus_path) {
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return (*hc->root_bus_path)(host_bridge, rootbus);
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} |
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return rootbus->qbus.name;
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} |
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static void pci_bus_init(PCIBus *bus, DeviceState *parent, |
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const char *name, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min) |
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{ |
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assert(PCI_FUNC(devfn_min) == 0);
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bus->devfn_min = devfn_min; |
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bus->address_space_mem = address_space_mem; |
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bus->address_space_io = address_space_io; |
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/* host bridge */
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QLIST_INIT(&bus->child); |
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pci_host_bus_register(bus, parent); |
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vmstate_register(NULL, -1, &vmstate_pcibus, bus); |
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} |
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bool pci_bus_is_express(PCIBus *bus)
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{ |
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return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
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} |
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bool pci_bus_is_root(PCIBus *bus)
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{ |
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return !bus->parent_dev;
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} |
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void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
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const char *name, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min, const char *typename) |
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{ |
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qbus_create_inplace(bus, bus_size, typename, parent, name); |
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pci_bus_init(bus, parent, name, address_space_mem, |
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address_space_io, devfn_min); |
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} |
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PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min, const char *typename) |
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{ |
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PCIBus *bus; |
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bus = PCI_BUS(qbus_create(typename, parent, name)); |
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pci_bus_init(bus, parent, name, address_space_mem, |
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address_space_io, devfn_min); |
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return bus;
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} |
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|
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int nirq) |
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{ |
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bus->set_irq = set_irq; |
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bus->map_irq = map_irq; |
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bus->irq_opaque = irq_opaque; |
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bus->nirq = nirq; |
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bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); |
347 |
} |
348 |
|
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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
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{ |
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bus->qbus.allow_hotplug = 1;
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bus->hotplug = hotplug; |
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bus->hotplug_qdev = qdev; |
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} |
355 |
|
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PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
357 |
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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void *irq_opaque,
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min, int nirq, const char *typename) |
362 |
{ |
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PCIBus *bus; |
364 |
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bus = pci_bus_new(parent, name, address_space_mem, |
366 |
address_space_io, devfn_min, typename); |
367 |
pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
368 |
return bus;
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} |
370 |
|
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int pci_bus_num(PCIBus *s)
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{ |
373 |
if (pci_bus_is_root(s))
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return 0; /* pci host bridge */ |
375 |
return s->parent_dev->config[PCI_SECONDARY_BUS];
|
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} |
377 |
|
378 |
static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
379 |
{ |
380 |
PCIDevice *s = container_of(pv, PCIDevice, config); |
381 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); |
382 |
uint8_t *config; |
383 |
int i;
|
384 |
|
385 |
assert(size == pci_config_size(s)); |
386 |
config = g_malloc(size); |
387 |
|
388 |
qemu_get_buffer(f, config, size); |
389 |
for (i = 0; i < size; ++i) { |
390 |
if ((config[i] ^ s->config[i]) &
|
391 |
s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { |
392 |
g_free(config); |
393 |
return -EINVAL;
|
394 |
} |
395 |
} |
396 |
memcpy(s->config, config, size); |
397 |
|
398 |
pci_update_mappings(s); |
399 |
if (pc->is_bridge) {
|
400 |
PCIBridge *b = PCI_BRIDGE(s); |
401 |
pci_bridge_update_mappings(b); |
402 |
} |
403 |
|
404 |
memory_region_set_enabled(&s->bus_master_enable_region, |
405 |
pci_get_word(s->config + PCI_COMMAND) |
406 |
& PCI_COMMAND_MASTER); |
407 |
|
408 |
g_free(config); |
409 |
return 0; |
410 |
} |
411 |
|
412 |
/* just put buffer */
|
413 |
static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
414 |
{ |
415 |
const uint8_t **v = pv;
|
416 |
assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
417 |
qemu_put_buffer(f, *v, size); |
418 |
} |
419 |
|
420 |
static VMStateInfo vmstate_info_pci_config = {
|
421 |
.name = "pci config",
|
422 |
.get = get_pci_config_device, |
423 |
.put = put_pci_config_device, |
424 |
}; |
425 |
|
426 |
static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
427 |
{ |
428 |
PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
429 |
uint32_t irq_state[PCI_NUM_PINS]; |
430 |
int i;
|
431 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
432 |
irq_state[i] = qemu_get_be32(f); |
433 |
if (irq_state[i] != 0x1 && irq_state[i] != 0) { |
434 |
fprintf(stderr, "irq state %d: must be 0 or 1.\n",
|
435 |
irq_state[i]); |
436 |
return -EINVAL;
|
437 |
} |
438 |
} |
439 |
|
440 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
441 |
pci_set_irq_state(s, i, irq_state[i]); |
442 |
} |
443 |
|
444 |
return 0; |
445 |
} |
446 |
|
447 |
static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
448 |
{ |
449 |
int i;
|
450 |
PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
451 |
|
452 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
453 |
qemu_put_be32(f, pci_irq_state(s, i)); |
454 |
} |
455 |
} |
456 |
|
457 |
static VMStateInfo vmstate_info_pci_irq_state = {
|
458 |
.name = "pci irq state",
|
459 |
.get = get_pci_irq_state, |
460 |
.put = put_pci_irq_state, |
461 |
}; |
462 |
|
463 |
const VMStateDescription vmstate_pci_device = {
|
464 |
.name = "PCIDevice",
|
465 |
.version_id = 2,
|
466 |
.minimum_version_id = 1,
|
467 |
.minimum_version_id_old = 1,
|
468 |
.fields = (VMStateField []) { |
469 |
VMSTATE_INT32_LE(version_id, PCIDevice), |
470 |
VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
|
471 |
vmstate_info_pci_config, |
472 |
PCI_CONFIG_SPACE_SIZE), |
473 |
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
|
474 |
vmstate_info_pci_irq_state, |
475 |
PCI_NUM_PINS * sizeof(int32_t)),
|
476 |
VMSTATE_END_OF_LIST() |
477 |
} |
478 |
}; |
479 |
|
480 |
const VMStateDescription vmstate_pcie_device = {
|
481 |
.name = "PCIEDevice",
|
482 |
.version_id = 2,
|
483 |
.minimum_version_id = 1,
|
484 |
.minimum_version_id_old = 1,
|
485 |
.fields = (VMStateField []) { |
486 |
VMSTATE_INT32_LE(version_id, PCIDevice), |
487 |
VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
|
488 |
vmstate_info_pci_config, |
489 |
PCIE_CONFIG_SPACE_SIZE), |
490 |
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
|
491 |
vmstate_info_pci_irq_state, |
492 |
PCI_NUM_PINS * sizeof(int32_t)),
|
493 |
VMSTATE_END_OF_LIST() |
494 |
} |
495 |
}; |
496 |
|
497 |
static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
498 |
{ |
499 |
return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
|
500 |
} |
501 |
|
502 |
void pci_device_save(PCIDevice *s, QEMUFile *f)
|
503 |
{ |
504 |
/* Clear interrupt status bit: it is implicit
|
505 |
* in irq_state which we are saving.
|
506 |
* This makes us compatible with old devices
|
507 |
* which never set or clear this bit. */
|
508 |
s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
509 |
vmstate_save_state(f, pci_get_vmstate(s), s); |
510 |
/* Restore the interrupt status bit. */
|
511 |
pci_update_irq_status(s); |
512 |
} |
513 |
|
514 |
int pci_device_load(PCIDevice *s, QEMUFile *f)
|
515 |
{ |
516 |
int ret;
|
517 |
ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); |
518 |
/* Restore the interrupt status bit. */
|
519 |
pci_update_irq_status(s); |
520 |
return ret;
|
521 |
} |
522 |
|
523 |
static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
524 |
{ |
525 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
526 |
pci_default_sub_vendor_id); |
527 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
528 |
pci_default_sub_device_id); |
529 |
} |
530 |
|
531 |
/*
|
532 |
* Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
|
533 |
* [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
|
534 |
*/
|
535 |
int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
536 |
unsigned int *slotp, unsigned int *funcp) |
537 |
{ |
538 |
const char *p; |
539 |
char *e;
|
540 |
unsigned long val; |
541 |
unsigned long dom = 0, bus = 0; |
542 |
unsigned int slot = 0; |
543 |
unsigned int func = 0; |
544 |
|
545 |
p = addr; |
546 |
val = strtoul(p, &e, 16);
|
547 |
if (e == p)
|
548 |
return -1; |
549 |
if (*e == ':') { |
550 |
bus = val; |
551 |
p = e + 1;
|
552 |
val = strtoul(p, &e, 16);
|
553 |
if (e == p)
|
554 |
return -1; |
555 |
if (*e == ':') { |
556 |
dom = bus; |
557 |
bus = val; |
558 |
p = e + 1;
|
559 |
val = strtoul(p, &e, 16);
|
560 |
if (e == p)
|
561 |
return -1; |
562 |
} |
563 |
} |
564 |
|
565 |
slot = val; |
566 |
|
567 |
if (funcp != NULL) { |
568 |
if (*e != '.') |
569 |
return -1; |
570 |
|
571 |
p = e + 1;
|
572 |
val = strtoul(p, &e, 16);
|
573 |
if (e == p)
|
574 |
return -1; |
575 |
|
576 |
func = val; |
577 |
} |
578 |
|
579 |
/* if funcp == NULL func is 0 */
|
580 |
if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) |
581 |
return -1; |
582 |
|
583 |
if (*e)
|
584 |
return -1; |
585 |
|
586 |
*domp = dom; |
587 |
*busp = bus; |
588 |
*slotp = slot; |
589 |
if (funcp != NULL) |
590 |
*funcp = func; |
591 |
return 0; |
592 |
} |
593 |
|
594 |
PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr) |
595 |
{ |
596 |
int dom, bus;
|
597 |
unsigned slot;
|
598 |
|
599 |
assert(!root->parent_dev); |
600 |
|
601 |
if (!root) {
|
602 |
fprintf(stderr, "No primary PCI bus\n");
|
603 |
return NULL; |
604 |
} |
605 |
|
606 |
if (!devaddr) {
|
607 |
*devfnp = -1;
|
608 |
return pci_find_bus_nr(root, 0); |
609 |
} |
610 |
|
611 |
if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { |
612 |
return NULL; |
613 |
} |
614 |
|
615 |
if (dom != 0) { |
616 |
fprintf(stderr, "No support for non-zero PCI domains\n");
|
617 |
return NULL; |
618 |
} |
619 |
|
620 |
*devfnp = PCI_DEVFN(slot, 0);
|
621 |
return pci_find_bus_nr(root, bus);
|
622 |
} |
623 |
|
624 |
static void pci_init_cmask(PCIDevice *dev) |
625 |
{ |
626 |
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
|
627 |
pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
|
628 |
dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; |
629 |
dev->cmask[PCI_REVISION_ID] = 0xff;
|
630 |
dev->cmask[PCI_CLASS_PROG] = 0xff;
|
631 |
pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
|
632 |
dev->cmask[PCI_HEADER_TYPE] = 0xff;
|
633 |
dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
|
634 |
} |
635 |
|
636 |
static void pci_init_wmask(PCIDevice *dev) |
637 |
{ |
638 |
int config_size = pci_config_size(dev);
|
639 |
|
640 |
dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
|
641 |
dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
|
642 |
pci_set_word(dev->wmask + PCI_COMMAND, |
643 |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
644 |
PCI_COMMAND_INTX_DISABLE); |
645 |
if (dev->cap_present & QEMU_PCI_CAP_SERR) {
|
646 |
pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); |
647 |
} |
648 |
|
649 |
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
|
650 |
config_size - PCI_CONFIG_HEADER_SIZE); |
651 |
} |
652 |
|
653 |
static void pci_init_w1cmask(PCIDevice *dev) |
654 |
{ |
655 |
/*
|
656 |
* Note: It's okay to set w1cmask even for readonly bits as
|
657 |
* long as their value is hardwired to 0.
|
658 |
*/
|
659 |
pci_set_word(dev->w1cmask + PCI_STATUS, |
660 |
PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | |
661 |
PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | |
662 |
PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); |
663 |
} |
664 |
|
665 |
static void pci_init_mask_bridge(PCIDevice *d) |
666 |
{ |
667 |
/* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
|
668 |
PCI_SEC_LETENCY_TIMER */
|
669 |
memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); |
670 |
|
671 |
/* base and limit */
|
672 |
d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
|
673 |
d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
|
674 |
pci_set_word(d->wmask + PCI_MEMORY_BASE, |
675 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
676 |
pci_set_word(d->wmask + PCI_MEMORY_LIMIT, |
677 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
678 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, |
679 |
PCI_PREF_RANGE_MASK & 0xffff);
|
680 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, |
681 |
PCI_PREF_RANGE_MASK & 0xffff);
|
682 |
|
683 |
/* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
|
684 |
memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); |
685 |
|
686 |
/* Supported memory and i/o types */
|
687 |
d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; |
688 |
d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; |
689 |
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, |
690 |
PCI_PREF_RANGE_TYPE_64); |
691 |
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, |
692 |
PCI_PREF_RANGE_TYPE_64); |
693 |
|
694 |
/*
|
695 |
* TODO: Bridges default to 10-bit VGA decoding but we currently only
|
696 |
* implement 16-bit decoding (no alias support).
|
697 |
*/
|
698 |
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, |
699 |
PCI_BRIDGE_CTL_PARITY | |
700 |
PCI_BRIDGE_CTL_SERR | |
701 |
PCI_BRIDGE_CTL_ISA | |
702 |
PCI_BRIDGE_CTL_VGA | |
703 |
PCI_BRIDGE_CTL_VGA_16BIT | |
704 |
PCI_BRIDGE_CTL_MASTER_ABORT | |
705 |
PCI_BRIDGE_CTL_BUS_RESET | |
706 |
PCI_BRIDGE_CTL_FAST_BACK | |
707 |
PCI_BRIDGE_CTL_DISCARD | |
708 |
PCI_BRIDGE_CTL_SEC_DISCARD | |
709 |
PCI_BRIDGE_CTL_DISCARD_SERR); |
710 |
/* Below does not do anything as we never set this bit, put here for
|
711 |
* completeness. */
|
712 |
pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, |
713 |
PCI_BRIDGE_CTL_DISCARD_STATUS); |
714 |
d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; |
715 |
d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; |
716 |
pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, |
717 |
PCI_PREF_RANGE_TYPE_MASK); |
718 |
pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, |
719 |
PCI_PREF_RANGE_TYPE_MASK); |
720 |
} |
721 |
|
722 |
static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |
723 |
{ |
724 |
uint8_t slot = PCI_SLOT(dev->devfn); |
725 |
uint8_t func; |
726 |
|
727 |
if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
|
728 |
dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; |
729 |
} |
730 |
|
731 |
/*
|
732 |
* multifunction bit is interpreted in two ways as follows.
|
733 |
* - all functions must set the bit to 1.
|
734 |
* Example: Intel X53
|
735 |
* - function 0 must set the bit, but the rest function (> 0)
|
736 |
* is allowed to leave the bit to 0.
|
737 |
* Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
|
738 |
*
|
739 |
* So OS (at least Linux) checks the bit of only function 0,
|
740 |
* and doesn't see the bit of function > 0.
|
741 |
*
|
742 |
* The below check allows both interpretation.
|
743 |
*/
|
744 |
if (PCI_FUNC(dev->devfn)) {
|
745 |
PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
|
746 |
if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
|
747 |
/* function 0 should set multifunction bit */
|
748 |
error_report("PCI: single function device can't be populated "
|
749 |
"in function %x.%x", slot, PCI_FUNC(dev->devfn));
|
750 |
return -1; |
751 |
} |
752 |
return 0; |
753 |
} |
754 |
|
755 |
if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
|
756 |
return 0; |
757 |
} |
758 |
/* function 0 indicates single function, so function > 0 must be NULL */
|
759 |
for (func = 1; func < PCI_FUNC_MAX; ++func) { |
760 |
if (bus->devices[PCI_DEVFN(slot, func)]) {
|
761 |
error_report("PCI: %x.0 indicates single function, "
|
762 |
"but %x.%x is already populated.",
|
763 |
slot, slot, func); |
764 |
return -1; |
765 |
} |
766 |
} |
767 |
return 0; |
768 |
} |
769 |
|
770 |
static void pci_config_alloc(PCIDevice *pci_dev) |
771 |
{ |
772 |
int config_size = pci_config_size(pci_dev);
|
773 |
|
774 |
pci_dev->config = g_malloc0(config_size); |
775 |
pci_dev->cmask = g_malloc0(config_size); |
776 |
pci_dev->wmask = g_malloc0(config_size); |
777 |
pci_dev->w1cmask = g_malloc0(config_size); |
778 |
pci_dev->used = g_malloc0(config_size); |
779 |
} |
780 |
|
781 |
static void pci_config_free(PCIDevice *pci_dev) |
782 |
{ |
783 |
g_free(pci_dev->config); |
784 |
g_free(pci_dev->cmask); |
785 |
g_free(pci_dev->wmask); |
786 |
g_free(pci_dev->w1cmask); |
787 |
g_free(pci_dev->used); |
788 |
} |
789 |
|
790 |
/* -1 for devfn means auto assign */
|
791 |
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
|
792 |
const char *name, int devfn) |
793 |
{ |
794 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
795 |
PCIConfigReadFunc *config_read = pc->config_read; |
796 |
PCIConfigWriteFunc *config_write = pc->config_write; |
797 |
AddressSpace *dma_as; |
798 |
|
799 |
if (devfn < 0) { |
800 |
for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
|
801 |
devfn += PCI_FUNC_MAX) { |
802 |
if (!bus->devices[devfn])
|
803 |
goto found;
|
804 |
} |
805 |
error_report("PCI: no slot/function available for %s, all in use", name);
|
806 |
return NULL; |
807 |
found: ;
|
808 |
} else if (bus->devices[devfn]) { |
809 |
error_report("PCI: slot %d function %d not available for %s, in use by %s",
|
810 |
PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); |
811 |
return NULL; |
812 |
} |
813 |
|
814 |
pci_dev->bus = bus; |
815 |
dma_as = pci_device_iommu_address_space(pci_dev); |
816 |
|
817 |
memory_region_init_alias(&pci_dev->bus_master_enable_region, |
818 |
OBJECT(pci_dev), "bus master",
|
819 |
dma_as->root, 0, memory_region_size(dma_as->root));
|
820 |
memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
|
821 |
address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, |
822 |
name); |
823 |
|
824 |
pci_dev->devfn = devfn; |
825 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
826 |
pci_dev->irq_state = 0;
|
827 |
pci_config_alloc(pci_dev); |
828 |
|
829 |
pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); |
830 |
pci_config_set_device_id(pci_dev->config, pc->device_id); |
831 |
pci_config_set_revision(pci_dev->config, pc->revision); |
832 |
pci_config_set_class(pci_dev->config, pc->class_id); |
833 |
|
834 |
if (!pc->is_bridge) {
|
835 |
if (pc->subsystem_vendor_id || pc->subsystem_id) {
|
836 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
837 |
pc->subsystem_vendor_id); |
838 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
839 |
pc->subsystem_id); |
840 |
} else {
|
841 |
pci_set_default_subsystem_id(pci_dev); |
842 |
} |
843 |
} else {
|
844 |
/* subsystem_vendor_id/subsystem_id are only for header type 0 */
|
845 |
assert(!pc->subsystem_vendor_id); |
846 |
assert(!pc->subsystem_id); |
847 |
} |
848 |
pci_init_cmask(pci_dev); |
849 |
pci_init_wmask(pci_dev); |
850 |
pci_init_w1cmask(pci_dev); |
851 |
if (pc->is_bridge) {
|
852 |
pci_init_mask_bridge(pci_dev); |
853 |
} |
854 |
if (pci_init_multifunction(bus, pci_dev)) {
|
855 |
pci_config_free(pci_dev); |
856 |
return NULL; |
857 |
} |
858 |
|
859 |
if (!config_read)
|
860 |
config_read = pci_default_read_config; |
861 |
if (!config_write)
|
862 |
config_write = pci_default_write_config; |
863 |
pci_dev->config_read = config_read; |
864 |
pci_dev->config_write = config_write; |
865 |
bus->devices[devfn] = pci_dev; |
866 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
867 |
pci_dev->version_id = 2; /* Current pci device vmstate version */ |
868 |
return pci_dev;
|
869 |
} |
870 |
|
871 |
static void do_pci_unregister_device(PCIDevice *pci_dev) |
872 |
{ |
873 |
qemu_free_irqs(pci_dev->irq); |
874 |
pci_dev->bus->devices[pci_dev->devfn] = NULL;
|
875 |
pci_config_free(pci_dev); |
876 |
|
877 |
address_space_destroy(&pci_dev->bus_master_as); |
878 |
memory_region_destroy(&pci_dev->bus_master_enable_region); |
879 |
} |
880 |
|
881 |
static void pci_unregister_io_regions(PCIDevice *pci_dev) |
882 |
{ |
883 |
PCIIORegion *r; |
884 |
int i;
|
885 |
|
886 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
887 |
r = &pci_dev->io_regions[i]; |
888 |
if (!r->size || r->addr == PCI_BAR_UNMAPPED)
|
889 |
continue;
|
890 |
memory_region_del_subregion(r->address_space, r->memory); |
891 |
} |
892 |
|
893 |
pci_unregister_vga(pci_dev); |
894 |
} |
895 |
|
896 |
static int pci_unregister_device(DeviceState *dev) |
897 |
{ |
898 |
PCIDevice *pci_dev = PCI_DEVICE(dev); |
899 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
900 |
|
901 |
pci_unregister_io_regions(pci_dev); |
902 |
pci_del_option_rom(pci_dev); |
903 |
|
904 |
if (pc->exit) {
|
905 |
pc->exit(pci_dev); |
906 |
} |
907 |
|
908 |
do_pci_unregister_device(pci_dev); |
909 |
return 0; |
910 |
} |
911 |
|
912 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
913 |
uint8_t type, MemoryRegion *memory) |
914 |
{ |
915 |
PCIIORegion *r; |
916 |
uint32_t addr; |
917 |
uint64_t wmask; |
918 |
pcibus_t size = memory_region_size(memory); |
919 |
|
920 |
assert(region_num >= 0);
|
921 |
assert(region_num < PCI_NUM_REGIONS); |
922 |
if (size & (size-1)) { |
923 |
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
924 |
"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
925 |
exit(1);
|
926 |
} |
927 |
|
928 |
r = &pci_dev->io_regions[region_num]; |
929 |
r->addr = PCI_BAR_UNMAPPED; |
930 |
r->size = size; |
931 |
r->type = type; |
932 |
r->memory = NULL;
|
933 |
|
934 |
wmask = ~(size - 1);
|
935 |
addr = pci_bar(pci_dev, region_num); |
936 |
if (region_num == PCI_ROM_SLOT) {
|
937 |
/* ROM enable bit is writable */
|
938 |
wmask |= PCI_ROM_ADDRESS_ENABLE; |
939 |
} |
940 |
pci_set_long(pci_dev->config + addr, type); |
941 |
if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
|
942 |
r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
943 |
pci_set_quad(pci_dev->wmask + addr, wmask); |
944 |
pci_set_quad(pci_dev->cmask + addr, ~0ULL);
|
945 |
} else {
|
946 |
pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
|
947 |
pci_set_long(pci_dev->cmask + addr, 0xffffffff);
|
948 |
} |
949 |
pci_dev->io_regions[region_num].memory = memory; |
950 |
pci_dev->io_regions[region_num].address_space |
951 |
= type & PCI_BASE_ADDRESS_SPACE_IO |
952 |
? pci_dev->bus->address_space_io |
953 |
: pci_dev->bus->address_space_mem; |
954 |
} |
955 |
|
956 |
static void pci_update_vga(PCIDevice *pci_dev) |
957 |
{ |
958 |
uint16_t cmd; |
959 |
|
960 |
if (!pci_dev->has_vga) {
|
961 |
return;
|
962 |
} |
963 |
|
964 |
cmd = pci_get_word(pci_dev->config + PCI_COMMAND); |
965 |
|
966 |
memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], |
967 |
cmd & PCI_COMMAND_MEMORY); |
968 |
memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], |
969 |
cmd & PCI_COMMAND_IO); |
970 |
memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], |
971 |
cmd & PCI_COMMAND_IO); |
972 |
} |
973 |
|
974 |
void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
|
975 |
MemoryRegion *io_lo, MemoryRegion *io_hi) |
976 |
{ |
977 |
assert(!pci_dev->has_vga); |
978 |
|
979 |
assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); |
980 |
pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; |
981 |
memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, |
982 |
QEMU_PCI_VGA_MEM_BASE, mem, 1);
|
983 |
|
984 |
assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); |
985 |
pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; |
986 |
memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, |
987 |
QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
|
988 |
|
989 |
assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); |
990 |
pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; |
991 |
memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, |
992 |
QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
|
993 |
pci_dev->has_vga = true;
|
994 |
|
995 |
pci_update_vga(pci_dev); |
996 |
} |
997 |
|
998 |
void pci_unregister_vga(PCIDevice *pci_dev)
|
999 |
{ |
1000 |
if (!pci_dev->has_vga) {
|
1001 |
return;
|
1002 |
} |
1003 |
|
1004 |
memory_region_del_subregion(pci_dev->bus->address_space_mem, |
1005 |
pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); |
1006 |
memory_region_del_subregion(pci_dev->bus->address_space_io, |
1007 |
pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); |
1008 |
memory_region_del_subregion(pci_dev->bus->address_space_io, |
1009 |
pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); |
1010 |
pci_dev->has_vga = false;
|
1011 |
} |
1012 |
|
1013 |
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
|
1014 |
{ |
1015 |
return pci_dev->io_regions[region_num].addr;
|
1016 |
} |
1017 |
|
1018 |
static pcibus_t pci_bar_address(PCIDevice *d,
|
1019 |
int reg, uint8_t type, pcibus_t size)
|
1020 |
{ |
1021 |
pcibus_t new_addr, last_addr; |
1022 |
int bar = pci_bar(d, reg);
|
1023 |
uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); |
1024 |
|
1025 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
1026 |
if (!(cmd & PCI_COMMAND_IO)) {
|
1027 |
return PCI_BAR_UNMAPPED;
|
1028 |
} |
1029 |
new_addr = pci_get_long(d->config + bar) & ~(size - 1);
|
1030 |
last_addr = new_addr + size - 1;
|
1031 |
/* Check if 32 bit BAR wraps around explicitly.
|
1032 |
* TODO: make priorities correct and remove this work around.
|
1033 |
*/
|
1034 |
if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) { |
1035 |
return PCI_BAR_UNMAPPED;
|
1036 |
} |
1037 |
return new_addr;
|
1038 |
} |
1039 |
|
1040 |
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
1041 |
return PCI_BAR_UNMAPPED;
|
1042 |
} |
1043 |
if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
1044 |
new_addr = pci_get_quad(d->config + bar); |
1045 |
} else {
|
1046 |
new_addr = pci_get_long(d->config + bar); |
1047 |
} |
1048 |
/* the ROM slot has a specific enable bit */
|
1049 |
if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
|
1050 |
return PCI_BAR_UNMAPPED;
|
1051 |
} |
1052 |
new_addr &= ~(size - 1);
|
1053 |
last_addr = new_addr + size - 1;
|
1054 |
/* NOTE: we do not support wrapping */
|
1055 |
/* XXX: as we cannot support really dynamic
|
1056 |
mappings, we handle specific values as invalid
|
1057 |
mappings. */
|
1058 |
if (last_addr <= new_addr || new_addr == 0 || |
1059 |
last_addr == PCI_BAR_UNMAPPED) { |
1060 |
return PCI_BAR_UNMAPPED;
|
1061 |
} |
1062 |
|
1063 |
/* Now pcibus_t is 64bit.
|
1064 |
* Check if 32 bit BAR wraps around explicitly.
|
1065 |
* Without this, PC ide doesn't work well.
|
1066 |
* TODO: remove this work around.
|
1067 |
*/
|
1068 |
if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
|
1069 |
return PCI_BAR_UNMAPPED;
|
1070 |
} |
1071 |
|
1072 |
/*
|
1073 |
* OS is allowed to set BAR beyond its addressable
|
1074 |
* bits. For example, 32 bit OS can set 64bit bar
|
1075 |
* to >4G. Check it. TODO: we might need to support
|
1076 |
* it in the future for e.g. PAE.
|
1077 |
*/
|
1078 |
if (last_addr >= HWADDR_MAX) {
|
1079 |
return PCI_BAR_UNMAPPED;
|
1080 |
} |
1081 |
|
1082 |
return new_addr;
|
1083 |
} |
1084 |
|
1085 |
static void pci_update_mappings(PCIDevice *d) |
1086 |
{ |
1087 |
PCIIORegion *r; |
1088 |
int i;
|
1089 |
pcibus_t new_addr; |
1090 |
|
1091 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
1092 |
r = &d->io_regions[i]; |
1093 |
|
1094 |
/* this region isn't registered */
|
1095 |
if (!r->size)
|
1096 |
continue;
|
1097 |
|
1098 |
new_addr = pci_bar_address(d, i, r->type, r->size); |
1099 |
|
1100 |
/* This bar isn't changed */
|
1101 |
if (new_addr == r->addr)
|
1102 |
continue;
|
1103 |
|
1104 |
/* now do the real mapping */
|
1105 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
1106 |
memory_region_del_subregion(r->address_space, r->memory); |
1107 |
} |
1108 |
r->addr = new_addr; |
1109 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
1110 |
memory_region_add_subregion_overlap(r->address_space, |
1111 |
r->addr, r->memory, 1);
|
1112 |
} |
1113 |
} |
1114 |
|
1115 |
pci_update_vga(d); |
1116 |
} |
1117 |
|
1118 |
static inline int pci_irq_disabled(PCIDevice *d) |
1119 |
{ |
1120 |
return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
|
1121 |
} |
1122 |
|
1123 |
/* Called after interrupt disabled field update in config space,
|
1124 |
* assert/deassert interrupts if necessary.
|
1125 |
* Gets original interrupt disable bit value (before update). */
|
1126 |
static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) |
1127 |
{ |
1128 |
int i, disabled = pci_irq_disabled(d);
|
1129 |
if (disabled == was_irq_disabled)
|
1130 |
return;
|
1131 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
1132 |
int state = pci_irq_state(d, i);
|
1133 |
pci_change_irq_level(d, i, disabled ? -state : state); |
1134 |
} |
1135 |
} |
1136 |
|
1137 |
uint32_t pci_default_read_config(PCIDevice *d, |
1138 |
uint32_t address, int len)
|
1139 |
{ |
1140 |
uint32_t val = 0;
|
1141 |
|
1142 |
memcpy(&val, d->config + address, len); |
1143 |
return le32_to_cpu(val);
|
1144 |
} |
1145 |
|
1146 |
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
1147 |
{ |
1148 |
int i, was_irq_disabled = pci_irq_disabled(d);
|
1149 |
|
1150 |
for (i = 0; i < l; val >>= 8, ++i) { |
1151 |
uint8_t wmask = d->wmask[addr + i]; |
1152 |
uint8_t w1cmask = d->w1cmask[addr + i]; |
1153 |
assert(!(wmask & w1cmask)); |
1154 |
d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
1155 |
d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
|
1156 |
} |
1157 |
if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
1158 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
|
1159 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
|
1160 |
range_covers_byte(addr, l, PCI_COMMAND)) |
1161 |
pci_update_mappings(d); |
1162 |
|
1163 |
if (range_covers_byte(addr, l, PCI_COMMAND)) {
|
1164 |
pci_update_irq_disabled(d, was_irq_disabled); |
1165 |
memory_region_set_enabled(&d->bus_master_enable_region, |
1166 |
pci_get_word(d->config + PCI_COMMAND) |
1167 |
& PCI_COMMAND_MASTER); |
1168 |
} |
1169 |
|
1170 |
msi_write_config(d, addr, val, l); |
1171 |
msix_write_config(d, addr, val, l); |
1172 |
} |
1173 |
|
1174 |
/***********************************************************/
|
1175 |
/* generic PCI irq support */
|
1176 |
|
1177 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
1178 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
1179 |
{ |
1180 |
PCIDevice *pci_dev = opaque; |
1181 |
int change;
|
1182 |
|
1183 |
change = level - pci_irq_state(pci_dev, irq_num); |
1184 |
if (!change)
|
1185 |
return;
|
1186 |
|
1187 |
pci_set_irq_state(pci_dev, irq_num, level); |
1188 |
pci_update_irq_status(pci_dev); |
1189 |
if (pci_irq_disabled(pci_dev))
|
1190 |
return;
|
1191 |
pci_change_irq_level(pci_dev, irq_num, change); |
1192 |
} |
1193 |
|
1194 |
/* Special hooks used by device assignment */
|
1195 |
void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
|
1196 |
{ |
1197 |
assert(pci_bus_is_root(bus)); |
1198 |
bus->route_intx_to_irq = route_intx_to_irq; |
1199 |
} |
1200 |
|
1201 |
PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
|
1202 |
{ |
1203 |
PCIBus *bus; |
1204 |
|
1205 |
do {
|
1206 |
bus = dev->bus; |
1207 |
pin = bus->map_irq(dev, pin); |
1208 |
dev = bus->parent_dev; |
1209 |
} while (dev);
|
1210 |
|
1211 |
if (!bus->route_intx_to_irq) {
|
1212 |
error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
|
1213 |
object_get_typename(OBJECT(bus->qbus.parent))); |
1214 |
return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; |
1215 |
} |
1216 |
|
1217 |
return bus->route_intx_to_irq(bus->irq_opaque, pin);
|
1218 |
} |
1219 |
|
1220 |
bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
|
1221 |
{ |
1222 |
return old->mode != new->mode || old->irq != new->irq;
|
1223 |
} |
1224 |
|
1225 |
void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
|
1226 |
{ |
1227 |
PCIDevice *dev; |
1228 |
PCIBus *sec; |
1229 |
int i;
|
1230 |
|
1231 |
for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
1232 |
dev = bus->devices[i]; |
1233 |
if (dev && dev->intx_routing_notifier) {
|
1234 |
dev->intx_routing_notifier(dev); |
1235 |
} |
1236 |
} |
1237 |
|
1238 |
QLIST_FOREACH(sec, &bus->child, sibling) { |
1239 |
pci_bus_fire_intx_routing_notifier(sec); |
1240 |
} |
1241 |
} |
1242 |
|
1243 |
void pci_device_set_intx_routing_notifier(PCIDevice *dev,
|
1244 |
PCIINTxRoutingNotifier notifier) |
1245 |
{ |
1246 |
dev->intx_routing_notifier = notifier; |
1247 |
} |
1248 |
|
1249 |
/*
|
1250 |
* PCI-to-PCI bridge specification
|
1251 |
* 9.1: Interrupt routing. Table 9-1
|
1252 |
*
|
1253 |
* the PCI Express Base Specification, Revision 2.1
|
1254 |
* 2.2.8.1: INTx interrutp signaling - Rules
|
1255 |
* the Implementation Note
|
1256 |
* Table 2-20
|
1257 |
*/
|
1258 |
/*
|
1259 |
* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
|
1260 |
* 0-origin unlike PCI interrupt pin register.
|
1261 |
*/
|
1262 |
int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) |
1263 |
{ |
1264 |
return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
|
1265 |
} |
1266 |
|
1267 |
/***********************************************************/
|
1268 |
/* monitor info on PCI */
|
1269 |
|
1270 |
typedef struct { |
1271 |
uint16_t class; |
1272 |
const char *desc; |
1273 |
const char *fw_name; |
1274 |
uint16_t fw_ign_bits; |
1275 |
} pci_class_desc; |
1276 |
|
1277 |
static const pci_class_desc pci_class_descriptions[] = |
1278 |
{ |
1279 |
{ 0x0001, "VGA controller", "display"}, |
1280 |
{ 0x0100, "SCSI controller", "scsi"}, |
1281 |
{ 0x0101, "IDE controller", "ide"}, |
1282 |
{ 0x0102, "Floppy controller", "fdc"}, |
1283 |
{ 0x0103, "IPI controller", "ipi"}, |
1284 |
{ 0x0104, "RAID controller", "raid"}, |
1285 |
{ 0x0106, "SATA controller"}, |
1286 |
{ 0x0107, "SAS controller"}, |
1287 |
{ 0x0180, "Storage controller"}, |
1288 |
{ 0x0200, "Ethernet controller", "ethernet"}, |
1289 |
{ 0x0201, "Token Ring controller", "token-ring"}, |
1290 |
{ 0x0202, "FDDI controller", "fddi"}, |
1291 |
{ 0x0203, "ATM controller", "atm"}, |
1292 |
{ 0x0280, "Network controller"}, |
1293 |
{ 0x0300, "VGA controller", "display", 0x00ff}, |
1294 |
{ 0x0301, "XGA controller"}, |
1295 |
{ 0x0302, "3D controller"}, |
1296 |
{ 0x0380, "Display controller"}, |
1297 |
{ 0x0400, "Video controller", "video"}, |
1298 |
{ 0x0401, "Audio controller", "sound"}, |
1299 |
{ 0x0402, "Phone"}, |
1300 |
{ 0x0403, "Audio controller", "sound"}, |
1301 |
{ 0x0480, "Multimedia controller"}, |
1302 |
{ 0x0500, "RAM controller", "memory"}, |
1303 |
{ 0x0501, "Flash controller", "flash"}, |
1304 |
{ 0x0580, "Memory controller"}, |
1305 |
{ 0x0600, "Host bridge", "host"}, |
1306 |
{ 0x0601, "ISA bridge", "isa"}, |
1307 |
{ 0x0602, "EISA bridge", "eisa"}, |
1308 |
{ 0x0603, "MC bridge", "mca"}, |
1309 |
{ 0x0604, "PCI bridge", "pci"}, |
1310 |
{ 0x0605, "PCMCIA bridge", "pcmcia"}, |
1311 |
{ 0x0606, "NUBUS bridge", "nubus"}, |
1312 |
{ 0x0607, "CARDBUS bridge", "cardbus"}, |
1313 |
{ 0x0608, "RACEWAY bridge"}, |
1314 |
{ 0x0680, "Bridge"}, |
1315 |
{ 0x0700, "Serial port", "serial"}, |
1316 |
{ 0x0701, "Parallel port", "parallel"}, |
1317 |
{ 0x0800, "Interrupt controller", "interrupt-controller"}, |
1318 |
{ 0x0801, "DMA controller", "dma-controller"}, |
1319 |
{ 0x0802, "Timer", "timer"}, |
1320 |
{ 0x0803, "RTC", "rtc"}, |
1321 |
{ 0x0900, "Keyboard", "keyboard"}, |
1322 |
{ 0x0901, "Pen", "pen"}, |
1323 |
{ 0x0902, "Mouse", "mouse"}, |
1324 |
{ 0x0A00, "Dock station", "dock", 0x00ff}, |
1325 |
{ 0x0B00, "i386 cpu", "cpu", 0x00ff}, |
1326 |
{ 0x0c00, "Fireware contorller", "fireware"}, |
1327 |
{ 0x0c01, "Access bus controller", "access-bus"}, |
1328 |
{ 0x0c02, "SSA controller", "ssa"}, |
1329 |
{ 0x0c03, "USB controller", "usb"}, |
1330 |
{ 0x0c04, "Fibre channel controller", "fibre-channel"}, |
1331 |
{ 0x0c05, "SMBus"}, |
1332 |
{ 0, NULL} |
1333 |
}; |
1334 |
|
1335 |
static void pci_for_each_device_under_bus(PCIBus *bus, |
1336 |
void (*fn)(PCIBus *b, PCIDevice *d,
|
1337 |
void *opaque),
|
1338 |
void *opaque)
|
1339 |
{ |
1340 |
PCIDevice *d; |
1341 |
int devfn;
|
1342 |
|
1343 |
for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1344 |
d = bus->devices[devfn]; |
1345 |
if (d) {
|
1346 |
fn(bus, d, opaque); |
1347 |
} |
1348 |
} |
1349 |
} |
1350 |
|
1351 |
void pci_for_each_device(PCIBus *bus, int bus_num, |
1352 |
void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), |
1353 |
void *opaque)
|
1354 |
{ |
1355 |
bus = pci_find_bus_nr(bus, bus_num); |
1356 |
|
1357 |
if (bus) {
|
1358 |
pci_for_each_device_under_bus(bus, fn, opaque); |
1359 |
} |
1360 |
} |
1361 |
|
1362 |
static const pci_class_desc *get_class_desc(int class) |
1363 |
{ |
1364 |
const pci_class_desc *desc;
|
1365 |
|
1366 |
desc = pci_class_descriptions; |
1367 |
while (desc->desc && class != desc->class) {
|
1368 |
desc++; |
1369 |
} |
1370 |
|
1371 |
return desc;
|
1372 |
} |
1373 |
|
1374 |
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); |
1375 |
|
1376 |
static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) |
1377 |
{ |
1378 |
PciMemoryRegionList *head = NULL, *cur_item = NULL; |
1379 |
int i;
|
1380 |
|
1381 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1382 |
const PCIIORegion *r = &dev->io_regions[i];
|
1383 |
PciMemoryRegionList *region; |
1384 |
|
1385 |
if (!r->size) {
|
1386 |
continue;
|
1387 |
} |
1388 |
|
1389 |
region = g_malloc0(sizeof(*region));
|
1390 |
region->value = g_malloc0(sizeof(*region->value));
|
1391 |
|
1392 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
1393 |
region->value->type = g_strdup("io");
|
1394 |
} else {
|
1395 |
region->value->type = g_strdup("memory");
|
1396 |
region->value->has_prefetch = true;
|
1397 |
region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); |
1398 |
region->value->has_mem_type_64 = true;
|
1399 |
region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); |
1400 |
} |
1401 |
|
1402 |
region->value->bar = i; |
1403 |
region->value->address = r->addr; |
1404 |
region->value->size = r->size; |
1405 |
|
1406 |
/* XXX: waiting for the qapi to support GSList */
|
1407 |
if (!cur_item) {
|
1408 |
head = cur_item = region; |
1409 |
} else {
|
1410 |
cur_item->next = region; |
1411 |
cur_item = region; |
1412 |
} |
1413 |
} |
1414 |
|
1415 |
return head;
|
1416 |
} |
1417 |
|
1418 |
static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
|
1419 |
int bus_num)
|
1420 |
{ |
1421 |
PciBridgeInfo *info; |
1422 |
|
1423 |
info = g_malloc0(sizeof(*info));
|
1424 |
|
1425 |
info->bus.number = dev->config[PCI_PRIMARY_BUS]; |
1426 |
info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; |
1427 |
info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; |
1428 |
|
1429 |
info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
|
1430 |
info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); |
1431 |
info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); |
1432 |
|
1433 |
info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
|
1434 |
info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); |
1435 |
info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); |
1436 |
|
1437 |
info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
|
1438 |
info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
1439 |
info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
1440 |
|
1441 |
if (dev->config[PCI_SECONDARY_BUS] != 0) { |
1442 |
PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); |
1443 |
if (child_bus) {
|
1444 |
info->has_devices = true;
|
1445 |
info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); |
1446 |
} |
1447 |
} |
1448 |
|
1449 |
return info;
|
1450 |
} |
1451 |
|
1452 |
static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
|
1453 |
int bus_num)
|
1454 |
{ |
1455 |
const pci_class_desc *desc;
|
1456 |
PciDeviceInfo *info; |
1457 |
uint8_t type; |
1458 |
int class;
|
1459 |
|
1460 |
info = g_malloc0(sizeof(*info));
|
1461 |
info->bus = bus_num; |
1462 |
info->slot = PCI_SLOT(dev->devfn); |
1463 |
info->function = PCI_FUNC(dev->devfn); |
1464 |
|
1465 |
class = pci_get_word(dev->config + PCI_CLASS_DEVICE); |
1466 |
info->class_info.q_class = class; |
1467 |
desc = get_class_desc(class); |
1468 |
if (desc->desc) {
|
1469 |
info->class_info.has_desc = true;
|
1470 |
info->class_info.desc = g_strdup(desc->desc); |
1471 |
} |
1472 |
|
1473 |
info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); |
1474 |
info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); |
1475 |
info->regions = qmp_query_pci_regions(dev); |
1476 |
info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
|
1477 |
|
1478 |
if (dev->config[PCI_INTERRUPT_PIN] != 0) { |
1479 |
info->has_irq = true;
|
1480 |
info->irq = dev->config[PCI_INTERRUPT_LINE]; |
1481 |
} |
1482 |
|
1483 |
type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1484 |
if (type == PCI_HEADER_TYPE_BRIDGE) {
|
1485 |
info->has_pci_bridge = true;
|
1486 |
info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); |
1487 |
} |
1488 |
|
1489 |
return info;
|
1490 |
} |
1491 |
|
1492 |
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) |
1493 |
{ |
1494 |
PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; |
1495 |
PCIDevice *dev; |
1496 |
int devfn;
|
1497 |
|
1498 |
for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1499 |
dev = bus->devices[devfn]; |
1500 |
if (dev) {
|
1501 |
info = g_malloc0(sizeof(*info));
|
1502 |
info->value = qmp_query_pci_device(dev, bus, bus_num); |
1503 |
|
1504 |
/* XXX: waiting for the qapi to support GSList */
|
1505 |
if (!cur_item) {
|
1506 |
head = cur_item = info; |
1507 |
} else {
|
1508 |
cur_item->next = info; |
1509 |
cur_item = info; |
1510 |
} |
1511 |
} |
1512 |
} |
1513 |
|
1514 |
return head;
|
1515 |
} |
1516 |
|
1517 |
static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) |
1518 |
{ |
1519 |
PciInfo *info = NULL;
|
1520 |
|
1521 |
bus = pci_find_bus_nr(bus, bus_num); |
1522 |
if (bus) {
|
1523 |
info = g_malloc0(sizeof(*info));
|
1524 |
info->bus = bus_num; |
1525 |
info->devices = qmp_query_pci_devices(bus, bus_num); |
1526 |
} |
1527 |
|
1528 |
return info;
|
1529 |
} |
1530 |
|
1531 |
PciInfoList *qmp_query_pci(Error **errp) |
1532 |
{ |
1533 |
PciInfoList *info, *head = NULL, *cur_item = NULL; |
1534 |
PCIHostState *host_bridge; |
1535 |
|
1536 |
QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
1537 |
info = g_malloc0(sizeof(*info));
|
1538 |
info->value = qmp_query_pci_bus(host_bridge->bus, 0);
|
1539 |
|
1540 |
/* XXX: waiting for the qapi to support GSList */
|
1541 |
if (!cur_item) {
|
1542 |
head = cur_item = info; |
1543 |
} else {
|
1544 |
cur_item->next = info; |
1545 |
cur_item = info; |
1546 |
} |
1547 |
} |
1548 |
|
1549 |
return head;
|
1550 |
} |
1551 |
|
1552 |
static const char * const pci_nic_models[] = { |
1553 |
"ne2k_pci",
|
1554 |
"i82551",
|
1555 |
"i82557b",
|
1556 |
"i82559er",
|
1557 |
"rtl8139",
|
1558 |
"e1000",
|
1559 |
"pcnet",
|
1560 |
"virtio",
|
1561 |
NULL
|
1562 |
}; |
1563 |
|
1564 |
static const char * const pci_nic_names[] = { |
1565 |
"ne2k_pci",
|
1566 |
"i82551",
|
1567 |
"i82557b",
|
1568 |
"i82559er",
|
1569 |
"rtl8139",
|
1570 |
"e1000",
|
1571 |
"pcnet",
|
1572 |
"virtio-net-pci",
|
1573 |
NULL
|
1574 |
}; |
1575 |
|
1576 |
/* Initialize a PCI NIC. */
|
1577 |
/* FIXME callers should check for failure, but don't */
|
1578 |
PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, |
1579 |
const char *default_model, |
1580 |
const char *default_devaddr) |
1581 |
{ |
1582 |
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
1583 |
PCIBus *bus; |
1584 |
int devfn;
|
1585 |
PCIDevice *pci_dev; |
1586 |
DeviceState *dev; |
1587 |
int i;
|
1588 |
|
1589 |
i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1590 |
if (i < 0) |
1591 |
return NULL; |
1592 |
|
1593 |
bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); |
1594 |
if (!bus) {
|
1595 |
error_report("Invalid PCI device address %s for device %s",
|
1596 |
devaddr, pci_nic_names[i]); |
1597 |
return NULL; |
1598 |
} |
1599 |
|
1600 |
pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
1601 |
dev = &pci_dev->qdev; |
1602 |
qdev_set_nic_properties(dev, nd); |
1603 |
if (qdev_init(dev) < 0) |
1604 |
return NULL; |
1605 |
return pci_dev;
|
1606 |
} |
1607 |
|
1608 |
PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, |
1609 |
const char *default_model, |
1610 |
const char *default_devaddr) |
1611 |
{ |
1612 |
PCIDevice *res; |
1613 |
|
1614 |
if (qemu_show_nic_models(nd->model, pci_nic_models))
|
1615 |
exit(0);
|
1616 |
|
1617 |
res = pci_nic_init(nd, rootbus, default_model, default_devaddr); |
1618 |
if (!res)
|
1619 |
exit(1);
|
1620 |
return res;
|
1621 |
} |
1622 |
|
1623 |
PCIDevice *pci_vga_init(PCIBus *bus) |
1624 |
{ |
1625 |
switch (vga_interface_type) {
|
1626 |
case VGA_CIRRUS:
|
1627 |
return pci_create_simple(bus, -1, "cirrus-vga"); |
1628 |
case VGA_QXL:
|
1629 |
return pci_create_simple(bus, -1, "qxl-vga"); |
1630 |
case VGA_STD:
|
1631 |
return pci_create_simple(bus, -1, "VGA"); |
1632 |
case VGA_VMWARE:
|
1633 |
return pci_create_simple(bus, -1, "vmware-svga"); |
1634 |
case VGA_NONE:
|
1635 |
default: /* Other non-PCI types. Checking for unsupported types is already |
1636 |
done in vl.c. */
|
1637 |
return NULL; |
1638 |
} |
1639 |
} |
1640 |
|
1641 |
/* Whether a given bus number is in range of the secondary
|
1642 |
* bus of the given bridge device. */
|
1643 |
static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) |
1644 |
{ |
1645 |
return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
|
1646 |
PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
|
1647 |
dev->config[PCI_SECONDARY_BUS] < bus_num && |
1648 |
bus_num <= dev->config[PCI_SUBORDINATE_BUS]; |
1649 |
} |
1650 |
|
1651 |
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) |
1652 |
{ |
1653 |
PCIBus *sec; |
1654 |
|
1655 |
if (!bus) {
|
1656 |
return NULL; |
1657 |
} |
1658 |
|
1659 |
if (pci_bus_num(bus) == bus_num) {
|
1660 |
return bus;
|
1661 |
} |
1662 |
|
1663 |
/* Consider all bus numbers in range for the host pci bridge. */
|
1664 |
if (!pci_bus_is_root(bus) &&
|
1665 |
!pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { |
1666 |
return NULL; |
1667 |
} |
1668 |
|
1669 |
/* try child bus */
|
1670 |
for (; bus; bus = sec) {
|
1671 |
QLIST_FOREACH(sec, &bus->child, sibling) { |
1672 |
assert(!pci_bus_is_root(sec)); |
1673 |
if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
|
1674 |
return sec;
|
1675 |
} |
1676 |
if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
|
1677 |
break;
|
1678 |
} |
1679 |
} |
1680 |
} |
1681 |
|
1682 |
return NULL; |
1683 |
} |
1684 |
|
1685 |
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
|
1686 |
{ |
1687 |
bus = pci_find_bus_nr(bus, bus_num); |
1688 |
|
1689 |
if (!bus)
|
1690 |
return NULL; |
1691 |
|
1692 |
return bus->devices[devfn];
|
1693 |
} |
1694 |
|
1695 |
static int pci_qdev_init(DeviceState *qdev) |
1696 |
{ |
1697 |
PCIDevice *pci_dev = (PCIDevice *)qdev; |
1698 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
1699 |
PCIBus *bus; |
1700 |
int rc;
|
1701 |
bool is_default_rom;
|
1702 |
|
1703 |
/* initialize cap_present for pci_is_express() and pci_config_size() */
|
1704 |
if (pc->is_express) {
|
1705 |
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
1706 |
} |
1707 |
|
1708 |
bus = PCI_BUS(qdev_get_parent_bus(qdev)); |
1709 |
pci_dev = do_pci_register_device(pci_dev, bus, |
1710 |
object_get_typename(OBJECT(qdev)), |
1711 |
pci_dev->devfn); |
1712 |
if (pci_dev == NULL) |
1713 |
return -1; |
1714 |
if (qdev->hotplugged && pc->no_hotplug) {
|
1715 |
qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); |
1716 |
do_pci_unregister_device(pci_dev); |
1717 |
return -1; |
1718 |
} |
1719 |
if (pc->init) {
|
1720 |
rc = pc->init(pci_dev); |
1721 |
if (rc != 0) { |
1722 |
do_pci_unregister_device(pci_dev); |
1723 |
return rc;
|
1724 |
} |
1725 |
} |
1726 |
|
1727 |
/* rom loading */
|
1728 |
is_default_rom = false;
|
1729 |
if (pci_dev->romfile == NULL && pc->romfile != NULL) { |
1730 |
pci_dev->romfile = g_strdup(pc->romfile); |
1731 |
is_default_rom = true;
|
1732 |
} |
1733 |
pci_add_option_rom(pci_dev, is_default_rom); |
1734 |
|
1735 |
if (bus->hotplug) {
|
1736 |
/* Let buses differentiate between hotplug and when device is
|
1737 |
* enabled during qemu machine creation. */
|
1738 |
rc = bus->hotplug(bus->hotplug_qdev, pci_dev, |
1739 |
qdev->hotplugged ? PCI_HOTPLUG_ENABLED: |
1740 |
PCI_COLDPLUG_ENABLED); |
1741 |
if (rc != 0) { |
1742 |
int r = pci_unregister_device(&pci_dev->qdev);
|
1743 |
assert(!r); |
1744 |
return rc;
|
1745 |
} |
1746 |
} |
1747 |
return 0; |
1748 |
} |
1749 |
|
1750 |
static int pci_unplug_device(DeviceState *qdev) |
1751 |
{ |
1752 |
PCIDevice *dev = PCI_DEVICE(qdev); |
1753 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
1754 |
|
1755 |
if (pc->no_hotplug) {
|
1756 |
qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); |
1757 |
return -1; |
1758 |
} |
1759 |
return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
|
1760 |
PCI_HOTPLUG_DISABLED); |
1761 |
} |
1762 |
|
1763 |
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
1764 |
const char *name) |
1765 |
{ |
1766 |
DeviceState *dev; |
1767 |
|
1768 |
dev = qdev_create(&bus->qbus, name); |
1769 |
qdev_prop_set_int32(dev, "addr", devfn);
|
1770 |
qdev_prop_set_bit(dev, "multifunction", multifunction);
|
1771 |
return PCI_DEVICE(dev);
|
1772 |
} |
1773 |
|
1774 |
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
1775 |
bool multifunction,
|
1776 |
const char *name) |
1777 |
{ |
1778 |
PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
1779 |
qdev_init_nofail(&dev->qdev); |
1780 |
return dev;
|
1781 |
} |
1782 |
|
1783 |
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1784 |
{ |
1785 |
return pci_create_multifunction(bus, devfn, false, name); |
1786 |
} |
1787 |
|
1788 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
1789 |
{ |
1790 |
return pci_create_simple_multifunction(bus, devfn, false, name); |
1791 |
} |
1792 |
|
1793 |
static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
|
1794 |
{ |
1795 |
int offset = PCI_CONFIG_HEADER_SIZE;
|
1796 |
int i;
|
1797 |
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
|
1798 |
if (pdev->used[i])
|
1799 |
offset = i + 1;
|
1800 |
else if (i - offset + 1 == size) |
1801 |
return offset;
|
1802 |
} |
1803 |
return 0; |
1804 |
} |
1805 |
|
1806 |
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
1807 |
uint8_t *prev_p) |
1808 |
{ |
1809 |
uint8_t next, prev; |
1810 |
|
1811 |
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
1812 |
return 0; |
1813 |
|
1814 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
1815 |
prev = next + PCI_CAP_LIST_NEXT) |
1816 |
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
1817 |
break;
|
1818 |
|
1819 |
if (prev_p)
|
1820 |
*prev_p = prev; |
1821 |
return next;
|
1822 |
} |
1823 |
|
1824 |
static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
|
1825 |
{ |
1826 |
uint8_t next, prev, found = 0;
|
1827 |
|
1828 |
if (!(pdev->used[offset])) {
|
1829 |
return 0; |
1830 |
} |
1831 |
|
1832 |
assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); |
1833 |
|
1834 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
1835 |
prev = next + PCI_CAP_LIST_NEXT) { |
1836 |
if (next <= offset && next > found) {
|
1837 |
found = next; |
1838 |
} |
1839 |
} |
1840 |
return found;
|
1841 |
} |
1842 |
|
1843 |
/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
|
1844 |
This is needed for an option rom which is used for more than one device. */
|
1845 |
static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) |
1846 |
{ |
1847 |
uint16_t vendor_id; |
1848 |
uint16_t device_id; |
1849 |
uint16_t rom_vendor_id; |
1850 |
uint16_t rom_device_id; |
1851 |
uint16_t rom_magic; |
1852 |
uint16_t pcir_offset; |
1853 |
uint8_t checksum; |
1854 |
|
1855 |
/* Words in rom data are little endian (like in PCI configuration),
|
1856 |
so they can be read / written with pci_get_word / pci_set_word. */
|
1857 |
|
1858 |
/* Only a valid rom will be patched. */
|
1859 |
rom_magic = pci_get_word(ptr); |
1860 |
if (rom_magic != 0xaa55) { |
1861 |
PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
|
1862 |
return;
|
1863 |
} |
1864 |
pcir_offset = pci_get_word(ptr + 0x18);
|
1865 |
if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { |
1866 |
PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
|
1867 |
return;
|
1868 |
} |
1869 |
|
1870 |
vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); |
1871 |
device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); |
1872 |
rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
|
1873 |
rom_device_id = pci_get_word(ptr + pcir_offset + 6);
|
1874 |
|
1875 |
PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
|
1876 |
vendor_id, device_id, rom_vendor_id, rom_device_id); |
1877 |
|
1878 |
checksum = ptr[6];
|
1879 |
|
1880 |
if (vendor_id != rom_vendor_id) {
|
1881 |
/* Patch vendor id and checksum (at offset 6 for etherboot roms). */
|
1882 |
checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
|
1883 |
checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
|
1884 |
PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); |
1885 |
ptr[6] = checksum;
|
1886 |
pci_set_word(ptr + pcir_offset + 4, vendor_id);
|
1887 |
} |
1888 |
|
1889 |
if (device_id != rom_device_id) {
|
1890 |
/* Patch device id and checksum (at offset 6 for etherboot roms). */
|
1891 |
checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
|
1892 |
checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
|
1893 |
PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); |
1894 |
ptr[6] = checksum;
|
1895 |
pci_set_word(ptr + pcir_offset + 6, device_id);
|
1896 |
} |
1897 |
} |
1898 |
|
1899 |
/* Add an option rom for the device */
|
1900 |
static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) |
1901 |
{ |
1902 |
int size;
|
1903 |
char *path;
|
1904 |
void *ptr;
|
1905 |
char name[32]; |
1906 |
const VMStateDescription *vmsd;
|
1907 |
|
1908 |
if (!pdev->romfile)
|
1909 |
return 0; |
1910 |
if (strlen(pdev->romfile) == 0) |
1911 |
return 0; |
1912 |
|
1913 |
if (!pdev->rom_bar) {
|
1914 |
/*
|
1915 |
* Load rom via fw_cfg instead of creating a rom bar,
|
1916 |
* for 0.11 compatibility.
|
1917 |
*/
|
1918 |
int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
|
1919 |
if (class == 0x0300) { |
1920 |
rom_add_vga(pdev->romfile); |
1921 |
} else {
|
1922 |
rom_add_option(pdev->romfile, -1);
|
1923 |
} |
1924 |
return 0; |
1925 |
} |
1926 |
|
1927 |
path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
1928 |
if (path == NULL) { |
1929 |
path = g_strdup(pdev->romfile); |
1930 |
} |
1931 |
|
1932 |
size = get_image_size(path); |
1933 |
if (size < 0) { |
1934 |
error_report("%s: failed to find romfile \"%s\"",
|
1935 |
__func__, pdev->romfile); |
1936 |
g_free(path); |
1937 |
return -1; |
1938 |
} else if (size == 0) { |
1939 |
error_report("%s: ignoring empty romfile \"%s\"",
|
1940 |
__func__, pdev->romfile); |
1941 |
g_free(path); |
1942 |
return -1; |
1943 |
} |
1944 |
if (size & (size - 1)) { |
1945 |
size = 1 << qemu_fls(size);
|
1946 |
} |
1947 |
|
1948 |
vmsd = qdev_get_vmsd(DEVICE(pdev)); |
1949 |
|
1950 |
if (vmsd) {
|
1951 |
snprintf(name, sizeof(name), "%s.rom", vmsd->name); |
1952 |
} else {
|
1953 |
snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); |
1954 |
} |
1955 |
pdev->has_rom = true;
|
1956 |
memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size); |
1957 |
vmstate_register_ram(&pdev->rom, &pdev->qdev); |
1958 |
ptr = memory_region_get_ram_ptr(&pdev->rom); |
1959 |
load_image(path, ptr); |
1960 |
g_free(path); |
1961 |
|
1962 |
if (is_default_rom) {
|
1963 |
/* Only the default rom images will be patched (if needed). */
|
1964 |
pci_patch_ids(pdev, ptr, size); |
1965 |
} |
1966 |
|
1967 |
pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
|
1968 |
|
1969 |
return 0; |
1970 |
} |
1971 |
|
1972 |
static void pci_del_option_rom(PCIDevice *pdev) |
1973 |
{ |
1974 |
if (!pdev->has_rom)
|
1975 |
return;
|
1976 |
|
1977 |
vmstate_unregister_ram(&pdev->rom, &pdev->qdev); |
1978 |
memory_region_destroy(&pdev->rom); |
1979 |
pdev->has_rom = false;
|
1980 |
} |
1981 |
|
1982 |
/*
|
1983 |
* if !offset
|
1984 |
* Reserve space and add capability to the linked list in pci config space
|
1985 |
*
|
1986 |
* if offset = 0,
|
1987 |
* Find and reserve space and add capability to the linked list
|
1988 |
* in pci config space */
|
1989 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
1990 |
uint8_t offset, uint8_t size) |
1991 |
{ |
1992 |
uint8_t *config; |
1993 |
int i, overlapping_cap;
|
1994 |
|
1995 |
if (!offset) {
|
1996 |
offset = pci_find_space(pdev, size); |
1997 |
if (!offset) {
|
1998 |
return -ENOSPC;
|
1999 |
} |
2000 |
} else {
|
2001 |
/* Verify that capabilities don't overlap. Note: device assignment
|
2002 |
* depends on this check to verify that the device is not broken.
|
2003 |
* Should never trigger for emulated devices, but it's helpful
|
2004 |
* for debugging these. */
|
2005 |
for (i = offset; i < offset + size; i++) {
|
2006 |
overlapping_cap = pci_find_capability_at_offset(pdev, i); |
2007 |
if (overlapping_cap) {
|
2008 |
fprintf(stderr, "ERROR: %s:%02x:%02x.%x "
|
2009 |
"Attempt to add PCI capability %x at offset "
|
2010 |
"%x overlaps existing capability %x at offset %x\n",
|
2011 |
pci_root_bus_path(pdev), pci_bus_num(pdev->bus), |
2012 |
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
2013 |
cap_id, offset, overlapping_cap, i); |
2014 |
return -EINVAL;
|
2015 |
} |
2016 |
} |
2017 |
} |
2018 |
|
2019 |
config = pdev->config + offset; |
2020 |
config[PCI_CAP_LIST_ID] = cap_id; |
2021 |
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
2022 |
pdev->config[PCI_CAPABILITY_LIST] = offset; |
2023 |
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
2024 |
memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); |
2025 |
/* Make capability read-only by default */
|
2026 |
memset(pdev->wmask + offset, 0, size);
|
2027 |
/* Check capability by default */
|
2028 |
memset(pdev->cmask + offset, 0xFF, size);
|
2029 |
return offset;
|
2030 |
} |
2031 |
|
2032 |
/* Unlink capability from the pci config space. */
|
2033 |
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
2034 |
{ |
2035 |
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
2036 |
if (!offset)
|
2037 |
return;
|
2038 |
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
2039 |
/* Make capability writable again */
|
2040 |
memset(pdev->wmask + offset, 0xff, size);
|
2041 |
memset(pdev->w1cmask + offset, 0, size);
|
2042 |
/* Clear cmask as device-specific registers can't be checked */
|
2043 |
memset(pdev->cmask + offset, 0, size);
|
2044 |
memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); |
2045 |
|
2046 |
if (!pdev->config[PCI_CAPABILITY_LIST])
|
2047 |
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
2048 |
} |
2049 |
|
2050 |
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
2051 |
{ |
2052 |
return pci_find_capability_list(pdev, cap_id, NULL); |
2053 |
} |
2054 |
|
2055 |
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) |
2056 |
{ |
2057 |
PCIDevice *d = (PCIDevice *)dev; |
2058 |
const pci_class_desc *desc;
|
2059 |
char ctxt[64]; |
2060 |
PCIIORegion *r; |
2061 |
int i, class;
|
2062 |
|
2063 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
2064 |
desc = pci_class_descriptions; |
2065 |
while (desc->desc && class != desc->class)
|
2066 |
desc++; |
2067 |
if (desc->desc) {
|
2068 |
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); |
2069 |
} else {
|
2070 |
snprintf(ctxt, sizeof(ctxt), "Class %04x", class); |
2071 |
} |
2072 |
|
2073 |
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
2074 |
"pci id %04x:%04x (sub %04x:%04x)\n",
|
2075 |
indent, "", ctxt, pci_bus_num(d->bus),
|
2076 |
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
2077 |
pci_get_word(d->config + PCI_VENDOR_ID), |
2078 |
pci_get_word(d->config + PCI_DEVICE_ID), |
2079 |
pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), |
2080 |
pci_get_word(d->config + PCI_SUBSYSTEM_ID)); |
2081 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
2082 |
r = &d->io_regions[i]; |
2083 |
if (!r->size)
|
2084 |
continue;
|
2085 |
monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
|
2086 |
" [0x%"FMT_PCIBUS"]\n", |
2087 |
indent, "",
|
2088 |
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
2089 |
r->addr, r->addr + r->size - 1);
|
2090 |
} |
2091 |
} |
2092 |
|
2093 |
static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) |
2094 |
{ |
2095 |
PCIDevice *d = (PCIDevice *)dev; |
2096 |
const char *name = NULL; |
2097 |
const pci_class_desc *desc = pci_class_descriptions;
|
2098 |
int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
|
2099 |
|
2100 |
while (desc->desc &&
|
2101 |
(class & ~desc->fw_ign_bits) != |
2102 |
(desc->class & ~desc->fw_ign_bits)) { |
2103 |
desc++; |
2104 |
} |
2105 |
|
2106 |
if (desc->desc) {
|
2107 |
name = desc->fw_name; |
2108 |
} |
2109 |
|
2110 |
if (name) {
|
2111 |
pstrcpy(buf, len, name); |
2112 |
} else {
|
2113 |
snprintf(buf, len, "pci%04x,%04x",
|
2114 |
pci_get_word(d->config + PCI_VENDOR_ID), |
2115 |
pci_get_word(d->config + PCI_DEVICE_ID)); |
2116 |
} |
2117 |
|
2118 |
return buf;
|
2119 |
} |
2120 |
|
2121 |
static char *pcibus_get_fw_dev_path(DeviceState *dev) |
2122 |
{ |
2123 |
PCIDevice *d = (PCIDevice *)dev; |
2124 |
char path[50], name[33]; |
2125 |
int off;
|
2126 |
|
2127 |
off = snprintf(path, sizeof(path), "%s@%x", |
2128 |
pci_dev_fw_name(dev, name, sizeof name),
|
2129 |
PCI_SLOT(d->devfn)); |
2130 |
if (PCI_FUNC(d->devfn))
|
2131 |
snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); |
2132 |
return g_strdup(path);
|
2133 |
} |
2134 |
|
2135 |
static char *pcibus_get_dev_path(DeviceState *dev) |
2136 |
{ |
2137 |
PCIDevice *d = container_of(dev, PCIDevice, qdev); |
2138 |
PCIDevice *t; |
2139 |
int slot_depth;
|
2140 |
/* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
|
2141 |
* 00 is added here to make this format compatible with
|
2142 |
* domain:Bus:Slot.Func for systems without nested PCI bridges.
|
2143 |
* Slot.Function list specifies the slot and function numbers for all
|
2144 |
* devices on the path from root to the specific device. */
|
2145 |
const char *root_bus_path; |
2146 |
int root_bus_len;
|
2147 |
char slot[] = ":SS.F"; |
2148 |
int slot_len = sizeof slot - 1 /* For '\0' */; |
2149 |
int path_len;
|
2150 |
char *path, *p;
|
2151 |
int s;
|
2152 |
|
2153 |
root_bus_path = pci_root_bus_path(d); |
2154 |
root_bus_len = strlen(root_bus_path); |
2155 |
|
2156 |
/* Calculate # of slots on path between device and root. */;
|
2157 |
slot_depth = 0;
|
2158 |
for (t = d; t; t = t->bus->parent_dev) {
|
2159 |
++slot_depth; |
2160 |
} |
2161 |
|
2162 |
path_len = root_bus_len + slot_len * slot_depth; |
2163 |
|
2164 |
/* Allocate memory, fill in the terminating null byte. */
|
2165 |
path = g_malloc(path_len + 1 /* For '\0' */); |
2166 |
path[path_len] = '\0';
|
2167 |
|
2168 |
memcpy(path, root_bus_path, root_bus_len); |
2169 |
|
2170 |
/* Fill in slot numbers. We walk up from device to root, so need to print
|
2171 |
* them in the reverse order, last to first. */
|
2172 |
p = path + path_len; |
2173 |
for (t = d; t; t = t->bus->parent_dev) {
|
2174 |
p -= slot_len; |
2175 |
s = snprintf(slot, sizeof slot, ":%02x.%x", |
2176 |
PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); |
2177 |
assert(s == slot_len); |
2178 |
memcpy(p, slot, slot_len); |
2179 |
} |
2180 |
|
2181 |
return path;
|
2182 |
} |
2183 |
|
2184 |
static int pci_qdev_find_recursive(PCIBus *bus, |
2185 |
const char *id, PCIDevice **pdev) |
2186 |
{ |
2187 |
DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); |
2188 |
if (!qdev) {
|
2189 |
return -ENODEV;
|
2190 |
} |
2191 |
|
2192 |
/* roughly check if given qdev is pci device */
|
2193 |
if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
|
2194 |
*pdev = PCI_DEVICE(qdev); |
2195 |
return 0; |
2196 |
} |
2197 |
return -EINVAL;
|
2198 |
} |
2199 |
|
2200 |
int pci_qdev_find_device(const char *id, PCIDevice **pdev) |
2201 |
{ |
2202 |
PCIHostState *host_bridge; |
2203 |
int rc = -ENODEV;
|
2204 |
|
2205 |
QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
2206 |
int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
|
2207 |
if (!tmp) {
|
2208 |
rc = 0;
|
2209 |
break;
|
2210 |
} |
2211 |
if (tmp != -ENODEV) {
|
2212 |
rc = tmp; |
2213 |
} |
2214 |
} |
2215 |
|
2216 |
return rc;
|
2217 |
} |
2218 |
|
2219 |
MemoryRegion *pci_address_space(PCIDevice *dev) |
2220 |
{ |
2221 |
return dev->bus->address_space_mem;
|
2222 |
} |
2223 |
|
2224 |
MemoryRegion *pci_address_space_io(PCIDevice *dev) |
2225 |
{ |
2226 |
return dev->bus->address_space_io;
|
2227 |
} |
2228 |
|
2229 |
static void pci_device_class_init(ObjectClass *klass, void *data) |
2230 |
{ |
2231 |
DeviceClass *k = DEVICE_CLASS(klass); |
2232 |
k->init = pci_qdev_init; |
2233 |
k->unplug = pci_unplug_device; |
2234 |
k->exit = pci_unregister_device; |
2235 |
k->bus_type = TYPE_PCI_BUS; |
2236 |
k->props = pci_props; |
2237 |
} |
2238 |
|
2239 |
AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) |
2240 |
{ |
2241 |
PCIBus *bus = PCI_BUS(dev->bus); |
2242 |
|
2243 |
if (bus->iommu_fn) {
|
2244 |
return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn);
|
2245 |
} |
2246 |
|
2247 |
if (bus->parent_dev) {
|
2248 |
/** We are ignoring the bus master DMA bit of the bridge
|
2249 |
* as it would complicate things such as VFIO for no good reason */
|
2250 |
return pci_device_iommu_address_space(bus->parent_dev);
|
2251 |
} |
2252 |
|
2253 |
return &address_space_memory;
|
2254 |
} |
2255 |
|
2256 |
void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) |
2257 |
{ |
2258 |
bus->iommu_fn = fn; |
2259 |
bus->iommu_opaque = opaque; |
2260 |
} |
2261 |
|
2262 |
static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) |
2263 |
{ |
2264 |
Range *range = opaque; |
2265 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
2266 |
uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); |
2267 |
int r;
|
2268 |
|
2269 |
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
2270 |
return;
|
2271 |
} |
2272 |
|
2273 |
if (pc->is_bridge) {
|
2274 |
pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
2275 |
pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
2276 |
|
2277 |
base = MAX(base, 0x1ULL << 32); |
2278 |
|
2279 |
if (limit >= base) {
|
2280 |
Range pref_range; |
2281 |
pref_range.begin = base; |
2282 |
pref_range.end = limit + 1;
|
2283 |
range_extend(range, &pref_range); |
2284 |
} |
2285 |
} |
2286 |
for (r = 0; r < PCI_NUM_REGIONS; ++r) { |
2287 |
PCIIORegion *region = &dev->io_regions[r]; |
2288 |
Range region_range; |
2289 |
|
2290 |
if (!region->size ||
|
2291 |
(region->type & PCI_BASE_ADDRESS_SPACE_IO) || |
2292 |
!(region->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { |
2293 |
continue;
|
2294 |
} |
2295 |
region_range.begin = pci_get_quad(dev->config + pci_bar(dev, r)); |
2296 |
region_range.end = region_range.begin + region->size; |
2297 |
|
2298 |
region_range.begin = MAX(region_range.begin, 0x1ULL << 32); |
2299 |
|
2300 |
if (region_range.end - 1 >= region_range.begin) { |
2301 |
range_extend(range, ®ion_range); |
2302 |
} |
2303 |
} |
2304 |
} |
2305 |
|
2306 |
void pci_bus_get_w64_range(PCIBus *bus, Range *range)
|
2307 |
{ |
2308 |
range->begin = range->end = 0;
|
2309 |
pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); |
2310 |
} |
2311 |
|
2312 |
static const TypeInfo pci_device_type_info = { |
2313 |
.name = TYPE_PCI_DEVICE, |
2314 |
.parent = TYPE_DEVICE, |
2315 |
.instance_size = sizeof(PCIDevice),
|
2316 |
.abstract = true,
|
2317 |
.class_size = sizeof(PCIDeviceClass),
|
2318 |
.class_init = pci_device_class_init, |
2319 |
}; |
2320 |
|
2321 |
static void pci_register_types(void) |
2322 |
{ |
2323 |
type_register_static(&pci_bus_info); |
2324 |
type_register_static(&pcie_bus_info); |
2325 |
type_register_static(&pci_device_type_info); |
2326 |
} |
2327 |
|
2328 |
type_init(pci_register_types) |