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/*
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 * QEMU Floppy disk emulator (Intel 82078)
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 * 
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 * Copyright (c) 2003, 2007 Jocelyn Mayer
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * The controller is used in Sun4m systems in a slightly different
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 * way. There are changes in DOR register and DMA is not available.
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 */
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#include "vl.h"
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, args...) \
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do { printf("FLOPPY: " fmt , ##args); } while (0)
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#else
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#define FLOPPY_DPRINTF(fmt, args...)
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#endif
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#define FLOPPY_ERROR(fmt, args...) \
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do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ##args); } while (0)
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/********************************************************/
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/* Floppy drive emulation                               */
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN 512
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#define FD_SECTOR_SC  2   /* Sector size code */
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/* Floppy disk drive emulation */
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typedef enum fdisk_type_t {
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    FDRIVE_DISK_288   = 0x01, /* 2.88 MB disk           */
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    FDRIVE_DISK_144   = 0x02, /* 1.44 MB disk           */
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    FDRIVE_DISK_720   = 0x03, /* 720 kB disk            */
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    FDRIVE_DISK_USER  = 0x04, /* User defined geometry  */
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    FDRIVE_DISK_NONE  = 0x05, /* No disk                */
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} fdisk_type_t;
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typedef enum fdrive_type_t {
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    FDRIVE_DRV_144  = 0x00,   /* 1.44 MB 3"5 drive      */
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    FDRIVE_DRV_288  = 0x01,   /* 2.88 MB 3"5 drive      */
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    FDRIVE_DRV_120  = 0x02,   /* 1.2  MB 5"25 drive     */
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    FDRIVE_DRV_NONE = 0x03,   /* No drive connected     */
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} fdrive_type_t;
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typedef enum fdrive_flags_t {
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    FDRIVE_MOTOR_ON   = 0x01, /* motor on/off           */
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} fdrive_flags_t;
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typedef enum fdisk_flags_t {
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    FDISK_DBL_SIDES  = 0x01,
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} fdisk_flags_t;
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typedef struct fdrive_t {
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    BlockDriverState *bs;
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    /* Drive status */
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    fdrive_type_t drive;
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    fdrive_flags_t drflags;
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    uint8_t perpendicular;    /* 2.88 MB access mode    */
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    /* Position */
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    uint8_t head;
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    uint8_t track;
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    uint8_t sect;
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    /* Last operation status */
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    uint8_t dir;              /* Direction              */
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    uint8_t rw;               /* Read/write             */
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    /* Media */
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    fdisk_flags_t flags;
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    uint8_t last_sect;        /* Nb sector per track    */
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    uint8_t max_track;        /* Nb of tracks           */
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    uint16_t bps;             /* Bytes per sector       */
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    uint8_t ro;               /* Is read-only           */
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} fdrive_t;
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static void fd_init (fdrive_t *drv, BlockDriverState *bs)
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{
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    /* Drive */
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    drv->bs = bs;
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    drv->drive = FDRIVE_DRV_NONE;
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    drv->drflags = 0;
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    drv->perpendicular = 0;
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    /* Disk */
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    drv->last_sect = 0;
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    drv->max_track = 0;
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}
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static int _fd_sector (uint8_t head, uint8_t track,
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                        uint8_t sect, uint8_t last_sect)
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{
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    return (((track * 2) + head) * last_sect) + sect - 1;
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}
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/* Returns current position, in sectors, for given drive */
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static int fd_sector (fdrive_t *drv)
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{
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    return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
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}
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static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
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                    int enable_seek)
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{
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    uint32_t sector;
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    int ret;
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    if (track > drv->max_track ||
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        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 2;
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    }
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    if (sect > drv->last_sect) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 3;
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    }
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    sector = _fd_sector(head, track, sect, drv->last_sect);
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    ret = 0;
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    if (sector != fd_sector(drv)) {
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#if 0
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        if (!enable_seek) {
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            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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                         head, track, sect, 1, drv->max_track, drv->last_sect);
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            return 4;
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        }
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#endif
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        drv->head = head;
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        if (drv->track != track)
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            ret = 1;
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        drv->track = track;
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        drv->sect = sect;
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    }
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    return ret;
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}
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/* Set drive back to track 0 */
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static void fd_recalibrate (fdrive_t *drv)
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{
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    FLOPPY_DPRINTF("recalibrate\n");
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    drv->head = 0;
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    drv->track = 0;
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    drv->sect = 1;
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    drv->dir = 1;
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    drv->rw = 0;
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}
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/* Recognize floppy formats */
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typedef struct fd_format_t {
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    fdrive_type_t drive;
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    fdisk_type_t  disk;
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    uint8_t last_sect;
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    uint8_t max_track;
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    uint8_t max_head;
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    const unsigned char *str;
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} fd_format_t;
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static fd_format_t fd_formats[] = {
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    /* First entry is default format */
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    /* 1.44 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1,  "1.6 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
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    /* 2.88 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1,  "3.2 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
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    /* 720 kB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 1,  "720 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1,  "800 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1,  "820 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1,  "830 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
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    /* 1.2 MB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1,  "1.2 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1,  "1.6 MB 5\"1/4", },
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    /* 720 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 80, 1,  "720 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1,  "880 kB 5\"1/4", },
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    /* 360 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 1,  "360 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 0,  "180 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1,  "410 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1,  "420 kB 5\"1/4", },
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    /* 320 kB 5"1/4 floppy disks */ 
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 1,  "320 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 0,  "160 kB 5\"1/4", },
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    /* 360 kB must match 5"1/4 better than 3"1/2... */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 0,  "360 kB 3\"1/2", },
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    /* end */
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    { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
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};
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate (fdrive_t *drv)
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{
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    fd_format_t *parse;
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    int64_t nb_sectors, size;
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    int i, first_match, match;
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    int nb_heads, max_track, last_sect, ro;
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    FLOPPY_DPRINTF("revalidate\n");
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    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
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        ro = bdrv_is_read_only(drv->bs);
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        bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
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        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
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            FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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                           nb_heads - 1, max_track, last_sect);
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        } else {
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            bdrv_get_geometry(drv->bs, &nb_sectors);
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            match = -1;
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            first_match = -1;
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            for (i = 0;; i++) {
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                parse = &fd_formats[i];
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                if (parse->drive == FDRIVE_DRV_NONE)
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                    break;
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                if (drv->drive == parse->drive ||
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                    drv->drive == FDRIVE_DRV_NONE) {
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                    size = (parse->max_head + 1) * parse->max_track *
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                        parse->last_sect;
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                    if (nb_sectors == size) {
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                        match = i;
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                        break;
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                    }
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                    if (first_match == -1)
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                        first_match = i;
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                }
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            }
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            if (match == -1) {
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                if (first_match == -1)
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                    match = 1;
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                else
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                    match = first_match;
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                parse = &fd_formats[match];
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            }
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            nb_heads = parse->max_head + 1;
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            max_track = parse->max_track;
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            last_sect = parse->last_sect;
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            drv->drive = parse->drive;
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            FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
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                           nb_heads, max_track, last_sect, ro ? "ro" : "rw");
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        }
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            if (nb_heads == 1) {
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                drv->flags &= ~FDISK_DBL_SIDES;
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            } else {
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                drv->flags |= FDISK_DBL_SIDES;
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            }
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            drv->max_track = max_track;
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            drv->last_sect = last_sect;
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        drv->ro = ro;
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    } else {
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        FLOPPY_DPRINTF("No disk in drive\n");
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        drv->last_sect = 0;
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        drv->max_track = 0;
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        drv->flags &= ~FDISK_DBL_SIDES;
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    }
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}
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/* Motor control */
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static void fd_start (fdrive_t *drv)
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{
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    drv->drflags |= FDRIVE_MOTOR_ON;
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}
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static void fd_stop (fdrive_t *drv)
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{
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    drv->drflags &= ~FDRIVE_MOTOR_ON;
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}
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/* Re-initialise a drives (motor off, repositioned) */
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static void fd_reset (fdrive_t *drv)
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{
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    fd_stop(drv);
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    fd_recalibrate(drv);
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}
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation          */
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static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
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static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
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static int fdctrl_transfer_handler (void *opaque, int nchan,
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                                    int dma_pos, int dma_len);
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static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status);
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static void fdctrl_result_timer(void *opaque);
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static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
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static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
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static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
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static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
329 baca51fa bellard
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
330 baca51fa bellard
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
331 baca51fa bellard
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
332 8977f3c1 bellard
333 8977f3c1 bellard
enum {
334 ed5fd2cc bellard
    FD_CTRL_ACTIVE = 0x01, /* XXX: suppress that */
335 8977f3c1 bellard
    FD_CTRL_RESET  = 0x02,
336 ed5fd2cc bellard
    FD_CTRL_SLEEP  = 0x04, /* XXX: suppress that */
337 ed5fd2cc bellard
    FD_CTRL_BUSY   = 0x08, /* dma transfer in progress */
338 8977f3c1 bellard
    FD_CTRL_INTR   = 0x10,
339 8977f3c1 bellard
};
340 8977f3c1 bellard
341 8977f3c1 bellard
enum {
342 8977f3c1 bellard
    FD_DIR_WRITE   = 0,
343 8977f3c1 bellard
    FD_DIR_READ    = 1,
344 8977f3c1 bellard
    FD_DIR_SCANE   = 2,
345 8977f3c1 bellard
    FD_DIR_SCANL   = 3,
346 8977f3c1 bellard
    FD_DIR_SCANH   = 4,
347 8977f3c1 bellard
};
348 8977f3c1 bellard
349 8977f3c1 bellard
enum {
350 8977f3c1 bellard
    FD_STATE_CMD    = 0x00,
351 8977f3c1 bellard
    FD_STATE_STATUS = 0x01,
352 8977f3c1 bellard
    FD_STATE_DATA   = 0x02,
353 8977f3c1 bellard
    FD_STATE_STATE  = 0x03,
354 8977f3c1 bellard
    FD_STATE_MULTI  = 0x10,
355 8977f3c1 bellard
    FD_STATE_SEEK   = 0x20,
356 baca51fa bellard
    FD_STATE_FORMAT = 0x40,
357 8977f3c1 bellard
};
358 8977f3c1 bellard
359 8977f3c1 bellard
#define FD_STATE(state) ((state) & FD_STATE_STATE)
360 baca51fa bellard
#define FD_SET_STATE(state, new_state) \
361 baca51fa bellard
do { (state) = ((state) & ~FD_STATE_STATE) | (new_state); } while (0)
362 8977f3c1 bellard
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
363 8977f3c1 bellard
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
364 baca51fa bellard
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
365 8977f3c1 bellard
366 baca51fa bellard
struct fdctrl_t {
367 baca51fa bellard
    fdctrl_t *fdctrl;
368 4b19ec0c bellard
    /* Controller's identification */
369 8977f3c1 bellard
    uint8_t version;
370 8977f3c1 bellard
    /* HW */
371 d537cf6c pbrook
    qemu_irq irq;
372 8977f3c1 bellard
    int dma_chann;
373 5dcb6b91 blueswir1
    target_phys_addr_t io_base;
374 4b19ec0c bellard
    /* Controller state */
375 ed5fd2cc bellard
    QEMUTimer *result_timer;
376 8977f3c1 bellard
    uint8_t state;
377 8977f3c1 bellard
    uint8_t dma_en;
378 8977f3c1 bellard
    uint8_t cur_drv;
379 8977f3c1 bellard
    uint8_t bootsel;
380 8977f3c1 bellard
    /* Command FIFO */
381 8977f3c1 bellard
    uint8_t fifo[FD_SECTOR_LEN];
382 8977f3c1 bellard
    uint32_t data_pos;
383 8977f3c1 bellard
    uint32_t data_len;
384 8977f3c1 bellard
    uint8_t data_state;
385 8977f3c1 bellard
    uint8_t data_dir;
386 8977f3c1 bellard
    uint8_t int_status;
387 890fa6be bellard
    uint8_t eot; /* last wanted sector */
388 8977f3c1 bellard
    /* States kept only to be returned back */
389 8977f3c1 bellard
    /* Timers state */
390 8977f3c1 bellard
    uint8_t timer0;
391 8977f3c1 bellard
    uint8_t timer1;
392 8977f3c1 bellard
    /* precompensation */
393 8977f3c1 bellard
    uint8_t precomp_trk;
394 8977f3c1 bellard
    uint8_t config;
395 8977f3c1 bellard
    uint8_t lock;
396 8977f3c1 bellard
    /* Power down config (also with status regB access mode */
397 8977f3c1 bellard
    uint8_t pwrd;
398 8977f3c1 bellard
    /* Floppy drives */
399 8977f3c1 bellard
    fdrive_t drives[2];
400 baca51fa bellard
};
401 baca51fa bellard
402 baca51fa bellard
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
403 baca51fa bellard
{
404 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
405 baca51fa bellard
    uint32_t retval;
406 baca51fa bellard
407 a541f297 bellard
    switch (reg & 0x07) {
408 6f7e9aec bellard
#ifdef TARGET_SPARC
409 6f7e9aec bellard
    case 0x00:
410 6f7e9aec bellard
        // Identify to Linux as S82078B
411 6f7e9aec bellard
        retval = fdctrl_read_statusB(fdctrl);
412 6f7e9aec bellard
        break;
413 6f7e9aec bellard
#endif
414 a541f297 bellard
    case 0x01:
415 baca51fa bellard
        retval = fdctrl_read_statusB(fdctrl);
416 a541f297 bellard
        break;
417 a541f297 bellard
    case 0x02:
418 baca51fa bellard
        retval = fdctrl_read_dor(fdctrl);
419 a541f297 bellard
        break;
420 a541f297 bellard
    case 0x03:
421 baca51fa bellard
        retval = fdctrl_read_tape(fdctrl);
422 a541f297 bellard
        break;
423 a541f297 bellard
    case 0x04:
424 baca51fa bellard
        retval = fdctrl_read_main_status(fdctrl);
425 a541f297 bellard
        break;
426 a541f297 bellard
    case 0x05:
427 baca51fa bellard
        retval = fdctrl_read_data(fdctrl);
428 a541f297 bellard
        break;
429 a541f297 bellard
    case 0x07:
430 baca51fa bellard
        retval = fdctrl_read_dir(fdctrl);
431 a541f297 bellard
        break;
432 a541f297 bellard
    default:
433 baca51fa bellard
        retval = (uint32_t)(-1);
434 a541f297 bellard
        break;
435 a541f297 bellard
    }
436 ed5fd2cc bellard
    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
437 baca51fa bellard
438 baca51fa bellard
    return retval;
439 baca51fa bellard
}
440 baca51fa bellard
441 baca51fa bellard
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
442 baca51fa bellard
{
443 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
444 baca51fa bellard
445 ed5fd2cc bellard
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
446 ed5fd2cc bellard
447 a541f297 bellard
    switch (reg & 0x07) {
448 a541f297 bellard
    case 0x02:
449 baca51fa bellard
        fdctrl_write_dor(fdctrl, value);
450 a541f297 bellard
        break;
451 a541f297 bellard
    case 0x03:
452 baca51fa bellard
        fdctrl_write_tape(fdctrl, value);
453 a541f297 bellard
        break;
454 a541f297 bellard
    case 0x04:
455 baca51fa bellard
        fdctrl_write_rate(fdctrl, value);
456 a541f297 bellard
        break;
457 a541f297 bellard
    case 0x05:
458 baca51fa bellard
        fdctrl_write_data(fdctrl, value);
459 a541f297 bellard
        break;
460 a541f297 bellard
    default:
461 a541f297 bellard
        break;
462 a541f297 bellard
    }
463 baca51fa bellard
}
464 baca51fa bellard
465 62a46c61 bellard
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
466 62a46c61 bellard
{
467 5dcb6b91 blueswir1
    return fdctrl_read(opaque, (uint32_t)reg);
468 62a46c61 bellard
}
469 62a46c61 bellard
470 62a46c61 bellard
static void fdctrl_write_mem (void *opaque, 
471 62a46c61 bellard
                              target_phys_addr_t reg, uint32_t value)
472 62a46c61 bellard
{
473 5dcb6b91 blueswir1
    fdctrl_write(opaque, (uint32_t)reg, value);
474 62a46c61 bellard
}
475 62a46c61 bellard
476 e80cfcfc bellard
static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
477 62a46c61 bellard
    fdctrl_read_mem,
478 62a46c61 bellard
    fdctrl_read_mem,
479 62a46c61 bellard
    fdctrl_read_mem,
480 e80cfcfc bellard
};
481 e80cfcfc bellard
482 e80cfcfc bellard
static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
483 62a46c61 bellard
    fdctrl_write_mem,
484 62a46c61 bellard
    fdctrl_write_mem,
485 62a46c61 bellard
    fdctrl_write_mem,
486 e80cfcfc bellard
};
487 e80cfcfc bellard
488 3ccacc4a blueswir1
static void fd_save (QEMUFile *f, fdrive_t *fd)
489 3ccacc4a blueswir1
{
490 3ccacc4a blueswir1
    uint8_t tmp;
491 3ccacc4a blueswir1
492 3ccacc4a blueswir1
    tmp = fd->drflags;
493 3ccacc4a blueswir1
    qemu_put_8s(f, &tmp);
494 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->head);
495 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->track);
496 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->sect);
497 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->dir);
498 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->rw);
499 3ccacc4a blueswir1
}
500 3ccacc4a blueswir1
501 3ccacc4a blueswir1
static void fdc_save (QEMUFile *f, void *opaque)
502 3ccacc4a blueswir1
{
503 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
504 3ccacc4a blueswir1
505 3ccacc4a blueswir1
    qemu_put_8s(f, &s->state);
506 3ccacc4a blueswir1
    qemu_put_8s(f, &s->dma_en);
507 3ccacc4a blueswir1
    qemu_put_8s(f, &s->cur_drv);
508 3ccacc4a blueswir1
    qemu_put_8s(f, &s->bootsel);
509 3ccacc4a blueswir1
    qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
510 3ccacc4a blueswir1
    qemu_put_be32s(f, &s->data_pos);
511 3ccacc4a blueswir1
    qemu_put_be32s(f, &s->data_len);
512 3ccacc4a blueswir1
    qemu_put_8s(f, &s->data_state);
513 3ccacc4a blueswir1
    qemu_put_8s(f, &s->data_dir);
514 3ccacc4a blueswir1
    qemu_put_8s(f, &s->int_status);
515 3ccacc4a blueswir1
    qemu_put_8s(f, &s->eot);
516 3ccacc4a blueswir1
    qemu_put_8s(f, &s->timer0);
517 3ccacc4a blueswir1
    qemu_put_8s(f, &s->timer1);
518 3ccacc4a blueswir1
    qemu_put_8s(f, &s->precomp_trk);
519 3ccacc4a blueswir1
    qemu_put_8s(f, &s->config);
520 3ccacc4a blueswir1
    qemu_put_8s(f, &s->lock);
521 3ccacc4a blueswir1
    qemu_put_8s(f, &s->pwrd);
522 3ccacc4a blueswir1
    fd_save(f, &s->drives[0]);
523 3ccacc4a blueswir1
    fd_save(f, &s->drives[1]);
524 3ccacc4a blueswir1
}
525 3ccacc4a blueswir1
526 3ccacc4a blueswir1
static int fd_load (QEMUFile *f, fdrive_t *fd)
527 3ccacc4a blueswir1
{
528 3ccacc4a blueswir1
    uint8_t tmp;
529 3ccacc4a blueswir1
530 3ccacc4a blueswir1
    qemu_get_8s(f, &tmp);
531 3ccacc4a blueswir1
    fd->drflags = tmp;
532 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->head);
533 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->track);
534 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->sect);
535 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->dir);
536 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->rw);
537 3ccacc4a blueswir1
538 3ccacc4a blueswir1
    return 0;
539 3ccacc4a blueswir1
}
540 3ccacc4a blueswir1
541 3ccacc4a blueswir1
static int fdc_load (QEMUFile *f, void *opaque, int version_id)
542 3ccacc4a blueswir1
{
543 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
544 3ccacc4a blueswir1
    int ret;
545 3ccacc4a blueswir1
546 3ccacc4a blueswir1
    if (version_id != 1)
547 3ccacc4a blueswir1
        return -EINVAL;
548 3ccacc4a blueswir1
549 3ccacc4a blueswir1
    qemu_get_8s(f, &s->state);
550 3ccacc4a blueswir1
    qemu_get_8s(f, &s->dma_en);
551 3ccacc4a blueswir1
    qemu_get_8s(f, &s->cur_drv);
552 3ccacc4a blueswir1
    qemu_get_8s(f, &s->bootsel);
553 3ccacc4a blueswir1
    qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
554 3ccacc4a blueswir1
    qemu_get_be32s(f, &s->data_pos);
555 3ccacc4a blueswir1
    qemu_get_be32s(f, &s->data_len);
556 3ccacc4a blueswir1
    qemu_get_8s(f, &s->data_state);
557 3ccacc4a blueswir1
    qemu_get_8s(f, &s->data_dir);
558 3ccacc4a blueswir1
    qemu_get_8s(f, &s->int_status);
559 3ccacc4a blueswir1
    qemu_get_8s(f, &s->eot);
560 3ccacc4a blueswir1
    qemu_get_8s(f, &s->timer0);
561 3ccacc4a blueswir1
    qemu_get_8s(f, &s->timer1);
562 3ccacc4a blueswir1
    qemu_get_8s(f, &s->precomp_trk);
563 3ccacc4a blueswir1
    qemu_get_8s(f, &s->config);
564 3ccacc4a blueswir1
    qemu_get_8s(f, &s->lock);
565 3ccacc4a blueswir1
    qemu_get_8s(f, &s->pwrd);
566 3ccacc4a blueswir1
567 3ccacc4a blueswir1
    ret = fd_load(f, &s->drives[0]);
568 3ccacc4a blueswir1
    if (ret == 0)
569 3ccacc4a blueswir1
        ret = fd_load(f, &s->drives[1]);
570 3ccacc4a blueswir1
571 3ccacc4a blueswir1
    return ret;
572 3ccacc4a blueswir1
}
573 3ccacc4a blueswir1
574 3ccacc4a blueswir1
static void fdctrl_external_reset(void *opaque)
575 3ccacc4a blueswir1
{
576 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
577 3ccacc4a blueswir1
578 3ccacc4a blueswir1
    fdctrl_reset(s, 0);
579 3ccacc4a blueswir1
}
580 3ccacc4a blueswir1
581 d537cf6c pbrook
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, 
582 5dcb6b91 blueswir1
                       target_phys_addr_t io_base,
583 baca51fa bellard
                       BlockDriverState **fds)
584 8977f3c1 bellard
{
585 baca51fa bellard
    fdctrl_t *fdctrl;
586 e80cfcfc bellard
    int io_mem;
587 8977f3c1 bellard
    int i;
588 8977f3c1 bellard
589 4b19ec0c bellard
    FLOPPY_DPRINTF("init controller\n");
590 baca51fa bellard
    fdctrl = qemu_mallocz(sizeof(fdctrl_t));
591 baca51fa bellard
    if (!fdctrl)
592 baca51fa bellard
        return NULL;
593 ed5fd2cc bellard
    fdctrl->result_timer = qemu_new_timer(vm_clock, 
594 ed5fd2cc bellard
                                          fdctrl_result_timer, fdctrl);
595 ed5fd2cc bellard
596 4b19ec0c bellard
    fdctrl->version = 0x90; /* Intel 82078 controller */
597 d537cf6c pbrook
    fdctrl->irq = irq;
598 baca51fa bellard
    fdctrl->dma_chann = dma_chann;
599 baca51fa bellard
    fdctrl->io_base = io_base;
600 a541f297 bellard
    fdctrl->config = 0x60; /* Implicit seek, polling & FIFO enabled */
601 baca51fa bellard
    if (fdctrl->dma_chann != -1) {
602 baca51fa bellard
        fdctrl->dma_en = 1;
603 baca51fa bellard
        DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
604 8977f3c1 bellard
    } else {
605 baca51fa bellard
        fdctrl->dma_en = 0;
606 8977f3c1 bellard
    }
607 baca51fa bellard
    for (i = 0; i < 2; i++) {
608 baca51fa bellard
        fd_init(&fdctrl->drives[i], fds[i]);
609 caed8802 bellard
    }
610 baca51fa bellard
    fdctrl_reset(fdctrl, 0);
611 baca51fa bellard
    fdctrl->state = FD_CTRL_ACTIVE;
612 8977f3c1 bellard
    if (mem_mapped) {
613 e80cfcfc bellard
        io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write, fdctrl);
614 e80cfcfc bellard
        cpu_register_physical_memory(io_base, 0x08, io_mem);
615 8977f3c1 bellard
    } else {
616 5dcb6b91 blueswir1
        register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
617 5dcb6b91 blueswir1
                             fdctrl);
618 5dcb6b91 blueswir1
        register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
619 5dcb6b91 blueswir1
                             fdctrl);
620 5dcb6b91 blueswir1
        register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
621 5dcb6b91 blueswir1
                              fdctrl);
622 5dcb6b91 blueswir1
        register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
623 5dcb6b91 blueswir1
                              fdctrl);
624 8977f3c1 bellard
    }
625 3ccacc4a blueswir1
    register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
626 3ccacc4a blueswir1
    qemu_register_reset(fdctrl_external_reset, fdctrl);
627 a541f297 bellard
    for (i = 0; i < 2; i++) {
628 baca51fa bellard
        fd_revalidate(&fdctrl->drives[i]);
629 8977f3c1 bellard
    }
630 a541f297 bellard
631 baca51fa bellard
    return fdctrl;
632 caed8802 bellard
}
633 8977f3c1 bellard
634 baca51fa bellard
/* XXX: may change if moved to bdrv */
635 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
636 caed8802 bellard
{
637 baca51fa bellard
    return fdctrl->drives[drive_num].drive;
638 8977f3c1 bellard
}
639 8977f3c1 bellard
640 8977f3c1 bellard
/* Change IRQ state */
641 baca51fa bellard
static void fdctrl_reset_irq (fdctrl_t *fdctrl)
642 8977f3c1 bellard
{
643 ed5fd2cc bellard
    FLOPPY_DPRINTF("Reset interrupt\n");
644 d537cf6c pbrook
    qemu_set_irq(fdctrl->irq, 0);
645 ed5fd2cc bellard
    fdctrl->state &= ~FD_CTRL_INTR;
646 8977f3c1 bellard
}
647 8977f3c1 bellard
648 baca51fa bellard
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status)
649 8977f3c1 bellard
{
650 6f7e9aec bellard
#ifdef TARGET_SPARC
651 6f7e9aec bellard
    // Sparc mutation
652 6f7e9aec bellard
    if (!fdctrl->dma_en) {
653 6f7e9aec bellard
        fdctrl->state &= ~FD_CTRL_BUSY;
654 6f7e9aec bellard
        fdctrl->int_status = status;
655 6f7e9aec bellard
        return;
656 6f7e9aec bellard
    }
657 6f7e9aec bellard
#endif
658 baca51fa bellard
    if (~(fdctrl->state & FD_CTRL_INTR)) {
659 d537cf6c pbrook
        qemu_set_irq(fdctrl->irq, 1);
660 baca51fa bellard
        fdctrl->state |= FD_CTRL_INTR;
661 8977f3c1 bellard
    }
662 8977f3c1 bellard
    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", status);
663 baca51fa bellard
    fdctrl->int_status = status;
664 8977f3c1 bellard
}
665 8977f3c1 bellard
666 4b19ec0c bellard
/* Reset controller */
667 baca51fa bellard
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
668 8977f3c1 bellard
{
669 8977f3c1 bellard
    int i;
670 8977f3c1 bellard
671 4b19ec0c bellard
    FLOPPY_DPRINTF("reset controller\n");
672 baca51fa bellard
    fdctrl_reset_irq(fdctrl);
673 4b19ec0c bellard
    /* Initialise controller */
674 baca51fa bellard
    fdctrl->cur_drv = 0;
675 8977f3c1 bellard
    /* FIFO state */
676 baca51fa bellard
    fdctrl->data_pos = 0;
677 baca51fa bellard
    fdctrl->data_len = 0;
678 baca51fa bellard
    fdctrl->data_state = FD_STATE_CMD;
679 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
680 8977f3c1 bellard
    for (i = 0; i < MAX_FD; i++)
681 baca51fa bellard
        fd_reset(&fdctrl->drives[i]);
682 baca51fa bellard
    fdctrl_reset_fifo(fdctrl);
683 8977f3c1 bellard
    if (do_irq)
684 ed5fd2cc bellard
        fdctrl_raise_irq(fdctrl, 0xc0);
685 baca51fa bellard
}
686 baca51fa bellard
687 baca51fa bellard
static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
688 baca51fa bellard
{
689 baca51fa bellard
    return &fdctrl->drives[fdctrl->bootsel];
690 baca51fa bellard
}
691 baca51fa bellard
692 baca51fa bellard
static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
693 baca51fa bellard
{
694 baca51fa bellard
    return &fdctrl->drives[1 - fdctrl->bootsel];
695 baca51fa bellard
}
696 baca51fa bellard
697 baca51fa bellard
static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
698 baca51fa bellard
{
699 baca51fa bellard
    return fdctrl->cur_drv == 0 ? drv0(fdctrl) : drv1(fdctrl);
700 8977f3c1 bellard
}
701 8977f3c1 bellard
702 8977f3c1 bellard
/* Status B register : 0x01 (read-only) */
703 baca51fa bellard
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
704 8977f3c1 bellard
{
705 8977f3c1 bellard
    FLOPPY_DPRINTF("status register: 0x00\n");
706 8977f3c1 bellard
    return 0;
707 8977f3c1 bellard
}
708 8977f3c1 bellard
709 8977f3c1 bellard
/* Digital output register : 0x02 */
710 baca51fa bellard
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
711 8977f3c1 bellard
{
712 8977f3c1 bellard
    uint32_t retval = 0;
713 8977f3c1 bellard
714 8977f3c1 bellard
    /* Drive motors state indicators */
715 baca51fa bellard
    if (drv0(fdctrl)->drflags & FDRIVE_MOTOR_ON)
716 baca51fa bellard
        retval |= 1 << 5;
717 baca51fa bellard
    if (drv1(fdctrl)->drflags & FDRIVE_MOTOR_ON)
718 baca51fa bellard
        retval |= 1 << 4;
719 8977f3c1 bellard
    /* DMA enable */
720 baca51fa bellard
    retval |= fdctrl->dma_en << 3;
721 8977f3c1 bellard
    /* Reset indicator */
722 baca51fa bellard
    retval |= (fdctrl->state & FD_CTRL_RESET) == 0 ? 0x04 : 0;
723 8977f3c1 bellard
    /* Selected drive */
724 baca51fa bellard
    retval |= fdctrl->cur_drv;
725 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
726 8977f3c1 bellard
727 8977f3c1 bellard
    return retval;
728 8977f3c1 bellard
}
729 8977f3c1 bellard
730 baca51fa bellard
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
731 8977f3c1 bellard
{
732 8977f3c1 bellard
    /* Reset mode */
733 baca51fa bellard
    if (fdctrl->state & FD_CTRL_RESET) {
734 8977f3c1 bellard
        if (!(value & 0x04)) {
735 4b19ec0c bellard
            FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
736 8977f3c1 bellard
            return;
737 8977f3c1 bellard
        }
738 8977f3c1 bellard
    }
739 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
740 8977f3c1 bellard
    /* Drive motors state indicators */
741 8977f3c1 bellard
    if (value & 0x20)
742 baca51fa bellard
        fd_start(drv1(fdctrl));
743 8977f3c1 bellard
    else
744 baca51fa bellard
        fd_stop(drv1(fdctrl));
745 8977f3c1 bellard
    if (value & 0x10)
746 baca51fa bellard
        fd_start(drv0(fdctrl));
747 8977f3c1 bellard
    else
748 baca51fa bellard
        fd_stop(drv0(fdctrl));
749 8977f3c1 bellard
    /* DMA enable */
750 8977f3c1 bellard
#if 0
751 baca51fa bellard
    if (fdctrl->dma_chann != -1)
752 baca51fa bellard
        fdctrl->dma_en = 1 - ((value >> 3) & 1);
753 8977f3c1 bellard
#endif
754 8977f3c1 bellard
    /* Reset */
755 8977f3c1 bellard
    if (!(value & 0x04)) {
756 baca51fa bellard
        if (!(fdctrl->state & FD_CTRL_RESET)) {
757 4b19ec0c bellard
            FLOPPY_DPRINTF("controller enter RESET state\n");
758 baca51fa bellard
            fdctrl->state |= FD_CTRL_RESET;
759 8977f3c1 bellard
        }
760 8977f3c1 bellard
    } else {
761 baca51fa bellard
        if (fdctrl->state & FD_CTRL_RESET) {
762 4b19ec0c bellard
            FLOPPY_DPRINTF("controller out of RESET state\n");
763 fb6cf1d0 bellard
            fdctrl_reset(fdctrl, 1);
764 baca51fa bellard
            fdctrl->state &= ~(FD_CTRL_RESET | FD_CTRL_SLEEP);
765 8977f3c1 bellard
        }
766 8977f3c1 bellard
    }
767 8977f3c1 bellard
    /* Selected drive */
768 baca51fa bellard
    fdctrl->cur_drv = value & 1;
769 8977f3c1 bellard
}
770 8977f3c1 bellard
771 8977f3c1 bellard
/* Tape drive register : 0x03 */
772 baca51fa bellard
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
773 8977f3c1 bellard
{
774 8977f3c1 bellard
    uint32_t retval = 0;
775 8977f3c1 bellard
776 8977f3c1 bellard
    /* Disk boot selection indicator */
777 baca51fa bellard
    retval |= fdctrl->bootsel << 2;
778 8977f3c1 bellard
    /* Tape indicators: never allowed */
779 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
780 8977f3c1 bellard
781 8977f3c1 bellard
    return retval;
782 8977f3c1 bellard
}
783 8977f3c1 bellard
784 baca51fa bellard
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
785 8977f3c1 bellard
{
786 8977f3c1 bellard
    /* Reset mode */
787 baca51fa bellard
    if (fdctrl->state & FD_CTRL_RESET) {
788 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
789 8977f3c1 bellard
        return;
790 8977f3c1 bellard
    }
791 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
792 8977f3c1 bellard
    /* Disk boot selection indicator */
793 baca51fa bellard
    fdctrl->bootsel = (value >> 2) & 1;
794 8977f3c1 bellard
    /* Tape indicators: never allow */
795 8977f3c1 bellard
}
796 8977f3c1 bellard
797 8977f3c1 bellard
/* Main status register : 0x04 (read) */
798 baca51fa bellard
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
799 8977f3c1 bellard
{
800 8977f3c1 bellard
    uint32_t retval = 0;
801 8977f3c1 bellard
802 baca51fa bellard
    fdctrl->state &= ~(FD_CTRL_SLEEP | FD_CTRL_RESET);
803 baca51fa bellard
    if (!(fdctrl->state & FD_CTRL_BUSY)) {
804 8977f3c1 bellard
        /* Data transfer allowed */
805 8977f3c1 bellard
        retval |= 0x80;
806 8977f3c1 bellard
        /* Data transfer direction indicator */
807 baca51fa bellard
        if (fdctrl->data_dir == FD_DIR_READ)
808 8977f3c1 bellard
            retval |= 0x40;
809 8977f3c1 bellard
    }
810 8977f3c1 bellard
    /* Should handle 0x20 for SPECIFY command */
811 8977f3c1 bellard
    /* Command busy indicator */
812 baca51fa bellard
    if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA ||
813 baca51fa bellard
        FD_STATE(fdctrl->data_state) == FD_STATE_STATUS)
814 8977f3c1 bellard
        retval |= 0x10;
815 8977f3c1 bellard
    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
816 8977f3c1 bellard
817 8977f3c1 bellard
    return retval;
818 8977f3c1 bellard
}
819 8977f3c1 bellard
820 8977f3c1 bellard
/* Data select rate register : 0x04 (write) */
821 baca51fa bellard
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
822 8977f3c1 bellard
{
823 8977f3c1 bellard
    /* Reset mode */
824 baca51fa bellard
    if (fdctrl->state & FD_CTRL_RESET) {
825 4b19ec0c bellard
            FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
826 8977f3c1 bellard
            return;
827 8977f3c1 bellard
        }
828 8977f3c1 bellard
    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
829 8977f3c1 bellard
    /* Reset: autoclear */
830 8977f3c1 bellard
    if (value & 0x80) {
831 baca51fa bellard
        fdctrl->state |= FD_CTRL_RESET;
832 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
833 baca51fa bellard
        fdctrl->state &= ~FD_CTRL_RESET;
834 8977f3c1 bellard
    }
835 8977f3c1 bellard
    if (value & 0x40) {
836 baca51fa bellard
        fdctrl->state |= FD_CTRL_SLEEP;
837 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
838 8977f3c1 bellard
    }
839 8977f3c1 bellard
//        fdctrl.precomp = (value >> 2) & 0x07;
840 8977f3c1 bellard
}
841 8977f3c1 bellard
842 ea185bbd bellard
static int fdctrl_media_changed(fdrive_t *drv)
843 ea185bbd bellard
{
844 ea185bbd bellard
    int ret;
845 ea185bbd bellard
    if (!drv->bs) 
846 ea185bbd bellard
        return 0;
847 ea185bbd bellard
    ret = bdrv_media_changed(drv->bs);
848 ea185bbd bellard
    if (ret) {
849 ea185bbd bellard
        fd_revalidate(drv);
850 ea185bbd bellard
    }
851 ea185bbd bellard
    return ret;
852 ea185bbd bellard
}
853 ea185bbd bellard
854 8977f3c1 bellard
/* Digital input register : 0x07 (read-only) */
855 baca51fa bellard
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
856 8977f3c1 bellard
{
857 8977f3c1 bellard
    uint32_t retval = 0;
858 8977f3c1 bellard
859 ea185bbd bellard
    if (fdctrl_media_changed(drv0(fdctrl)) ||
860 ea185bbd bellard
        fdctrl_media_changed(drv1(fdctrl)))
861 8977f3c1 bellard
        retval |= 0x80;
862 8977f3c1 bellard
    if (retval != 0)
863 baca51fa bellard
        FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
864 8977f3c1 bellard
865 8977f3c1 bellard
    return retval;
866 8977f3c1 bellard
}
867 8977f3c1 bellard
868 8977f3c1 bellard
/* FIFO state control */
869 baca51fa bellard
static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
870 8977f3c1 bellard
{
871 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
872 baca51fa bellard
    fdctrl->data_pos = 0;
873 baca51fa bellard
    FD_SET_STATE(fdctrl->data_state, FD_STATE_CMD);
874 8977f3c1 bellard
}
875 8977f3c1 bellard
876 8977f3c1 bellard
/* Set FIFO status for the host to read */
877 baca51fa bellard
static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
878 8977f3c1 bellard
{
879 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
880 baca51fa bellard
    fdctrl->data_len = fifo_len;
881 baca51fa bellard
    fdctrl->data_pos = 0;
882 baca51fa bellard
    FD_SET_STATE(fdctrl->data_state, FD_STATE_STATUS);
883 8977f3c1 bellard
    if (do_irq)
884 baca51fa bellard
        fdctrl_raise_irq(fdctrl, 0x00);
885 8977f3c1 bellard
}
886 8977f3c1 bellard
887 8977f3c1 bellard
/* Set an error: unimplemented/unknown command */
888 baca51fa bellard
static void fdctrl_unimplemented (fdctrl_t *fdctrl)
889 8977f3c1 bellard
{
890 8977f3c1 bellard
#if 0
891 baca51fa bellard
    fdrive_t *cur_drv;
892 baca51fa bellard

893 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
894 890fa6be bellard
    fdctrl->fifo[0] = 0x60 | (cur_drv->head << 2) | fdctrl->cur_drv;
895 baca51fa bellard
    fdctrl->fifo[1] = 0x00;
896 baca51fa bellard
    fdctrl->fifo[2] = 0x00;
897 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 3, 1);
898 8977f3c1 bellard
#else
899 baca51fa bellard
    //    fdctrl_reset_fifo(fdctrl);
900 baca51fa bellard
    fdctrl->fifo[0] = 0x80;
901 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 1, 0);
902 8977f3c1 bellard
#endif
903 8977f3c1 bellard
}
904 8977f3c1 bellard
905 8977f3c1 bellard
/* Callback for transfer end (stop or abort) */
906 baca51fa bellard
static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
907 baca51fa bellard
                                  uint8_t status1, uint8_t status2)
908 8977f3c1 bellard
{
909 baca51fa bellard
    fdrive_t *cur_drv;
910 8977f3c1 bellard
911 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
912 8977f3c1 bellard
    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
913 8977f3c1 bellard
                   status0, status1, status2,
914 890fa6be bellard
                   status0 | (cur_drv->head << 2) | fdctrl->cur_drv);
915 890fa6be bellard
    fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | fdctrl->cur_drv;
916 baca51fa bellard
    fdctrl->fifo[1] = status1;
917 baca51fa bellard
    fdctrl->fifo[2] = status2;
918 baca51fa bellard
    fdctrl->fifo[3] = cur_drv->track;
919 baca51fa bellard
    fdctrl->fifo[4] = cur_drv->head;
920 baca51fa bellard
    fdctrl->fifo[5] = cur_drv->sect;
921 baca51fa bellard
    fdctrl->fifo[6] = FD_SECTOR_SC;
922 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
923 ed5fd2cc bellard
    if (fdctrl->state & FD_CTRL_BUSY) {
924 baca51fa bellard
        DMA_release_DREQ(fdctrl->dma_chann);
925 ed5fd2cc bellard
        fdctrl->state &= ~FD_CTRL_BUSY;
926 ed5fd2cc bellard
    }
927 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 7, 1);
928 8977f3c1 bellard
}
929 8977f3c1 bellard
930 8977f3c1 bellard
/* Prepare a data transfer (either DMA or FIFO) */
931 baca51fa bellard
static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
932 8977f3c1 bellard
{
933 baca51fa bellard
    fdrive_t *cur_drv;
934 8977f3c1 bellard
    uint8_t kh, kt, ks;
935 8977f3c1 bellard
    int did_seek;
936 8977f3c1 bellard
937 baca51fa bellard
    fdctrl->cur_drv = fdctrl->fifo[1] & 1;
938 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
939 baca51fa bellard
    kt = fdctrl->fifo[2];
940 baca51fa bellard
    kh = fdctrl->fifo[3];
941 baca51fa bellard
    ks = fdctrl->fifo[4];
942 4b19ec0c bellard
    FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
943 baca51fa bellard
                   fdctrl->cur_drv, kh, kt, ks,
944 8977f3c1 bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
945 8977f3c1 bellard
    did_seek = 0;
946 baca51fa bellard
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & 0x40)) {
947 8977f3c1 bellard
    case 2:
948 8977f3c1 bellard
        /* sect too big */
949 baca51fa bellard
        fdctrl_stop_transfer(fdctrl, 0x40, 0x00, 0x00);
950 baca51fa bellard
        fdctrl->fifo[3] = kt;
951 baca51fa bellard
        fdctrl->fifo[4] = kh;
952 baca51fa bellard
        fdctrl->fifo[5] = ks;
953 8977f3c1 bellard
        return;
954 8977f3c1 bellard
    case 3:
955 8977f3c1 bellard
        /* track too big */
956 baca51fa bellard
        fdctrl_stop_transfer(fdctrl, 0x40, 0x80, 0x00);
957 baca51fa bellard
        fdctrl->fifo[3] = kt;
958 baca51fa bellard
        fdctrl->fifo[4] = kh;
959 baca51fa bellard
        fdctrl->fifo[5] = ks;
960 8977f3c1 bellard
        return;
961 8977f3c1 bellard
    case 4:
962 8977f3c1 bellard
        /* No seek enabled */
963 baca51fa bellard
        fdctrl_stop_transfer(fdctrl, 0x40, 0x00, 0x00);
964 baca51fa bellard
        fdctrl->fifo[3] = kt;
965 baca51fa bellard
        fdctrl->fifo[4] = kh;
966 baca51fa bellard
        fdctrl->fifo[5] = ks;
967 8977f3c1 bellard
        return;
968 8977f3c1 bellard
    case 1:
969 8977f3c1 bellard
        did_seek = 1;
970 8977f3c1 bellard
        break;
971 8977f3c1 bellard
    default:
972 8977f3c1 bellard
        break;
973 8977f3c1 bellard
    }
974 8977f3c1 bellard
    /* Set the FIFO state */
975 baca51fa bellard
    fdctrl->data_dir = direction;
976 baca51fa bellard
    fdctrl->data_pos = 0;
977 baca51fa bellard
    FD_SET_STATE(fdctrl->data_state, FD_STATE_DATA); /* FIFO ready for data */
978 baca51fa bellard
    if (fdctrl->fifo[0] & 0x80)
979 baca51fa bellard
        fdctrl->data_state |= FD_STATE_MULTI;
980 baca51fa bellard
    else
981 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_MULTI;
982 8977f3c1 bellard
    if (did_seek)
983 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
984 baca51fa bellard
    else
985 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_SEEK;
986 baca51fa bellard
    if (fdctrl->fifo[5] == 00) {
987 baca51fa bellard
        fdctrl->data_len = fdctrl->fifo[8];
988 baca51fa bellard
    } else {
989 baca51fa bellard
        int tmp;
990 3bcb80f1 ths
        fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
991 baca51fa bellard
        tmp = (cur_drv->last_sect - ks + 1);
992 baca51fa bellard
        if (fdctrl->fifo[0] & 0x80)
993 baca51fa bellard
            tmp += cur_drv->last_sect;
994 baca51fa bellard
        fdctrl->data_len *= tmp;
995 baca51fa bellard
    }
996 890fa6be bellard
    fdctrl->eot = fdctrl->fifo[6];
997 baca51fa bellard
    if (fdctrl->dma_en) {
998 8977f3c1 bellard
        int dma_mode;
999 8977f3c1 bellard
        /* DMA transfer are enabled. Check if DMA channel is well programmed */
1000 baca51fa bellard
        dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1001 8977f3c1 bellard
        dma_mode = (dma_mode >> 2) & 3;
1002 baca51fa bellard
        FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1003 baca51fa bellard
                       dma_mode, direction,
1004 baca51fa bellard
                       (128 << fdctrl->fifo[5]) *
1005 baca51fa bellard
                       (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1006 8977f3c1 bellard
        if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1007 8977f3c1 bellard
              direction == FD_DIR_SCANH) && dma_mode == 0) ||
1008 8977f3c1 bellard
            (direction == FD_DIR_WRITE && dma_mode == 2) ||
1009 8977f3c1 bellard
            (direction == FD_DIR_READ && dma_mode == 1)) {
1010 8977f3c1 bellard
            /* No access is allowed until DMA transfer has completed */
1011 baca51fa bellard
            fdctrl->state |= FD_CTRL_BUSY;
1012 4b19ec0c bellard
            /* Now, we just have to wait for the DMA controller to
1013 8977f3c1 bellard
             * recall us...
1014 8977f3c1 bellard
             */
1015 baca51fa bellard
            DMA_hold_DREQ(fdctrl->dma_chann);
1016 baca51fa bellard
            DMA_schedule(fdctrl->dma_chann);
1017 8977f3c1 bellard
            return;
1018 baca51fa bellard
        } else {
1019 baca51fa bellard
            FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1020 8977f3c1 bellard
        }
1021 8977f3c1 bellard
    }
1022 8977f3c1 bellard
    FLOPPY_DPRINTF("start non-DMA transfer\n");
1023 8977f3c1 bellard
    /* IO based transfer: calculate len */
1024 baca51fa bellard
    fdctrl_raise_irq(fdctrl, 0x00);
1025 8977f3c1 bellard
1026 8977f3c1 bellard
    return;
1027 8977f3c1 bellard
}
1028 8977f3c1 bellard
1029 8977f3c1 bellard
/* Prepare a transfer of deleted data */
1030 baca51fa bellard
static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1031 8977f3c1 bellard
{
1032 8977f3c1 bellard
    /* We don't handle deleted data,
1033 8977f3c1 bellard
     * so we don't return *ANYTHING*
1034 8977f3c1 bellard
     */
1035 baca51fa bellard
    fdctrl_stop_transfer(fdctrl, 0x60, 0x00, 0x00);
1036 8977f3c1 bellard
}
1037 8977f3c1 bellard
1038 8977f3c1 bellard
/* handlers for DMA transfers */
1039 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
1040 85571bc7 bellard
                                    int dma_pos, int dma_len)
1041 8977f3c1 bellard
{
1042 baca51fa bellard
    fdctrl_t *fdctrl;
1043 baca51fa bellard
    fdrive_t *cur_drv;
1044 baca51fa bellard
    int len, start_pos, rel_pos;
1045 8977f3c1 bellard
    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1046 8977f3c1 bellard
1047 baca51fa bellard
    fdctrl = opaque;
1048 baca51fa bellard
    if (!(fdctrl->state & FD_CTRL_BUSY)) {
1049 8977f3c1 bellard
        FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1050 8977f3c1 bellard
        return 0;
1051 8977f3c1 bellard
    }
1052 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1053 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1054 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1055 8977f3c1 bellard
        status2 = 0x04;
1056 85571bc7 bellard
    if (dma_len > fdctrl->data_len)
1057 85571bc7 bellard
        dma_len = fdctrl->data_len;
1058 890fa6be bellard
    if (cur_drv->bs == NULL) {
1059 baca51fa bellard
        if (fdctrl->data_dir == FD_DIR_WRITE)
1060 baca51fa bellard
            fdctrl_stop_transfer(fdctrl, 0x60, 0x00, 0x00);
1061 baca51fa bellard
        else
1062 baca51fa bellard
            fdctrl_stop_transfer(fdctrl, 0x40, 0x00, 0x00);
1063 baca51fa bellard
        len = 0;
1064 890fa6be bellard
        goto transfer_error;
1065 890fa6be bellard
    }
1066 baca51fa bellard
    rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1067 85571bc7 bellard
    for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1068 85571bc7 bellard
        len = dma_len - fdctrl->data_pos;
1069 baca51fa bellard
        if (len + rel_pos > FD_SECTOR_LEN)
1070 baca51fa bellard
            len = FD_SECTOR_LEN - rel_pos;
1071 6f7e9aec bellard
        FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1072 6f7e9aec bellard
                       "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1073 baca51fa bellard
                       fdctrl->data_len, fdctrl->cur_drv, cur_drv->head,
1074 baca51fa bellard
                       cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1075 6f7e9aec bellard
                       fd_sector(cur_drv) * 512);
1076 baca51fa bellard
        if (fdctrl->data_dir != FD_DIR_WRITE ||
1077 baca51fa bellard
            len < FD_SECTOR_LEN || rel_pos != 0) {
1078 baca51fa bellard
            /* READ & SCAN commands and realign to a sector for WRITE */
1079 baca51fa bellard
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1080 baca51fa bellard
                          fdctrl->fifo, 1) < 0) {
1081 8977f3c1 bellard
                FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1082 8977f3c1 bellard
                               fd_sector(cur_drv));
1083 8977f3c1 bellard
                /* Sure, image size is too small... */
1084 baca51fa bellard
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1085 8977f3c1 bellard
            }
1086 890fa6be bellard
        }
1087 baca51fa bellard
        switch (fdctrl->data_dir) {
1088 baca51fa bellard
        case FD_DIR_READ:
1089 baca51fa bellard
            /* READ commands */
1090 85571bc7 bellard
            DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1091 85571bc7 bellard
                              fdctrl->data_pos, len);
1092 85571bc7 bellard
/*             cpu_physical_memory_write(addr + fdctrl->data_pos, */
1093 85571bc7 bellard
/*                                       fdctrl->fifo + rel_pos, len); */
1094 baca51fa bellard
            break;
1095 baca51fa bellard
        case FD_DIR_WRITE:
1096 baca51fa bellard
            /* WRITE commands */
1097 85571bc7 bellard
            DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1098 85571bc7 bellard
                             fdctrl->data_pos, len);
1099 85571bc7 bellard
/*             cpu_physical_memory_read(addr + fdctrl->data_pos, */
1100 85571bc7 bellard
/*                                      fdctrl->fifo + rel_pos, len); */
1101 baca51fa bellard
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1102 baca51fa bellard
                           fdctrl->fifo, 1) < 0) {
1103 baca51fa bellard
                FLOPPY_ERROR("writting sector %d\n", fd_sector(cur_drv));
1104 baca51fa bellard
                fdctrl_stop_transfer(fdctrl, 0x60, 0x00, 0x00);
1105 baca51fa bellard
                goto transfer_error;
1106 890fa6be bellard
            }
1107 baca51fa bellard
            break;
1108 baca51fa bellard
        default:
1109 baca51fa bellard
            /* SCAN commands */
1110 baca51fa bellard
            {
1111 baca51fa bellard
                uint8_t tmpbuf[FD_SECTOR_LEN];
1112 baca51fa bellard
                int ret;
1113 85571bc7 bellard
                DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1114 85571bc7 bellard
/*                 cpu_physical_memory_read(addr + fdctrl->data_pos, */
1115 85571bc7 bellard
/*                                          tmpbuf, len); */
1116 baca51fa bellard
                ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1117 8977f3c1 bellard
                if (ret == 0) {
1118 8977f3c1 bellard
                    status2 = 0x08;
1119 8977f3c1 bellard
                    goto end_transfer;
1120 8977f3c1 bellard
                }
1121 baca51fa bellard
                if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1122 baca51fa bellard
                    (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1123 8977f3c1 bellard
                    status2 = 0x00;
1124 8977f3c1 bellard
                    goto end_transfer;
1125 8977f3c1 bellard
                }
1126 8977f3c1 bellard
            }
1127 baca51fa bellard
            break;
1128 8977f3c1 bellard
        }
1129 baca51fa bellard
        fdctrl->data_pos += len;
1130 baca51fa bellard
        rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1131 baca51fa bellard
        if (rel_pos == 0) {
1132 8977f3c1 bellard
            /* Seek to next sector */
1133 baca51fa bellard
            FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d) (%d)\n",
1134 baca51fa bellard
                           cur_drv->head, cur_drv->track, cur_drv->sect,
1135 baca51fa bellard
                           fd_sector(cur_drv),
1136 6f7e9aec bellard
                           fdctrl->data_pos - len);
1137 890fa6be bellard
            /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1138 890fa6be bellard
               error in fact */
1139 890fa6be bellard
            if (cur_drv->sect >= cur_drv->last_sect ||
1140 890fa6be bellard
                cur_drv->sect == fdctrl->eot) {
1141 baca51fa bellard
                cur_drv->sect = 1;
1142 baca51fa bellard
                if (FD_MULTI_TRACK(fdctrl->data_state)) {
1143 baca51fa bellard
                    if (cur_drv->head == 0 &&
1144 baca51fa bellard
                        (cur_drv->flags & FDISK_DBL_SIDES) != 0) {        
1145 890fa6be bellard
                        cur_drv->head = 1;
1146 890fa6be bellard
                    } else {
1147 890fa6be bellard
                        cur_drv->head = 0;
1148 baca51fa bellard
                        cur_drv->track++;
1149 baca51fa bellard
                        if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1150 baca51fa bellard
                            break;
1151 890fa6be bellard
                    }
1152 890fa6be bellard
                } else {
1153 890fa6be bellard
                    cur_drv->track++;
1154 890fa6be bellard
                    break;
1155 8977f3c1 bellard
                }
1156 baca51fa bellard
                FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1157 baca51fa bellard
                               cur_drv->head, cur_drv->track,
1158 baca51fa bellard
                               cur_drv->sect, fd_sector(cur_drv));
1159 890fa6be bellard
            } else {
1160 890fa6be bellard
                cur_drv->sect++;
1161 8977f3c1 bellard
            }
1162 8977f3c1 bellard
        }
1163 8977f3c1 bellard
    }
1164 8977f3c1 bellard
end_transfer:
1165 baca51fa bellard
    len = fdctrl->data_pos - start_pos;
1166 baca51fa bellard
    FLOPPY_DPRINTF("end transfer %d %d %d\n",
1167 baca51fa bellard
                   fdctrl->data_pos, len, fdctrl->data_len);
1168 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE ||
1169 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANL ||
1170 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1171 8977f3c1 bellard
        status2 = 0x08;
1172 baca51fa bellard
    if (FD_DID_SEEK(fdctrl->data_state))
1173 8977f3c1 bellard
        status0 |= 0x20;
1174 baca51fa bellard
    fdctrl->data_len -= len;
1175 baca51fa bellard
    //    if (fdctrl->data_len == 0)
1176 890fa6be bellard
    fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1177 8977f3c1 bellard
transfer_error:
1178 8977f3c1 bellard
1179 baca51fa bellard
    return len;
1180 8977f3c1 bellard
}
1181 8977f3c1 bellard
1182 8977f3c1 bellard
/* Data register : 0x05 */
1183 baca51fa bellard
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1184 8977f3c1 bellard
{
1185 baca51fa bellard
    fdrive_t *cur_drv;
1186 8977f3c1 bellard
    uint32_t retval = 0;
1187 8977f3c1 bellard
    int pos, len;
1188 8977f3c1 bellard
1189 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1190 baca51fa bellard
    fdctrl->state &= ~FD_CTRL_SLEEP;
1191 baca51fa bellard
    if (FD_STATE(fdctrl->data_state) == FD_STATE_CMD) {
1192 8977f3c1 bellard
        FLOPPY_ERROR("can't read data in CMD state\n");
1193 8977f3c1 bellard
        return 0;
1194 8977f3c1 bellard
    }
1195 baca51fa bellard
    pos = fdctrl->data_pos;
1196 baca51fa bellard
    if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
1197 8977f3c1 bellard
        pos %= FD_SECTOR_LEN;
1198 8977f3c1 bellard
        if (pos == 0) {
1199 baca51fa bellard
            len = fdctrl->data_len - fdctrl->data_pos;
1200 8977f3c1 bellard
            if (len > FD_SECTOR_LEN)
1201 8977f3c1 bellard
                len = FD_SECTOR_LEN;
1202 8977f3c1 bellard
            bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1203 baca51fa bellard
                      fdctrl->fifo, len);
1204 8977f3c1 bellard
        }
1205 8977f3c1 bellard
    }
1206 baca51fa bellard
    retval = fdctrl->fifo[pos];
1207 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1208 baca51fa bellard
        fdctrl->data_pos = 0;
1209 890fa6be bellard
        /* Switch from transfer mode to status mode
1210 8977f3c1 bellard
         * then from status mode to command mode
1211 8977f3c1 bellard
         */
1212 ed5fd2cc bellard
        if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
1213 baca51fa bellard
            fdctrl_stop_transfer(fdctrl, 0x20, 0x00, 0x00);
1214 ed5fd2cc bellard
        } else {
1215 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1216 ed5fd2cc bellard
            fdctrl_reset_irq(fdctrl);
1217 ed5fd2cc bellard
        }
1218 8977f3c1 bellard
    }
1219 8977f3c1 bellard
    FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1220 8977f3c1 bellard
1221 8977f3c1 bellard
    return retval;
1222 8977f3c1 bellard
}
1223 8977f3c1 bellard
1224 baca51fa bellard
static void fdctrl_format_sector (fdctrl_t *fdctrl)
1225 8977f3c1 bellard
{
1226 baca51fa bellard
    fdrive_t *cur_drv;
1227 baca51fa bellard
    uint8_t kh, kt, ks;
1228 baca51fa bellard
    int did_seek;
1229 8977f3c1 bellard
1230 baca51fa bellard
    fdctrl->cur_drv = fdctrl->fifo[1] & 1;
1231 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1232 baca51fa bellard
    kt = fdctrl->fifo[6];
1233 baca51fa bellard
    kh = fdctrl->fifo[7];
1234 baca51fa bellard
    ks = fdctrl->fifo[8];
1235 baca51fa bellard
    FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1236 baca51fa bellard
                   fdctrl->cur_drv, kh, kt, ks,
1237 baca51fa bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1238 baca51fa bellard
    did_seek = 0;
1239 baca51fa bellard
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & 0x40)) {
1240 baca51fa bellard
    case 2:
1241 baca51fa bellard
        /* sect too big */
1242 baca51fa bellard
        fdctrl_stop_transfer(fdctrl, 0x40, 0x00, 0x00);
1243 baca51fa bellard
        fdctrl->fifo[3] = kt;
1244 baca51fa bellard
        fdctrl->fifo[4] = kh;
1245 baca51fa bellard
        fdctrl->fifo[5] = ks;
1246 baca51fa bellard
        return;
1247 baca51fa bellard
    case 3:
1248 baca51fa bellard
        /* track too big */
1249 baca51fa bellard
        fdctrl_stop_transfer(fdctrl, 0x40, 0x80, 0x00);
1250 baca51fa bellard
        fdctrl->fifo[3] = kt;
1251 baca51fa bellard
        fdctrl->fifo[4] = kh;
1252 baca51fa bellard
        fdctrl->fifo[5] = ks;
1253 baca51fa bellard
        return;
1254 baca51fa bellard
    case 4:
1255 baca51fa bellard
        /* No seek enabled */
1256 baca51fa bellard
        fdctrl_stop_transfer(fdctrl, 0x40, 0x00, 0x00);
1257 baca51fa bellard
        fdctrl->fifo[3] = kt;
1258 baca51fa bellard
        fdctrl->fifo[4] = kh;
1259 baca51fa bellard
        fdctrl->fifo[5] = ks;
1260 baca51fa bellard
        return;
1261 baca51fa bellard
    case 1:
1262 baca51fa bellard
        did_seek = 1;
1263 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1264 baca51fa bellard
        break;
1265 baca51fa bellard
    default:
1266 baca51fa bellard
        break;
1267 baca51fa bellard
    }
1268 baca51fa bellard
    memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1269 baca51fa bellard
    if (cur_drv->bs == NULL ||
1270 baca51fa bellard
        bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1271 baca51fa bellard
        FLOPPY_ERROR("formating sector %d\n", fd_sector(cur_drv));
1272 baca51fa bellard
        fdctrl_stop_transfer(fdctrl, 0x60, 0x00, 0x00);
1273 baca51fa bellard
    } else {
1274 baca51fa bellard
        if (cur_drv->sect == cur_drv->last_sect) {
1275 baca51fa bellard
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1276 baca51fa bellard
            /* Last sector done */
1277 baca51fa bellard
            if (FD_DID_SEEK(fdctrl->data_state))
1278 baca51fa bellard
                fdctrl_stop_transfer(fdctrl, 0x20, 0x00, 0x00);
1279 baca51fa bellard
            else
1280 baca51fa bellard
                fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1281 baca51fa bellard
        } else {
1282 baca51fa bellard
            /* More to do */
1283 baca51fa bellard
            fdctrl->data_pos = 0;
1284 baca51fa bellard
            fdctrl->data_len = 4;
1285 baca51fa bellard
        }
1286 baca51fa bellard
    }
1287 baca51fa bellard
}
1288 baca51fa bellard
1289 baca51fa bellard
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1290 baca51fa bellard
{
1291 baca51fa bellard
    fdrive_t *cur_drv;
1292 baca51fa bellard
1293 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1294 8977f3c1 bellard
    /* Reset mode */
1295 baca51fa bellard
    if (fdctrl->state & FD_CTRL_RESET) {
1296 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1297 8977f3c1 bellard
        return;
1298 8977f3c1 bellard
    }
1299 baca51fa bellard
    fdctrl->state &= ~FD_CTRL_SLEEP;
1300 baca51fa bellard
    if (FD_STATE(fdctrl->data_state) == FD_STATE_STATUS) {
1301 8977f3c1 bellard
        FLOPPY_ERROR("can't write data in status mode\n");
1302 8977f3c1 bellard
        return;
1303 8977f3c1 bellard
    }
1304 8977f3c1 bellard
    /* Is it write command time ? */
1305 baca51fa bellard
    if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
1306 8977f3c1 bellard
        /* FIFO data write */
1307 baca51fa bellard
        fdctrl->fifo[fdctrl->data_pos++] = value;
1308 baca51fa bellard
        if (fdctrl->data_pos % FD_SECTOR_LEN == (FD_SECTOR_LEN - 1) ||
1309 baca51fa bellard
            fdctrl->data_pos == fdctrl->data_len) {
1310 8977f3c1 bellard
            bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1311 baca51fa bellard
                       fdctrl->fifo, FD_SECTOR_LEN);
1312 8977f3c1 bellard
        }
1313 890fa6be bellard
        /* Switch from transfer mode to status mode
1314 8977f3c1 bellard
         * then from status mode to command mode
1315 8977f3c1 bellard
         */
1316 baca51fa bellard
        if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA)
1317 baca51fa bellard
            fdctrl_stop_transfer(fdctrl, 0x20, 0x00, 0x00);
1318 8977f3c1 bellard
        return;
1319 8977f3c1 bellard
    }
1320 baca51fa bellard
    if (fdctrl->data_pos == 0) {
1321 8977f3c1 bellard
        /* Command */
1322 8977f3c1 bellard
        switch (value & 0x5F) {
1323 8977f3c1 bellard
        case 0x46:
1324 8977f3c1 bellard
            /* READ variants */
1325 8977f3c1 bellard
            FLOPPY_DPRINTF("READ command\n");
1326 8977f3c1 bellard
            /* 8 parameters cmd */
1327 baca51fa bellard
            fdctrl->data_len = 9;
1328 8977f3c1 bellard
            goto enqueue;
1329 8977f3c1 bellard
        case 0x4C:
1330 8977f3c1 bellard
            /* READ_DELETED variants */
1331 8977f3c1 bellard
            FLOPPY_DPRINTF("READ_DELETED command\n");
1332 8977f3c1 bellard
            /* 8 parameters cmd */
1333 baca51fa bellard
            fdctrl->data_len = 9;
1334 8977f3c1 bellard
            goto enqueue;
1335 8977f3c1 bellard
        case 0x50:
1336 8977f3c1 bellard
            /* SCAN_EQUAL variants */
1337 8977f3c1 bellard
            FLOPPY_DPRINTF("SCAN_EQUAL command\n");
1338 8977f3c1 bellard
            /* 8 parameters cmd */
1339 baca51fa bellard
            fdctrl->data_len = 9;
1340 8977f3c1 bellard
            goto enqueue;
1341 8977f3c1 bellard
        case 0x56:
1342 8977f3c1 bellard
            /* VERIFY variants */
1343 8977f3c1 bellard
            FLOPPY_DPRINTF("VERIFY command\n");
1344 8977f3c1 bellard
            /* 8 parameters cmd */
1345 baca51fa bellard
            fdctrl->data_len = 9;
1346 8977f3c1 bellard
            goto enqueue;
1347 8977f3c1 bellard
        case 0x59:
1348 8977f3c1 bellard
            /* SCAN_LOW_OR_EQUAL variants */
1349 8977f3c1 bellard
            FLOPPY_DPRINTF("SCAN_LOW_OR_EQUAL command\n");
1350 8977f3c1 bellard
            /* 8 parameters cmd */
1351 baca51fa bellard
            fdctrl->data_len = 9;
1352 8977f3c1 bellard
            goto enqueue;
1353 8977f3c1 bellard
        case 0x5D:
1354 8977f3c1 bellard
            /* SCAN_HIGH_OR_EQUAL variants */
1355 8977f3c1 bellard
            FLOPPY_DPRINTF("SCAN_HIGH_OR_EQUAL command\n");
1356 8977f3c1 bellard
            /* 8 parameters cmd */
1357 baca51fa bellard
            fdctrl->data_len = 9;
1358 8977f3c1 bellard
            goto enqueue;
1359 8977f3c1 bellard
        default:
1360 8977f3c1 bellard
            break;
1361 8977f3c1 bellard
        }
1362 8977f3c1 bellard
        switch (value & 0x7F) {
1363 8977f3c1 bellard
        case 0x45:
1364 8977f3c1 bellard
            /* WRITE variants */
1365 8977f3c1 bellard
            FLOPPY_DPRINTF("WRITE command\n");
1366 8977f3c1 bellard
            /* 8 parameters cmd */
1367 baca51fa bellard
            fdctrl->data_len = 9;
1368 8977f3c1 bellard
            goto enqueue;
1369 8977f3c1 bellard
        case 0x49:
1370 8977f3c1 bellard
            /* WRITE_DELETED variants */
1371 8977f3c1 bellard
            FLOPPY_DPRINTF("WRITE_DELETED command\n");
1372 8977f3c1 bellard
            /* 8 parameters cmd */
1373 baca51fa bellard
            fdctrl->data_len = 9;
1374 8977f3c1 bellard
            goto enqueue;
1375 8977f3c1 bellard
        default:
1376 8977f3c1 bellard
            break;
1377 8977f3c1 bellard
        }
1378 8977f3c1 bellard
        switch (value) {
1379 8977f3c1 bellard
        case 0x03:
1380 8977f3c1 bellard
            /* SPECIFY */
1381 8977f3c1 bellard
            FLOPPY_DPRINTF("SPECIFY command\n");
1382 8977f3c1 bellard
            /* 1 parameter cmd */
1383 baca51fa bellard
            fdctrl->data_len = 3;
1384 8977f3c1 bellard
            goto enqueue;
1385 8977f3c1 bellard
        case 0x04:
1386 8977f3c1 bellard
            /* SENSE_DRIVE_STATUS */
1387 8977f3c1 bellard
            FLOPPY_DPRINTF("SENSE_DRIVE_STATUS command\n");
1388 8977f3c1 bellard
            /* 1 parameter cmd */
1389 baca51fa bellard
            fdctrl->data_len = 2;
1390 8977f3c1 bellard
            goto enqueue;
1391 8977f3c1 bellard
        case 0x07:
1392 8977f3c1 bellard
            /* RECALIBRATE */
1393 8977f3c1 bellard
            FLOPPY_DPRINTF("RECALIBRATE command\n");
1394 8977f3c1 bellard
            /* 1 parameter cmd */
1395 baca51fa bellard
            fdctrl->data_len = 2;
1396 8977f3c1 bellard
            goto enqueue;
1397 8977f3c1 bellard
        case 0x08:
1398 8977f3c1 bellard
            /* SENSE_INTERRUPT_STATUS */
1399 8977f3c1 bellard
            FLOPPY_DPRINTF("SENSE_INTERRUPT_STATUS command (%02x)\n",
1400 baca51fa bellard
                           fdctrl->int_status);
1401 8977f3c1 bellard
            /* No parameters cmd: returns status if no interrupt */
1402 953569d2 bellard
#if 0
1403 baca51fa bellard
            fdctrl->fifo[0] =
1404 baca51fa bellard
                fdctrl->int_status | (cur_drv->head << 2) | fdctrl->cur_drv;
1405 953569d2 bellard
#else
1406 953569d2 bellard
            /* XXX: int_status handling is broken for read/write
1407 953569d2 bellard
               commands, so we do this hack. It should be suppressed
1408 953569d2 bellard
               ASAP */
1409 953569d2 bellard
            fdctrl->fifo[0] =
1410 953569d2 bellard
                0x20 | (cur_drv->head << 2) | fdctrl->cur_drv;
1411 953569d2 bellard
#endif
1412 baca51fa bellard
            fdctrl->fifo[1] = cur_drv->track;
1413 baca51fa bellard
            fdctrl_set_fifo(fdctrl, 2, 0);
1414 baca51fa bellard
            fdctrl_reset_irq(fdctrl);
1415 baca51fa bellard
            fdctrl->int_status = 0xC0;
1416 8977f3c1 bellard
            return;
1417 8977f3c1 bellard
        case 0x0E:
1418 8977f3c1 bellard
            /* DUMPREG */
1419 8977f3c1 bellard
            FLOPPY_DPRINTF("DUMPREG command\n");
1420 8977f3c1 bellard
            /* Drives position */
1421 baca51fa bellard
            fdctrl->fifo[0] = drv0(fdctrl)->track;
1422 baca51fa bellard
            fdctrl->fifo[1] = drv1(fdctrl)->track;
1423 baca51fa bellard
            fdctrl->fifo[2] = 0;
1424 baca51fa bellard
            fdctrl->fifo[3] = 0;
1425 8977f3c1 bellard
            /* timers */
1426 baca51fa bellard
            fdctrl->fifo[4] = fdctrl->timer0;
1427 baca51fa bellard
            fdctrl->fifo[5] = (fdctrl->timer1 << 1) | fdctrl->dma_en;
1428 baca51fa bellard
            fdctrl->fifo[6] = cur_drv->last_sect;
1429 baca51fa bellard
            fdctrl->fifo[7] = (fdctrl->lock << 7) |
1430 8977f3c1 bellard
                    (cur_drv->perpendicular << 2);
1431 baca51fa bellard
            fdctrl->fifo[8] = fdctrl->config;
1432 baca51fa bellard
            fdctrl->fifo[9] = fdctrl->precomp_trk;
1433 baca51fa bellard
            fdctrl_set_fifo(fdctrl, 10, 0);
1434 8977f3c1 bellard
            return;
1435 8977f3c1 bellard
        case 0x0F:
1436 8977f3c1 bellard
            /* SEEK */
1437 8977f3c1 bellard
            FLOPPY_DPRINTF("SEEK command\n");
1438 8977f3c1 bellard
            /* 2 parameters cmd */
1439 baca51fa bellard
            fdctrl->data_len = 3;
1440 8977f3c1 bellard
            goto enqueue;
1441 8977f3c1 bellard
        case 0x10:
1442 8977f3c1 bellard
            /* VERSION */
1443 8977f3c1 bellard
            FLOPPY_DPRINTF("VERSION command\n");
1444 8977f3c1 bellard
            /* No parameters cmd */
1445 4b19ec0c bellard
            /* Controller's version */
1446 baca51fa bellard
            fdctrl->fifo[0] = fdctrl->version;
1447 baca51fa bellard
            fdctrl_set_fifo(fdctrl, 1, 1);
1448 8977f3c1 bellard
            return;
1449 8977f3c1 bellard
        case 0x12:
1450 8977f3c1 bellard
            /* PERPENDICULAR_MODE */
1451 8977f3c1 bellard
            FLOPPY_DPRINTF("PERPENDICULAR_MODE command\n");
1452 8977f3c1 bellard
            /* 1 parameter cmd */
1453 baca51fa bellard
            fdctrl->data_len = 2;
1454 8977f3c1 bellard
            goto enqueue;
1455 8977f3c1 bellard
        case 0x13:
1456 8977f3c1 bellard
            /* CONFIGURE */
1457 8977f3c1 bellard
            FLOPPY_DPRINTF("CONFIGURE command\n");
1458 8977f3c1 bellard
            /* 3 parameters cmd */
1459 baca51fa bellard
            fdctrl->data_len = 4;
1460 8977f3c1 bellard
            goto enqueue;
1461 8977f3c1 bellard
        case 0x14:
1462 8977f3c1 bellard
            /* UNLOCK */
1463 8977f3c1 bellard
            FLOPPY_DPRINTF("UNLOCK command\n");
1464 8977f3c1 bellard
            /* No parameters cmd */
1465 baca51fa bellard
            fdctrl->lock = 0;
1466 baca51fa bellard
            fdctrl->fifo[0] = 0;
1467 baca51fa bellard
            fdctrl_set_fifo(fdctrl, 1, 0);
1468 8977f3c1 bellard
            return;
1469 8977f3c1 bellard
        case 0x17:
1470 8977f3c1 bellard
            /* POWERDOWN_MODE */
1471 8977f3c1 bellard
            FLOPPY_DPRINTF("POWERDOWN_MODE command\n");
1472 8977f3c1 bellard
            /* 2 parameters cmd */
1473 baca51fa bellard
            fdctrl->data_len = 3;
1474 8977f3c1 bellard
            goto enqueue;
1475 8977f3c1 bellard
        case 0x18:
1476 8977f3c1 bellard
            /* PART_ID */
1477 8977f3c1 bellard
            FLOPPY_DPRINTF("PART_ID command\n");
1478 8977f3c1 bellard
            /* No parameters cmd */
1479 baca51fa bellard
            fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1480 baca51fa bellard
            fdctrl_set_fifo(fdctrl, 1, 0);
1481 8977f3c1 bellard
            return;
1482 8977f3c1 bellard
        case 0x2C:
1483 8977f3c1 bellard
            /* SAVE */
1484 8977f3c1 bellard
            FLOPPY_DPRINTF("SAVE command\n");
1485 8977f3c1 bellard
            /* No parameters cmd */
1486 baca51fa bellard
            fdctrl->fifo[0] = 0;
1487 baca51fa bellard
            fdctrl->fifo[1] = 0;
1488 8977f3c1 bellard
            /* Drives position */
1489 baca51fa bellard
            fdctrl->fifo[2] = drv0(fdctrl)->track;
1490 baca51fa bellard
            fdctrl->fifo[3] = drv1(fdctrl)->track;
1491 baca51fa bellard
            fdctrl->fifo[4] = 0;
1492 baca51fa bellard
            fdctrl->fifo[5] = 0;
1493 8977f3c1 bellard
            /* timers */
1494 baca51fa bellard
            fdctrl->fifo[6] = fdctrl->timer0;
1495 baca51fa bellard
            fdctrl->fifo[7] = fdctrl->timer1;
1496 baca51fa bellard
            fdctrl->fifo[8] = cur_drv->last_sect;
1497 baca51fa bellard
            fdctrl->fifo[9] = (fdctrl->lock << 7) |
1498 8977f3c1 bellard
                    (cur_drv->perpendicular << 2);
1499 baca51fa bellard
            fdctrl->fifo[10] = fdctrl->config;
1500 baca51fa bellard
            fdctrl->fifo[11] = fdctrl->precomp_trk;
1501 baca51fa bellard
            fdctrl->fifo[12] = fdctrl->pwrd;
1502 baca51fa bellard
            fdctrl->fifo[13] = 0;
1503 baca51fa bellard
            fdctrl->fifo[14] = 0;
1504 baca51fa bellard
            fdctrl_set_fifo(fdctrl, 15, 1);
1505 8977f3c1 bellard
            return;
1506 8977f3c1 bellard
        case 0x33:
1507 8977f3c1 bellard
            /* OPTION */
1508 8977f3c1 bellard
            FLOPPY_DPRINTF("OPTION command\n");
1509 8977f3c1 bellard
            /* 1 parameter cmd */
1510 baca51fa bellard
            fdctrl->data_len = 2;
1511 8977f3c1 bellard
            goto enqueue;
1512 8977f3c1 bellard
        case 0x42:
1513 8977f3c1 bellard
            /* READ_TRACK */
1514 8977f3c1 bellard
            FLOPPY_DPRINTF("READ_TRACK command\n");
1515 8977f3c1 bellard
            /* 8 parameters cmd */
1516 baca51fa bellard
            fdctrl->data_len = 9;
1517 8977f3c1 bellard
            goto enqueue;
1518 8977f3c1 bellard
        case 0x4A:
1519 8977f3c1 bellard
            /* READ_ID */
1520 8977f3c1 bellard
            FLOPPY_DPRINTF("READ_ID command\n");
1521 8977f3c1 bellard
            /* 1 parameter cmd */
1522 baca51fa bellard
            fdctrl->data_len = 2;
1523 8977f3c1 bellard
            goto enqueue;
1524 8977f3c1 bellard
        case 0x4C:
1525 8977f3c1 bellard
            /* RESTORE */
1526 8977f3c1 bellard
            FLOPPY_DPRINTF("RESTORE command\n");
1527 8977f3c1 bellard
            /* 17 parameters cmd */
1528 baca51fa bellard
            fdctrl->data_len = 18;
1529 8977f3c1 bellard
            goto enqueue;
1530 8977f3c1 bellard
        case 0x4D:
1531 8977f3c1 bellard
            /* FORMAT_TRACK */
1532 8977f3c1 bellard
            FLOPPY_DPRINTF("FORMAT_TRACK command\n");
1533 8977f3c1 bellard
            /* 5 parameters cmd */
1534 baca51fa bellard
            fdctrl->data_len = 6;
1535 8977f3c1 bellard
            goto enqueue;
1536 8977f3c1 bellard
        case 0x8E:
1537 8977f3c1 bellard
            /* DRIVE_SPECIFICATION_COMMAND */
1538 8977f3c1 bellard
            FLOPPY_DPRINTF("DRIVE_SPECIFICATION_COMMAND command\n");
1539 8977f3c1 bellard
            /* 5 parameters cmd */
1540 baca51fa bellard
            fdctrl->data_len = 6;
1541 8977f3c1 bellard
            goto enqueue;
1542 8977f3c1 bellard
        case 0x8F:
1543 8977f3c1 bellard
            /* RELATIVE_SEEK_OUT */
1544 8977f3c1 bellard
            FLOPPY_DPRINTF("RELATIVE_SEEK_OUT command\n");
1545 8977f3c1 bellard
            /* 2 parameters cmd */
1546 baca51fa bellard
            fdctrl->data_len = 3;
1547 8977f3c1 bellard
            goto enqueue;
1548 8977f3c1 bellard
        case 0x94:
1549 8977f3c1 bellard
            /* LOCK */
1550 8977f3c1 bellard
            FLOPPY_DPRINTF("LOCK command\n");
1551 8977f3c1 bellard
            /* No parameters cmd */
1552 baca51fa bellard
            fdctrl->lock = 1;
1553 baca51fa bellard
            fdctrl->fifo[0] = 0x10;
1554 baca51fa bellard
            fdctrl_set_fifo(fdctrl, 1, 1);
1555 8977f3c1 bellard
            return;
1556 8977f3c1 bellard
        case 0xCD:
1557 8977f3c1 bellard
            /* FORMAT_AND_WRITE */
1558 8977f3c1 bellard
            FLOPPY_DPRINTF("FORMAT_AND_WRITE command\n");
1559 8977f3c1 bellard
            /* 10 parameters cmd */
1560 baca51fa bellard
            fdctrl->data_len = 11;
1561 8977f3c1 bellard
            goto enqueue;
1562 8977f3c1 bellard
        case 0xCF:
1563 8977f3c1 bellard
            /* RELATIVE_SEEK_IN */
1564 8977f3c1 bellard
            FLOPPY_DPRINTF("RELATIVE_SEEK_IN command\n");
1565 8977f3c1 bellard
            /* 2 parameters cmd */
1566 baca51fa bellard
            fdctrl->data_len = 3;
1567 8977f3c1 bellard
            goto enqueue;
1568 8977f3c1 bellard
        default:
1569 8977f3c1 bellard
            /* Unknown command */
1570 8977f3c1 bellard
            FLOPPY_ERROR("unknown command: 0x%02x\n", value);
1571 baca51fa bellard
            fdctrl_unimplemented(fdctrl);
1572 8977f3c1 bellard
            return;
1573 8977f3c1 bellard
        }
1574 8977f3c1 bellard
    }
1575 8977f3c1 bellard
enqueue:
1576 baca51fa bellard
    FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1577 baca51fa bellard
    fdctrl->fifo[fdctrl->data_pos] = value;
1578 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1579 8977f3c1 bellard
        /* We now have all parameters
1580 8977f3c1 bellard
         * and will be able to treat the command
1581 8977f3c1 bellard
         */
1582 baca51fa bellard
        if (fdctrl->data_state & FD_STATE_FORMAT) {
1583 baca51fa bellard
            fdctrl_format_sector(fdctrl);
1584 baca51fa bellard
            return;
1585 baca51fa bellard
        }
1586 baca51fa bellard
        switch (fdctrl->fifo[0] & 0x1F) {
1587 8977f3c1 bellard
        case 0x06:
1588 8977f3c1 bellard
        {
1589 8977f3c1 bellard
            /* READ variants */
1590 8977f3c1 bellard
            FLOPPY_DPRINTF("treat READ command\n");
1591 baca51fa bellard
            fdctrl_start_transfer(fdctrl, FD_DIR_READ);
1592 8977f3c1 bellard
            return;
1593 8977f3c1 bellard
        }
1594 8977f3c1 bellard
        case 0x0C:
1595 8977f3c1 bellard
            /* READ_DELETED variants */
1596 8977f3c1 bellard
//            FLOPPY_DPRINTF("treat READ_DELETED command\n");
1597 8977f3c1 bellard
            FLOPPY_ERROR("treat READ_DELETED command\n");
1598 baca51fa bellard
            fdctrl_start_transfer_del(fdctrl, FD_DIR_READ);
1599 8977f3c1 bellard
            return;
1600 8977f3c1 bellard
        case 0x16:
1601 8977f3c1 bellard
            /* VERIFY variants */
1602 8977f3c1 bellard
//            FLOPPY_DPRINTF("treat VERIFY command\n");
1603 8977f3c1 bellard
            FLOPPY_ERROR("treat VERIFY command\n");
1604 baca51fa bellard
            fdctrl_stop_transfer(fdctrl, 0x20, 0x00, 0x00);
1605 8977f3c1 bellard
            return;
1606 8977f3c1 bellard
        case 0x10:
1607 8977f3c1 bellard
            /* SCAN_EQUAL variants */
1608 8977f3c1 bellard
//            FLOPPY_DPRINTF("treat SCAN_EQUAL command\n");
1609 8977f3c1 bellard
            FLOPPY_ERROR("treat SCAN_EQUAL command\n");
1610 baca51fa bellard
            fdctrl_start_transfer(fdctrl, FD_DIR_SCANE);
1611 8977f3c1 bellard
            return;
1612 8977f3c1 bellard
        case 0x19:
1613 8977f3c1 bellard
            /* SCAN_LOW_OR_EQUAL variants */
1614 8977f3c1 bellard
//            FLOPPY_DPRINTF("treat SCAN_LOW_OR_EQUAL command\n");
1615 8977f3c1 bellard
            FLOPPY_ERROR("treat SCAN_LOW_OR_EQUAL command\n");
1616 baca51fa bellard
            fdctrl_start_transfer(fdctrl, FD_DIR_SCANL);
1617 8977f3c1 bellard
            return;
1618 8977f3c1 bellard
        case 0x1D:
1619 8977f3c1 bellard
            /* SCAN_HIGH_OR_EQUAL variants */
1620 8977f3c1 bellard
//            FLOPPY_DPRINTF("treat SCAN_HIGH_OR_EQUAL command\n");
1621 8977f3c1 bellard
            FLOPPY_ERROR("treat SCAN_HIGH_OR_EQUAL command\n");
1622 baca51fa bellard
            fdctrl_start_transfer(fdctrl, FD_DIR_SCANH);
1623 8977f3c1 bellard
            return;
1624 8977f3c1 bellard
        default:
1625 8977f3c1 bellard
            break;
1626 8977f3c1 bellard
        }
1627 baca51fa bellard
        switch (fdctrl->fifo[0] & 0x3F) {
1628 8977f3c1 bellard
        case 0x05:
1629 8977f3c1 bellard
            /* WRITE variants */
1630 baca51fa bellard
            FLOPPY_DPRINTF("treat WRITE command (%02x)\n", fdctrl->fifo[0]);
1631 baca51fa bellard
            fdctrl_start_transfer(fdctrl, FD_DIR_WRITE);
1632 8977f3c1 bellard
            return;
1633 8977f3c1 bellard
        case 0x09:
1634 8977f3c1 bellard
            /* WRITE_DELETED variants */
1635 8977f3c1 bellard
//            FLOPPY_DPRINTF("treat WRITE_DELETED command\n");
1636 8977f3c1 bellard
            FLOPPY_ERROR("treat WRITE_DELETED command\n");
1637 baca51fa bellard
            fdctrl_start_transfer_del(fdctrl, FD_DIR_WRITE);
1638 8977f3c1 bellard
            return;
1639 8977f3c1 bellard
        default:
1640 8977f3c1 bellard
            break;
1641 8977f3c1 bellard
        }
1642 baca51fa bellard
        switch (fdctrl->fifo[0]) {
1643 8977f3c1 bellard
        case 0x03:
1644 8977f3c1 bellard
            /* SPECIFY */
1645 8977f3c1 bellard
            FLOPPY_DPRINTF("treat SPECIFY command\n");
1646 baca51fa bellard
            fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1647 e309de25 bellard
            fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1648 baca51fa bellard
            fdctrl->dma_en = 1 - (fdctrl->fifo[2] & 1) ;
1649 8977f3c1 bellard
            /* No result back */
1650 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1651 8977f3c1 bellard
            break;
1652 8977f3c1 bellard
        case 0x04:
1653 8977f3c1 bellard
            /* SENSE_DRIVE_STATUS */
1654 8977f3c1 bellard
            FLOPPY_DPRINTF("treat SENSE_DRIVE_STATUS command\n");
1655 baca51fa bellard
            fdctrl->cur_drv = fdctrl->fifo[1] & 1;
1656 baca51fa bellard
            cur_drv = get_cur_drv(fdctrl);
1657 baca51fa bellard
            cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1658 8977f3c1 bellard
            /* 1 Byte status back */
1659 baca51fa bellard
            fdctrl->fifo[0] = (cur_drv->ro << 6) |
1660 8977f3c1 bellard
                (cur_drv->track == 0 ? 0x10 : 0x00) |
1661 890fa6be bellard
                (cur_drv->head << 2) |
1662 890fa6be bellard
                fdctrl->cur_drv |
1663 890fa6be bellard
                0x28;
1664 baca51fa bellard
            fdctrl_set_fifo(fdctrl, 1, 0);
1665 8977f3c1 bellard
            break;
1666 8977f3c1 bellard
        case 0x07:
1667 8977f3c1 bellard
            /* RECALIBRATE */
1668 8977f3c1 bellard
            FLOPPY_DPRINTF("treat RECALIBRATE command\n");
1669 baca51fa bellard
            fdctrl->cur_drv = fdctrl->fifo[1] & 1;
1670 baca51fa bellard
            cur_drv = get_cur_drv(fdctrl);
1671 8977f3c1 bellard
            fd_recalibrate(cur_drv);
1672 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1673 8977f3c1 bellard
            /* Raise Interrupt */
1674 baca51fa bellard
            fdctrl_raise_irq(fdctrl, 0x20);
1675 8977f3c1 bellard
            break;
1676 8977f3c1 bellard
        case 0x0F:
1677 8977f3c1 bellard
            /* SEEK */
1678 8977f3c1 bellard
            FLOPPY_DPRINTF("treat SEEK command\n");
1679 baca51fa bellard
            fdctrl->cur_drv = fdctrl->fifo[1] & 1;
1680 baca51fa bellard
            cur_drv = get_cur_drv(fdctrl);
1681 baca51fa bellard
            fd_start(cur_drv);
1682 baca51fa bellard
            if (fdctrl->fifo[2] <= cur_drv->track)
1683 8977f3c1 bellard
                cur_drv->dir = 1;
1684 8977f3c1 bellard
            else
1685 8977f3c1 bellard
                cur_drv->dir = 0;
1686 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1687 baca51fa bellard
            if (fdctrl->fifo[2] > cur_drv->max_track) {
1688 baca51fa bellard
                fdctrl_raise_irq(fdctrl, 0x60);
1689 8977f3c1 bellard
            } else {
1690 baca51fa bellard
                cur_drv->track = fdctrl->fifo[2];
1691 8977f3c1 bellard
                /* Raise Interrupt */
1692 baca51fa bellard
                fdctrl_raise_irq(fdctrl, 0x20);
1693 8977f3c1 bellard
            }
1694 8977f3c1 bellard
            break;
1695 8977f3c1 bellard
        case 0x12:
1696 8977f3c1 bellard
            /* PERPENDICULAR_MODE */
1697 8977f3c1 bellard
            FLOPPY_DPRINTF("treat PERPENDICULAR_MODE command\n");
1698 baca51fa bellard
            if (fdctrl->fifo[1] & 0x80)
1699 baca51fa bellard
                cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1700 8977f3c1 bellard
            /* No result back */
1701 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1702 8977f3c1 bellard
            break;
1703 8977f3c1 bellard
        case 0x13:
1704 8977f3c1 bellard
            /* CONFIGURE */
1705 8977f3c1 bellard
            FLOPPY_DPRINTF("treat CONFIGURE command\n");
1706 baca51fa bellard
            fdctrl->config = fdctrl->fifo[2];
1707 baca51fa bellard
            fdctrl->precomp_trk =  fdctrl->fifo[3];
1708 8977f3c1 bellard
            /* No result back */
1709 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1710 8977f3c1 bellard
            break;
1711 8977f3c1 bellard
        case 0x17:
1712 8977f3c1 bellard
            /* POWERDOWN_MODE */
1713 8977f3c1 bellard
            FLOPPY_DPRINTF("treat POWERDOWN_MODE command\n");
1714 baca51fa bellard
            fdctrl->pwrd = fdctrl->fifo[1];
1715 baca51fa bellard
            fdctrl->fifo[0] = fdctrl->fifo[1];
1716 baca51fa bellard
            fdctrl_set_fifo(fdctrl, 1, 1);
1717 8977f3c1 bellard
            break;
1718 8977f3c1 bellard
        case 0x33:
1719 8977f3c1 bellard
            /* OPTION */
1720 8977f3c1 bellard
            FLOPPY_DPRINTF("treat OPTION command\n");
1721 8977f3c1 bellard
            /* No result back */
1722 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1723 8977f3c1 bellard
            break;
1724 8977f3c1 bellard
        case 0x42:
1725 8977f3c1 bellard
            /* READ_TRACK */
1726 8977f3c1 bellard
//            FLOPPY_DPRINTF("treat READ_TRACK command\n");
1727 8977f3c1 bellard
            FLOPPY_ERROR("treat READ_TRACK command\n");
1728 baca51fa bellard
            fdctrl_start_transfer(fdctrl, FD_DIR_READ);
1729 8977f3c1 bellard
            break;
1730 8977f3c1 bellard
        case 0x4A:
1731 8977f3c1 bellard
                /* READ_ID */
1732 baca51fa bellard
            FLOPPY_DPRINTF("treat READ_ID command\n");
1733 ed5fd2cc bellard
            /* XXX: should set main status register to busy */
1734 890fa6be bellard
            cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1735 ed5fd2cc bellard
            qemu_mod_timer(fdctrl->result_timer, 
1736 ed5fd2cc bellard
                           qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1737 8977f3c1 bellard
            break;
1738 8977f3c1 bellard
        case 0x4C:
1739 8977f3c1 bellard
            /* RESTORE */
1740 8977f3c1 bellard
            FLOPPY_DPRINTF("treat RESTORE command\n");
1741 8977f3c1 bellard
            /* Drives position */
1742 baca51fa bellard
            drv0(fdctrl)->track = fdctrl->fifo[3];
1743 baca51fa bellard
            drv1(fdctrl)->track = fdctrl->fifo[4];
1744 8977f3c1 bellard
            /* timers */
1745 baca51fa bellard
            fdctrl->timer0 = fdctrl->fifo[7];
1746 baca51fa bellard
            fdctrl->timer1 = fdctrl->fifo[8];
1747 baca51fa bellard
            cur_drv->last_sect = fdctrl->fifo[9];
1748 baca51fa bellard
            fdctrl->lock = fdctrl->fifo[10] >> 7;
1749 baca51fa bellard
            cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1750 baca51fa bellard
            fdctrl->config = fdctrl->fifo[11];
1751 baca51fa bellard
            fdctrl->precomp_trk = fdctrl->fifo[12];
1752 baca51fa bellard
            fdctrl->pwrd = fdctrl->fifo[13];
1753 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1754 8977f3c1 bellard
            break;
1755 8977f3c1 bellard
        case 0x4D:
1756 8977f3c1 bellard
            /* FORMAT_TRACK */
1757 baca51fa bellard
            FLOPPY_DPRINTF("treat FORMAT_TRACK command\n");
1758 baca51fa bellard
            fdctrl->cur_drv = fdctrl->fifo[1] & 1;
1759 baca51fa bellard
            cur_drv = get_cur_drv(fdctrl);
1760 baca51fa bellard
            fdctrl->data_state |= FD_STATE_FORMAT;
1761 baca51fa bellard
            if (fdctrl->fifo[0] & 0x80)
1762 baca51fa bellard
                fdctrl->data_state |= FD_STATE_MULTI;
1763 baca51fa bellard
            else
1764 baca51fa bellard
                fdctrl->data_state &= ~FD_STATE_MULTI;
1765 baca51fa bellard
            fdctrl->data_state &= ~FD_STATE_SEEK;
1766 baca51fa bellard
            cur_drv->bps =
1767 baca51fa bellard
                fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1768 baca51fa bellard
#if 0
1769 baca51fa bellard
            cur_drv->last_sect =
1770 baca51fa bellard
                cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1771 baca51fa bellard
                fdctrl->fifo[3] / 2;
1772 baca51fa bellard
#else
1773 baca51fa bellard
            cur_drv->last_sect = fdctrl->fifo[3];
1774 baca51fa bellard
#endif
1775 b9209030 ths
            /* TODO: implement format using DMA expected by the Bochs BIOS
1776 b9209030 ths
             * and Linux fdformat (read 3 bytes per sector via DMA and fill
1777 b9209030 ths
             * the sector with the specified fill byte
1778 baca51fa bellard
             */
1779 baca51fa bellard
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1780 baca51fa bellard
            fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1781 8977f3c1 bellard
            break;
1782 8977f3c1 bellard
        case 0x8E:
1783 8977f3c1 bellard
            /* DRIVE_SPECIFICATION_COMMAND */
1784 8977f3c1 bellard
            FLOPPY_DPRINTF("treat DRIVE_SPECIFICATION_COMMAND command\n");
1785 baca51fa bellard
            if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1786 8977f3c1 bellard
                /* Command parameters done */
1787 baca51fa bellard
                if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1788 baca51fa bellard
                    fdctrl->fifo[0] = fdctrl->fifo[1];
1789 baca51fa bellard
                    fdctrl->fifo[2] = 0;
1790 baca51fa bellard
                    fdctrl->fifo[3] = 0;
1791 baca51fa bellard
                    fdctrl_set_fifo(fdctrl, 4, 1);
1792 8977f3c1 bellard
                } else {
1793 baca51fa bellard
                    fdctrl_reset_fifo(fdctrl);
1794 8977f3c1 bellard
                }
1795 baca51fa bellard
            } else if (fdctrl->data_len > 7) {
1796 8977f3c1 bellard
                /* ERROR */
1797 baca51fa bellard
                fdctrl->fifo[0] = 0x80 |
1798 baca51fa bellard
                    (cur_drv->head << 2) | fdctrl->cur_drv;
1799 baca51fa bellard
                fdctrl_set_fifo(fdctrl, 1, 1);
1800 8977f3c1 bellard
            }
1801 8977f3c1 bellard
            break;
1802 8977f3c1 bellard
        case 0x8F:
1803 8977f3c1 bellard
            /* RELATIVE_SEEK_OUT */
1804 8977f3c1 bellard
            FLOPPY_DPRINTF("treat RELATIVE_SEEK_OUT command\n");
1805 baca51fa bellard
            fdctrl->cur_drv = fdctrl->fifo[1] & 1;
1806 baca51fa bellard
            cur_drv = get_cur_drv(fdctrl);
1807 baca51fa bellard
            fd_start(cur_drv);
1808 8977f3c1 bellard
                cur_drv->dir = 0;
1809 baca51fa bellard
            if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1810 baca51fa bellard
                cur_drv->track = cur_drv->max_track - 1;
1811 baca51fa bellard
            } else {
1812 baca51fa bellard
                cur_drv->track += fdctrl->fifo[2];
1813 8977f3c1 bellard
            }
1814 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1815 baca51fa bellard
            fdctrl_raise_irq(fdctrl, 0x20);
1816 8977f3c1 bellard
            break;
1817 8977f3c1 bellard
        case 0xCD:
1818 8977f3c1 bellard
            /* FORMAT_AND_WRITE */
1819 8977f3c1 bellard
//                FLOPPY_DPRINTF("treat FORMAT_AND_WRITE command\n");
1820 8977f3c1 bellard
            FLOPPY_ERROR("treat FORMAT_AND_WRITE command\n");
1821 baca51fa bellard
            fdctrl_unimplemented(fdctrl);
1822 8977f3c1 bellard
            break;
1823 8977f3c1 bellard
        case 0xCF:
1824 8977f3c1 bellard
                /* RELATIVE_SEEK_IN */
1825 8977f3c1 bellard
            FLOPPY_DPRINTF("treat RELATIVE_SEEK_IN command\n");
1826 baca51fa bellard
            fdctrl->cur_drv = fdctrl->fifo[1] & 1;
1827 baca51fa bellard
            cur_drv = get_cur_drv(fdctrl);
1828 baca51fa bellard
            fd_start(cur_drv);
1829 8977f3c1 bellard
                cur_drv->dir = 1;
1830 baca51fa bellard
            if (fdctrl->fifo[2] > cur_drv->track) {
1831 baca51fa bellard
                cur_drv->track = 0;
1832 baca51fa bellard
            } else {
1833 baca51fa bellard
                cur_drv->track -= fdctrl->fifo[2];
1834 8977f3c1 bellard
            }
1835 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1836 baca51fa bellard
            /* Raise Interrupt */
1837 baca51fa bellard
            fdctrl_raise_irq(fdctrl, 0x20);
1838 8977f3c1 bellard
            break;
1839 8977f3c1 bellard
        }
1840 8977f3c1 bellard
    }
1841 8977f3c1 bellard
}
1842 ed5fd2cc bellard
1843 ed5fd2cc bellard
static void fdctrl_result_timer(void *opaque)
1844 ed5fd2cc bellard
{
1845 ed5fd2cc bellard
    fdctrl_t *fdctrl = opaque;
1846 ed5fd2cc bellard
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1847 ed5fd2cc bellard
}