Statistics
| Branch: | Revision:

root / target-sparc / op.c @ 5dcb6b91

History | View | Annotate | Download (47.3 kB)

1 7a3f1944 bellard
/*
2 7a3f1944 bellard
   SPARC micro operations
3 7a3f1944 bellard

4 7a3f1944 bellard
   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 7a3f1944 bellard

6 7a3f1944 bellard
   This library is free software; you can redistribute it and/or
7 7a3f1944 bellard
   modify it under the terms of the GNU Lesser General Public
8 7a3f1944 bellard
   License as published by the Free Software Foundation; either
9 7a3f1944 bellard
   version 2 of the License, or (at your option) any later version.
10 7a3f1944 bellard

11 7a3f1944 bellard
   This library is distributed in the hope that it will be useful,
12 7a3f1944 bellard
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13 7a3f1944 bellard
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 7a3f1944 bellard
   Lesser General Public License for more details.
15 7a3f1944 bellard

16 7a3f1944 bellard
   You should have received a copy of the GNU Lesser General Public
17 7a3f1944 bellard
   License along with this library; if not, write to the Free Software
18 7a3f1944 bellard
   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19 7a3f1944 bellard
*/
20 7a3f1944 bellard
21 7a3f1944 bellard
#include "exec.h"
22 7a3f1944 bellard
23 cf495bcf bellard
 /*XXX*/
24 7a3f1944 bellard
#define REGNAME g0
25 7a3f1944 bellard
#define REG (env->gregs[0])
26 7a3f1944 bellard
#include "op_template.h"
27 7a3f1944 bellard
#define REGNAME g1
28 7a3f1944 bellard
#define REG (env->gregs[1])
29 7a3f1944 bellard
#include "op_template.h"
30 7a3f1944 bellard
#define REGNAME g2
31 7a3f1944 bellard
#define REG (env->gregs[2])
32 7a3f1944 bellard
#include "op_template.h"
33 7a3f1944 bellard
#define REGNAME g3
34 7a3f1944 bellard
#define REG (env->gregs[3])
35 7a3f1944 bellard
#include "op_template.h"
36 7a3f1944 bellard
#define REGNAME g4
37 7a3f1944 bellard
#define REG (env->gregs[4])
38 7a3f1944 bellard
#include "op_template.h"
39 7a3f1944 bellard
#define REGNAME g5
40 7a3f1944 bellard
#define REG (env->gregs[5])
41 7a3f1944 bellard
#include "op_template.h"
42 7a3f1944 bellard
#define REGNAME g6
43 7a3f1944 bellard
#define REG (env->gregs[6])
44 7a3f1944 bellard
#include "op_template.h"
45 7a3f1944 bellard
#define REGNAME g7
46 7a3f1944 bellard
#define REG (env->gregs[7])
47 7a3f1944 bellard
#include "op_template.h"
48 7a3f1944 bellard
#define REGNAME i0
49 3475187d bellard
#define REG (REGWPTR[16])
50 7a3f1944 bellard
#include "op_template.h"
51 7a3f1944 bellard
#define REGNAME i1
52 3475187d bellard
#define REG (REGWPTR[17])
53 7a3f1944 bellard
#include "op_template.h"
54 7a3f1944 bellard
#define REGNAME i2
55 3475187d bellard
#define REG (REGWPTR[18])
56 7a3f1944 bellard
#include "op_template.h"
57 7a3f1944 bellard
#define REGNAME i3
58 3475187d bellard
#define REG (REGWPTR[19])
59 7a3f1944 bellard
#include "op_template.h"
60 7a3f1944 bellard
#define REGNAME i4
61 3475187d bellard
#define REG (REGWPTR[20])
62 7a3f1944 bellard
#include "op_template.h"
63 7a3f1944 bellard
#define REGNAME i5
64 3475187d bellard
#define REG (REGWPTR[21])
65 7a3f1944 bellard
#include "op_template.h"
66 7a3f1944 bellard
#define REGNAME i6
67 3475187d bellard
#define REG (REGWPTR[22])
68 7a3f1944 bellard
#include "op_template.h"
69 7a3f1944 bellard
#define REGNAME i7
70 3475187d bellard
#define REG (REGWPTR[23])
71 7a3f1944 bellard
#include "op_template.h"
72 7a3f1944 bellard
#define REGNAME l0
73 3475187d bellard
#define REG (REGWPTR[8])
74 7a3f1944 bellard
#include "op_template.h"
75 7a3f1944 bellard
#define REGNAME l1
76 3475187d bellard
#define REG (REGWPTR[9])
77 7a3f1944 bellard
#include "op_template.h"
78 7a3f1944 bellard
#define REGNAME l2
79 3475187d bellard
#define REG (REGWPTR[10])
80 7a3f1944 bellard
#include "op_template.h"
81 7a3f1944 bellard
#define REGNAME l3
82 3475187d bellard
#define REG (REGWPTR[11])
83 7a3f1944 bellard
#include "op_template.h"
84 7a3f1944 bellard
#define REGNAME l4
85 3475187d bellard
#define REG (REGWPTR[12])
86 7a3f1944 bellard
#include "op_template.h"
87 7a3f1944 bellard
#define REGNAME l5
88 3475187d bellard
#define REG (REGWPTR[13])
89 7a3f1944 bellard
#include "op_template.h"
90 7a3f1944 bellard
#define REGNAME l6
91 3475187d bellard
#define REG (REGWPTR[14])
92 7a3f1944 bellard
#include "op_template.h"
93 7a3f1944 bellard
#define REGNAME l7
94 3475187d bellard
#define REG (REGWPTR[15])
95 7a3f1944 bellard
#include "op_template.h"
96 7a3f1944 bellard
#define REGNAME o0
97 3475187d bellard
#define REG (REGWPTR[0])
98 7a3f1944 bellard
#include "op_template.h"
99 7a3f1944 bellard
#define REGNAME o1
100 3475187d bellard
#define REG (REGWPTR[1])
101 7a3f1944 bellard
#include "op_template.h"
102 7a3f1944 bellard
#define REGNAME o2
103 3475187d bellard
#define REG (REGWPTR[2])
104 7a3f1944 bellard
#include "op_template.h"
105 7a3f1944 bellard
#define REGNAME o3
106 3475187d bellard
#define REG (REGWPTR[3])
107 7a3f1944 bellard
#include "op_template.h"
108 7a3f1944 bellard
#define REGNAME o4
109 3475187d bellard
#define REG (REGWPTR[4])
110 7a3f1944 bellard
#include "op_template.h"
111 7a3f1944 bellard
#define REGNAME o5
112 3475187d bellard
#define REG (REGWPTR[5])
113 7a3f1944 bellard
#include "op_template.h"
114 7a3f1944 bellard
#define REGNAME o6
115 3475187d bellard
#define REG (REGWPTR[6])
116 7a3f1944 bellard
#include "op_template.h"
117 7a3f1944 bellard
#define REGNAME o7
118 3475187d bellard
#define REG (REGWPTR[7])
119 7a3f1944 bellard
#include "op_template.h"
120 e8af50a3 bellard
121 e8af50a3 bellard
#define REGNAME f0
122 e8af50a3 bellard
#define REG (env->fpr[0])
123 e8af50a3 bellard
#include "fop_template.h"
124 e8af50a3 bellard
#define REGNAME f1
125 e8af50a3 bellard
#define REG (env->fpr[1])
126 e8af50a3 bellard
#include "fop_template.h"
127 e8af50a3 bellard
#define REGNAME f2
128 e8af50a3 bellard
#define REG (env->fpr[2])
129 e8af50a3 bellard
#include "fop_template.h"
130 e8af50a3 bellard
#define REGNAME f3
131 e8af50a3 bellard
#define REG (env->fpr[3])
132 e8af50a3 bellard
#include "fop_template.h"
133 e8af50a3 bellard
#define REGNAME f4
134 e8af50a3 bellard
#define REG (env->fpr[4])
135 e8af50a3 bellard
#include "fop_template.h"
136 e8af50a3 bellard
#define REGNAME f5
137 e8af50a3 bellard
#define REG (env->fpr[5])
138 e8af50a3 bellard
#include "fop_template.h"
139 e8af50a3 bellard
#define REGNAME f6
140 e8af50a3 bellard
#define REG (env->fpr[6])
141 e8af50a3 bellard
#include "fop_template.h"
142 e8af50a3 bellard
#define REGNAME f7
143 e8af50a3 bellard
#define REG (env->fpr[7])
144 e8af50a3 bellard
#include "fop_template.h"
145 e8af50a3 bellard
#define REGNAME f8
146 e8af50a3 bellard
#define REG (env->fpr[8])
147 e8af50a3 bellard
#include "fop_template.h"
148 e8af50a3 bellard
#define REGNAME f9
149 e8af50a3 bellard
#define REG (env->fpr[9])
150 e8af50a3 bellard
#include "fop_template.h"
151 e8af50a3 bellard
#define REGNAME f10
152 e8af50a3 bellard
#define REG (env->fpr[10])
153 e8af50a3 bellard
#include "fop_template.h"
154 e8af50a3 bellard
#define REGNAME f11
155 e8af50a3 bellard
#define REG (env->fpr[11])
156 e8af50a3 bellard
#include "fop_template.h"
157 e8af50a3 bellard
#define REGNAME f12
158 e8af50a3 bellard
#define REG (env->fpr[12])
159 e8af50a3 bellard
#include "fop_template.h"
160 e8af50a3 bellard
#define REGNAME f13
161 e8af50a3 bellard
#define REG (env->fpr[13])
162 e8af50a3 bellard
#include "fop_template.h"
163 e8af50a3 bellard
#define REGNAME f14
164 e8af50a3 bellard
#define REG (env->fpr[14])
165 e8af50a3 bellard
#include "fop_template.h"
166 e8af50a3 bellard
#define REGNAME f15
167 e8af50a3 bellard
#define REG (env->fpr[15])
168 e8af50a3 bellard
#include "fop_template.h"
169 e8af50a3 bellard
#define REGNAME f16
170 e8af50a3 bellard
#define REG (env->fpr[16])
171 e8af50a3 bellard
#include "fop_template.h"
172 e8af50a3 bellard
#define REGNAME f17
173 e8af50a3 bellard
#define REG (env->fpr[17])
174 e8af50a3 bellard
#include "fop_template.h"
175 e8af50a3 bellard
#define REGNAME f18
176 e8af50a3 bellard
#define REG (env->fpr[18])
177 e8af50a3 bellard
#include "fop_template.h"
178 e8af50a3 bellard
#define REGNAME f19
179 e8af50a3 bellard
#define REG (env->fpr[19])
180 e8af50a3 bellard
#include "fop_template.h"
181 e8af50a3 bellard
#define REGNAME f20
182 e8af50a3 bellard
#define REG (env->fpr[20])
183 e8af50a3 bellard
#include "fop_template.h"
184 e8af50a3 bellard
#define REGNAME f21
185 e8af50a3 bellard
#define REG (env->fpr[21])
186 e8af50a3 bellard
#include "fop_template.h"
187 e8af50a3 bellard
#define REGNAME f22
188 e8af50a3 bellard
#define REG (env->fpr[22])
189 e8af50a3 bellard
#include "fop_template.h"
190 e8af50a3 bellard
#define REGNAME f23
191 e8af50a3 bellard
#define REG (env->fpr[23])
192 e8af50a3 bellard
#include "fop_template.h"
193 e8af50a3 bellard
#define REGNAME f24
194 e8af50a3 bellard
#define REG (env->fpr[24])
195 e8af50a3 bellard
#include "fop_template.h"
196 e8af50a3 bellard
#define REGNAME f25
197 e8af50a3 bellard
#define REG (env->fpr[25])
198 e8af50a3 bellard
#include "fop_template.h"
199 e8af50a3 bellard
#define REGNAME f26
200 e8af50a3 bellard
#define REG (env->fpr[26])
201 e8af50a3 bellard
#include "fop_template.h"
202 e8af50a3 bellard
#define REGNAME f27
203 e8af50a3 bellard
#define REG (env->fpr[27])
204 e8af50a3 bellard
#include "fop_template.h"
205 e8af50a3 bellard
#define REGNAME f28
206 e8af50a3 bellard
#define REG (env->fpr[28])
207 e8af50a3 bellard
#include "fop_template.h"
208 e8af50a3 bellard
#define REGNAME f29
209 e8af50a3 bellard
#define REG (env->fpr[29])
210 e8af50a3 bellard
#include "fop_template.h"
211 e8af50a3 bellard
#define REGNAME f30
212 e8af50a3 bellard
#define REG (env->fpr[30])
213 e8af50a3 bellard
#include "fop_template.h"
214 e8af50a3 bellard
#define REGNAME f31
215 e8af50a3 bellard
#define REG (env->fpr[31])
216 e8af50a3 bellard
#include "fop_template.h"
217 e8af50a3 bellard
218 3475187d bellard
#ifdef TARGET_SPARC64
219 3475187d bellard
#define REGNAME f32
220 3475187d bellard
#define REG (env->fpr[32])
221 3475187d bellard
#include "fop_template.h"
222 3475187d bellard
#define REGNAME f34
223 3475187d bellard
#define REG (env->fpr[34])
224 3475187d bellard
#include "fop_template.h"
225 3475187d bellard
#define REGNAME f36
226 3475187d bellard
#define REG (env->fpr[36])
227 3475187d bellard
#include "fop_template.h"
228 3475187d bellard
#define REGNAME f38
229 3475187d bellard
#define REG (env->fpr[38])
230 3475187d bellard
#include "fop_template.h"
231 3475187d bellard
#define REGNAME f40
232 3475187d bellard
#define REG (env->fpr[40])
233 3475187d bellard
#include "fop_template.h"
234 3475187d bellard
#define REGNAME f42
235 3475187d bellard
#define REG (env->fpr[42])
236 3475187d bellard
#include "fop_template.h"
237 3475187d bellard
#define REGNAME f44
238 3475187d bellard
#define REG (env->fpr[44])
239 3475187d bellard
#include "fop_template.h"
240 3475187d bellard
#define REGNAME f46
241 3475187d bellard
#define REG (env->fpr[46])
242 3475187d bellard
#include "fop_template.h"
243 3475187d bellard
#define REGNAME f48
244 3475187d bellard
#define REG (env->fpr[47])
245 3475187d bellard
#include "fop_template.h"
246 3475187d bellard
#define REGNAME f50
247 3475187d bellard
#define REG (env->fpr[50])
248 3475187d bellard
#include "fop_template.h"
249 3475187d bellard
#define REGNAME f52
250 3475187d bellard
#define REG (env->fpr[52])
251 3475187d bellard
#include "fop_template.h"
252 3475187d bellard
#define REGNAME f54
253 3475187d bellard
#define REG (env->fpr[54])
254 3475187d bellard
#include "fop_template.h"
255 3475187d bellard
#define REGNAME f56
256 3475187d bellard
#define REG (env->fpr[56])
257 3475187d bellard
#include "fop_template.h"
258 3475187d bellard
#define REGNAME f58
259 3475187d bellard
#define REG (env->fpr[58])
260 3475187d bellard
#include "fop_template.h"
261 3475187d bellard
#define REGNAME f60
262 3475187d bellard
#define REG (env->fpr[60])
263 3475187d bellard
#include "fop_template.h"
264 3475187d bellard
#define REGNAME f62
265 3475187d bellard
#define REG (env->fpr[62])
266 3475187d bellard
#include "fop_template.h"
267 3475187d bellard
#endif
268 3475187d bellard
269 3475187d bellard
#ifdef TARGET_SPARC64
270 3475187d bellard
#ifdef WORDS_BIGENDIAN
271 3475187d bellard
typedef union UREG64 {
272 3475187d bellard
    struct { uint16_t v3, v2, v1, v0; } w;
273 3475187d bellard
    struct { uint32_t v1, v0; } l;
274 3475187d bellard
    uint64_t q;
275 3475187d bellard
} UREG64;
276 3475187d bellard
#else
277 3475187d bellard
typedef union UREG64 {
278 3475187d bellard
    struct { uint16_t v0, v1, v2, v3; } w;
279 3475187d bellard
    struct { uint32_t v0, v1; } l;
280 3475187d bellard
    uint64_t q;
281 3475187d bellard
} UREG64;
282 3475187d bellard
#endif
283 3475187d bellard
284 3475187d bellard
#define PARAMQ1 \
285 3475187d bellard
({\
286 3475187d bellard
    UREG64 __p;\
287 3475187d bellard
    __p.l.v1 = PARAM1;\
288 3475187d bellard
    __p.l.v0 = PARAM2;\
289 3475187d bellard
    __p.q;\
290 3475187d bellard
}) 
291 3475187d bellard
292 3475187d bellard
void OPPROTO op_movq_T0_im64(void)
293 3475187d bellard
{
294 3475187d bellard
    T0 = PARAMQ1;
295 3475187d bellard
}
296 3475187d bellard
297 3475187d bellard
void OPPROTO op_movq_T1_im64(void)
298 3475187d bellard
{
299 3475187d bellard
    T1 = PARAMQ1;
300 3475187d bellard
}
301 3475187d bellard
302 3475187d bellard
#define XFLAG_SET(x) ((env->xcc&x)?1:0)
303 3475187d bellard
304 3475187d bellard
#else
305 7a3f1944 bellard
#define EIP (env->pc)
306 3475187d bellard
#endif
307 7a3f1944 bellard
308 af7bf89b bellard
#define FLAG_SET(x) ((env->psr&x)?1:0)
309 cf495bcf bellard
310 7a3f1944 bellard
void OPPROTO op_movl_T0_0(void)
311 7a3f1944 bellard
{
312 cf495bcf bellard
    T0 = 0;
313 7a3f1944 bellard
}
314 7a3f1944 bellard
315 7a3f1944 bellard
void OPPROTO op_movl_T0_im(void)
316 7a3f1944 bellard
{
317 3475187d bellard
    T0 = (uint32_t)PARAM1;
318 7a3f1944 bellard
}
319 7a3f1944 bellard
320 7a3f1944 bellard
void OPPROTO op_movl_T1_im(void)
321 7a3f1944 bellard
{
322 3475187d bellard
    T1 = (uint32_t)PARAM1;
323 7a3f1944 bellard
}
324 7a3f1944 bellard
325 7a3f1944 bellard
void OPPROTO op_movl_T2_im(void)
326 7a3f1944 bellard
{
327 3475187d bellard
    T2 = (uint32_t)PARAM1;
328 3475187d bellard
}
329 3475187d bellard
330 3475187d bellard
void OPPROTO op_movl_T0_sim(void)
331 3475187d bellard
{
332 3475187d bellard
    T0 = (int32_t)PARAM1;
333 3475187d bellard
}
334 3475187d bellard
335 3475187d bellard
void OPPROTO op_movl_T1_sim(void)
336 3475187d bellard
{
337 3475187d bellard
    T1 = (int32_t)PARAM1;
338 3475187d bellard
}
339 3475187d bellard
340 3475187d bellard
void OPPROTO op_movl_T2_sim(void)
341 3475187d bellard
{
342 3475187d bellard
    T2 = (int32_t)PARAM1;
343 3475187d bellard
}
344 3475187d bellard
345 3475187d bellard
void OPPROTO op_movl_T0_env(void)
346 3475187d bellard
{
347 3475187d bellard
    T0 = *(uint32_t *)((char *)env + PARAM1);
348 3475187d bellard
}
349 3475187d bellard
350 3475187d bellard
void OPPROTO op_movl_env_T0(void)
351 3475187d bellard
{
352 3475187d bellard
    *(uint32_t *)((char *)env + PARAM1) = T0;
353 3475187d bellard
}
354 3475187d bellard
355 3475187d bellard
void OPPROTO op_movtl_T0_env(void)
356 3475187d bellard
{
357 3475187d bellard
    T0 = *(target_ulong *)((char *)env + PARAM1);
358 3475187d bellard
}
359 3475187d bellard
360 3475187d bellard
void OPPROTO op_movtl_env_T0(void)
361 3475187d bellard
{
362 3475187d bellard
    *(target_ulong *)((char *)env + PARAM1) = T0;
363 7a3f1944 bellard
}
364 7a3f1944 bellard
365 af7bf89b bellard
void OPPROTO op_add_T1_T0(void)
366 7a3f1944 bellard
{
367 af7bf89b bellard
    T0 += T1;
368 7a3f1944 bellard
}
369 7a3f1944 bellard
370 af7bf89b bellard
void OPPROTO op_add_T1_T0_cc(void)
371 7a3f1944 bellard
{
372 af7bf89b bellard
    target_ulong src1;
373 7a3f1944 bellard
374 af7bf89b bellard
    src1 = T0;
375 af7bf89b bellard
    T0 += T1;
376 af7bf89b bellard
    env->psr = 0;
377 3475187d bellard
#ifdef TARGET_SPARC64
378 3475187d bellard
    if (!(T0 & 0xffffffff))
379 3475187d bellard
        env->psr |= PSR_ZERO;
380 3475187d bellard
    if ((int32_t) T0 < 0)
381 3475187d bellard
        env->psr |= PSR_NEG;
382 bb3911a6 bellard
    if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
383 3475187d bellard
        env->psr |= PSR_CARRY;
384 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
385 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
386 3475187d bellard
        env->psr |= PSR_OVF;
387 3475187d bellard
388 3475187d bellard
    env->xcc = 0;
389 3475187d bellard
    if (!T0)
390 3475187d bellard
        env->xcc |= PSR_ZERO;
391 3475187d bellard
    if ((int64_t) T0 < 0)
392 3475187d bellard
        env->xcc |= PSR_NEG;
393 3475187d bellard
    if (T0 < src1)
394 3475187d bellard
        env->xcc |= PSR_CARRY;
395 3475187d bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
396 3475187d bellard
        env->xcc |= PSR_OVF;
397 3475187d bellard
#else
398 af7bf89b bellard
    if (!T0)
399 af7bf89b bellard
        env->psr |= PSR_ZERO;
400 af7bf89b bellard
    if ((int32_t) T0 < 0)
401 af7bf89b bellard
        env->psr |= PSR_NEG;
402 af7bf89b bellard
    if (T0 < src1)
403 af7bf89b bellard
        env->psr |= PSR_CARRY;
404 af7bf89b bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
405 af7bf89b bellard
        env->psr |= PSR_OVF;
406 3475187d bellard
#endif
407 af7bf89b bellard
    FORCE_RET();
408 7a3f1944 bellard
}
409 7a3f1944 bellard
410 af7bf89b bellard
void OPPROTO op_addx_T1_T0(void)
411 7a3f1944 bellard
{
412 af7bf89b bellard
    T0 += T1 + FLAG_SET(PSR_CARRY);
413 7a3f1944 bellard
}
414 7a3f1944 bellard
415 af7bf89b bellard
void OPPROTO op_addx_T1_T0_cc(void)
416 7a3f1944 bellard
{
417 af7bf89b bellard
    target_ulong src1;
418 cf495bcf bellard
    src1 = T0;
419 b854608e bellard
    if (FLAG_SET(PSR_CARRY))
420 b854608e bellard
    {
421 b854608e bellard
      T0 += T1 + 1;
422 b854608e bellard
      env->psr = 0;
423 b854608e bellard
#ifdef TARGET_SPARC64
424 b854608e bellard
      if ((T0 & 0xffffffff) <= (src1 & 0xffffffff))
425 b854608e bellard
        env->psr |= PSR_CARRY;
426 b854608e bellard
      env->xcc = 0;
427 b854608e bellard
      if (T0 <= src1)
428 b854608e bellard
        env->xcc |= PSR_CARRY;
429 b854608e bellard
#else
430 b854608e bellard
      if (T0 <= src1)
431 b854608e bellard
        env->psr |= PSR_CARRY;
432 b854608e bellard
#endif
433 b854608e bellard
    }
434 b854608e bellard
    else
435 b854608e bellard
    {
436 b854608e bellard
      T0 += T1;
437 b854608e bellard
      env->psr = 0;
438 b854608e bellard
#ifdef TARGET_SPARC64
439 b854608e bellard
      if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
440 b854608e bellard
        env->psr |= PSR_CARRY;
441 b854608e bellard
      env->xcc = 0;
442 b854608e bellard
      if (T0 < src1)
443 b854608e bellard
        env->xcc |= PSR_CARRY;
444 b854608e bellard
#else
445 b854608e bellard
      if (T0 < src1)
446 b854608e bellard
        env->psr |= PSR_CARRY;
447 b854608e bellard
#endif
448 b854608e bellard
    }
449 3475187d bellard
#ifdef TARGET_SPARC64
450 3475187d bellard
    if (!(T0 & 0xffffffff))
451 3475187d bellard
        env->psr |= PSR_ZERO;
452 3475187d bellard
    if ((int32_t) T0 < 0)
453 3475187d bellard
        env->psr |= PSR_NEG;
454 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
455 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
456 3475187d bellard
        env->psr |= PSR_OVF;
457 3475187d bellard
458 3475187d bellard
    if (!T0)
459 3475187d bellard
        env->xcc |= PSR_ZERO;
460 3475187d bellard
    if ((int64_t) T0 < 0)
461 3475187d bellard
        env->xcc |= PSR_NEG;
462 3475187d bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
463 3475187d bellard
        env->xcc |= PSR_OVF;
464 3475187d bellard
#else
465 cf495bcf bellard
    if (!T0)
466 cf495bcf bellard
        env->psr |= PSR_ZERO;
467 af7bf89b bellard
    if ((int32_t) T0 < 0)
468 cf495bcf bellard
        env->psr |= PSR_NEG;
469 cf495bcf bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
470 cf495bcf bellard
        env->psr |= PSR_OVF;
471 3475187d bellard
#endif
472 cf495bcf bellard
    FORCE_RET();
473 7a3f1944 bellard
}
474 7a3f1944 bellard
475 e32f879d blueswir1
void OPPROTO op_tadd_T1_T0_cc(void)
476 e32f879d blueswir1
{
477 e32f879d blueswir1
    target_ulong src1;
478 e32f879d blueswir1
479 e32f879d blueswir1
    src1 = T0;
480 e32f879d blueswir1
    T0 += T1;
481 e32f879d blueswir1
    env->psr = 0;
482 e32f879d blueswir1
#ifdef TARGET_SPARC64
483 e32f879d blueswir1
    if (!(T0 & 0xffffffff))
484 e32f879d blueswir1
        env->psr |= PSR_ZERO;
485 e32f879d blueswir1
    if ((int32_t) T0 < 0)
486 e32f879d blueswir1
        env->psr |= PSR_NEG;
487 e32f879d blueswir1
    if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
488 e32f879d blueswir1
        env->psr |= PSR_CARRY;
489 e32f879d blueswir1
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
490 e32f879d blueswir1
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
491 e32f879d blueswir1
        env->psr |= PSR_OVF;
492 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
493 e32f879d blueswir1
        env->psr |= PSR_OVF;
494 e32f879d blueswir1
495 e32f879d blueswir1
    env->xcc = 0;
496 e32f879d blueswir1
    if (!T0)
497 e32f879d blueswir1
        env->xcc |= PSR_ZERO;
498 e32f879d blueswir1
    if ((int64_t) T0 < 0)
499 e32f879d blueswir1
        env->xcc |= PSR_NEG;
500 e32f879d blueswir1
    if (T0 < src1)
501 e32f879d blueswir1
        env->xcc |= PSR_CARRY;
502 e32f879d blueswir1
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
503 e32f879d blueswir1
        env->xcc |= PSR_OVF;
504 e32f879d blueswir1
#else
505 e32f879d blueswir1
    if (!T0)
506 e32f879d blueswir1
        env->psr |= PSR_ZERO;
507 e32f879d blueswir1
    if ((int32_t) T0 < 0)
508 e32f879d blueswir1
        env->psr |= PSR_NEG;
509 e32f879d blueswir1
    if (T0 < src1)
510 e32f879d blueswir1
        env->psr |= PSR_CARRY;
511 e32f879d blueswir1
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
512 e32f879d blueswir1
        env->psr |= PSR_OVF;
513 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
514 e32f879d blueswir1
        env->psr |= PSR_OVF;
515 e32f879d blueswir1
#endif
516 e32f879d blueswir1
    FORCE_RET();
517 e32f879d blueswir1
}
518 e32f879d blueswir1
519 e32f879d blueswir1
void OPPROTO op_tadd_T1_T0_ccTV(void)
520 e32f879d blueswir1
{
521 e32f879d blueswir1
    target_ulong src1;
522 e32f879d blueswir1
523 e32f879d blueswir1
    if ((T0 & 0x03) || (T1 & 0x03))
524 e32f879d blueswir1
        raise_exception(TT_TOVF);
525 e32f879d blueswir1
526 e32f879d blueswir1
    src1 = T0;
527 e32f879d blueswir1
    T0 += T1;
528 e32f879d blueswir1
529 e32f879d blueswir1
#ifdef TARGET_SPARC64
530 e32f879d blueswir1
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
531 e32f879d blueswir1
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
532 e32f879d blueswir1
        raise_exception(TT_TOVF);
533 e32f879d blueswir1
#else
534 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
535 e32f879d blueswir1
        raise_exception(TT_TOVF);
536 e32f879d blueswir1
#endif
537 e32f879d blueswir1
538 e32f879d blueswir1
    env->psr = 0;
539 e32f879d blueswir1
#ifdef TARGET_SPARC64
540 e32f879d blueswir1
    if (!(T0 & 0xffffffff))
541 e32f879d blueswir1
        env->psr |= PSR_ZERO;
542 e32f879d blueswir1
    if ((int32_t) T0 < 0)
543 e32f879d blueswir1
        env->psr |= PSR_NEG;
544 e32f879d blueswir1
    if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
545 e32f879d blueswir1
        env->psr |= PSR_CARRY;
546 e32f879d blueswir1
547 e32f879d blueswir1
    env->xcc = 0;
548 e32f879d blueswir1
    if (!T0)
549 e32f879d blueswir1
        env->xcc |= PSR_ZERO;
550 e32f879d blueswir1
    if ((int64_t) T0 < 0)
551 e32f879d blueswir1
        env->xcc |= PSR_NEG;
552 e32f879d blueswir1
    if (T0 < src1)
553 e32f879d blueswir1
        env->xcc |= PSR_CARRY;
554 e32f879d blueswir1
#else
555 e32f879d blueswir1
    if (!T0)
556 e32f879d blueswir1
        env->psr |= PSR_ZERO;
557 e32f879d blueswir1
    if ((int32_t) T0 < 0)
558 e32f879d blueswir1
        env->psr |= PSR_NEG;
559 e32f879d blueswir1
    if (T0 < src1)
560 e32f879d blueswir1
        env->psr |= PSR_CARRY;
561 e32f879d blueswir1
#endif
562 e32f879d blueswir1
    FORCE_RET();
563 e32f879d blueswir1
}
564 e32f879d blueswir1
565 cf495bcf bellard
void OPPROTO op_sub_T1_T0(void)
566 7a3f1944 bellard
{
567 cf495bcf bellard
    T0 -= T1;
568 7a3f1944 bellard
}
569 7a3f1944 bellard
570 cf495bcf bellard
void OPPROTO op_sub_T1_T0_cc(void)
571 7a3f1944 bellard
{
572 af7bf89b bellard
    target_ulong src1;
573 cf495bcf bellard
574 cf495bcf bellard
    src1 = T0;
575 cf495bcf bellard
    T0 -= T1;
576 cf495bcf bellard
    env->psr = 0;
577 3475187d bellard
#ifdef TARGET_SPARC64
578 3475187d bellard
    if (!(T0 & 0xffffffff))
579 3475187d bellard
        env->psr |= PSR_ZERO;
580 3475187d bellard
    if ((int32_t) T0 < 0)
581 3475187d bellard
        env->psr |= PSR_NEG;
582 83469015 bellard
    if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
583 3475187d bellard
        env->psr |= PSR_CARRY;
584 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
585 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
586 3475187d bellard
        env->psr |= PSR_OVF;
587 3475187d bellard
588 3475187d bellard
    env->xcc = 0;
589 3475187d bellard
    if (!T0)
590 3475187d bellard
        env->xcc |= PSR_ZERO;
591 3475187d bellard
    if ((int64_t) T0 < 0)
592 3475187d bellard
        env->xcc |= PSR_NEG;
593 bb3911a6 bellard
    if (src1 < T1)
594 3475187d bellard
        env->xcc |= PSR_CARRY;
595 3475187d bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
596 3475187d bellard
        env->xcc |= PSR_OVF;
597 3475187d bellard
#else
598 cf495bcf bellard
    if (!T0)
599 cf495bcf bellard
        env->psr |= PSR_ZERO;
600 af7bf89b bellard
    if ((int32_t) T0 < 0)
601 cf495bcf bellard
        env->psr |= PSR_NEG;
602 cf495bcf bellard
    if (src1 < T1)
603 cf495bcf bellard
        env->psr |= PSR_CARRY;
604 cf495bcf bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
605 cf495bcf bellard
        env->psr |= PSR_OVF;
606 3475187d bellard
#endif
607 af7bf89b bellard
    FORCE_RET();
608 af7bf89b bellard
}
609 af7bf89b bellard
610 af7bf89b bellard
void OPPROTO op_subx_T1_T0(void)
611 af7bf89b bellard
{
612 af7bf89b bellard
    T0 -= T1 + FLAG_SET(PSR_CARRY);
613 af7bf89b bellard
}
614 af7bf89b bellard
615 af7bf89b bellard
void OPPROTO op_subx_T1_T0_cc(void)
616 af7bf89b bellard
{
617 af7bf89b bellard
    target_ulong src1;
618 af7bf89b bellard
    src1 = T0;
619 b854608e bellard
    if (FLAG_SET(PSR_CARRY))
620 b854608e bellard
    {
621 b854608e bellard
      T0 -= T1 + 1;
622 b854608e bellard
      env->psr = 0;
623 b854608e bellard
#ifdef TARGET_SPARC64
624 b854608e bellard
      if ((src1 & 0xffffffff) <= (T1 & 0xffffffff))
625 b854608e bellard
        env->psr |= PSR_CARRY;
626 b854608e bellard
      env->xcc = 0;
627 b854608e bellard
      if (src1 <= T1)
628 b854608e bellard
        env->xcc |= PSR_CARRY;
629 b854608e bellard
#else
630 b854608e bellard
      if (src1 <= T1)
631 b854608e bellard
        env->psr |= PSR_CARRY;
632 b854608e bellard
#endif
633 b854608e bellard
    }
634 b854608e bellard
    else
635 b854608e bellard
    {
636 b854608e bellard
      T0 -= T1;
637 b854608e bellard
      env->psr = 0;
638 b854608e bellard
#ifdef TARGET_SPARC64
639 b854608e bellard
      if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
640 b854608e bellard
        env->psr |= PSR_CARRY;
641 b854608e bellard
      env->xcc = 0;
642 b854608e bellard
      if (src1 < T1)
643 b854608e bellard
        env->xcc |= PSR_CARRY;
644 b854608e bellard
#else
645 b854608e bellard
      if (src1 < T1)
646 b854608e bellard
        env->psr |= PSR_CARRY;
647 b854608e bellard
#endif
648 b854608e bellard
    }
649 3475187d bellard
#ifdef TARGET_SPARC64
650 3475187d bellard
    if (!(T0 & 0xffffffff))
651 3475187d bellard
        env->psr |= PSR_ZERO;
652 3475187d bellard
    if ((int32_t) T0 < 0)
653 3475187d bellard
        env->psr |= PSR_NEG;
654 3475187d bellard
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
655 3475187d bellard
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
656 3475187d bellard
        env->psr |= PSR_OVF;
657 3475187d bellard
658 3475187d bellard
    if (!T0)
659 3475187d bellard
        env->xcc |= PSR_ZERO;
660 3475187d bellard
    if ((int64_t) T0 < 0)
661 3475187d bellard
        env->xcc |= PSR_NEG;
662 3475187d bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
663 3475187d bellard
        env->xcc |= PSR_OVF;
664 3475187d bellard
#else
665 af7bf89b bellard
    if (!T0)
666 af7bf89b bellard
        env->psr |= PSR_ZERO;
667 af7bf89b bellard
    if ((int32_t) T0 < 0)
668 af7bf89b bellard
        env->psr |= PSR_NEG;
669 af7bf89b bellard
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
670 af7bf89b bellard
        env->psr |= PSR_OVF;
671 3475187d bellard
#endif
672 cf495bcf bellard
    FORCE_RET();
673 7a3f1944 bellard
}
674 7a3f1944 bellard
675 e32f879d blueswir1
void OPPROTO op_tsub_T1_T0_cc(void)
676 e32f879d blueswir1
{
677 e32f879d blueswir1
    target_ulong src1;
678 e32f879d blueswir1
679 e32f879d blueswir1
    src1 = T0;
680 e32f879d blueswir1
    T0 -= T1;
681 e32f879d blueswir1
    env->psr = 0;
682 e32f879d blueswir1
#ifdef TARGET_SPARC64
683 e32f879d blueswir1
    if (!(T0 & 0xffffffff))
684 e32f879d blueswir1
        env->psr |= PSR_ZERO;
685 e32f879d blueswir1
    if ((int32_t) T0 < 0)
686 e32f879d blueswir1
        env->psr |= PSR_NEG;
687 e32f879d blueswir1
    if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
688 e32f879d blueswir1
        env->psr |= PSR_CARRY;
689 e32f879d blueswir1
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
690 e32f879d blueswir1
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
691 e32f879d blueswir1
        env->psr |= PSR_OVF;
692 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
693 e32f879d blueswir1
        env->psr |= PSR_OVF;
694 e32f879d blueswir1
695 e32f879d blueswir1
    env->xcc = 0;
696 e32f879d blueswir1
    if (!T0)
697 e32f879d blueswir1
        env->xcc |= PSR_ZERO;
698 e32f879d blueswir1
    if ((int64_t) T0 < 0)
699 e32f879d blueswir1
        env->xcc |= PSR_NEG;
700 e32f879d blueswir1
    if (src1 < T1)
701 e32f879d blueswir1
        env->xcc |= PSR_CARRY;
702 e32f879d blueswir1
    if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
703 e32f879d blueswir1
        env->xcc |= PSR_OVF;
704 e32f879d blueswir1
#else
705 e32f879d blueswir1
    if (!T0)
706 e32f879d blueswir1
        env->psr |= PSR_ZERO;
707 e32f879d blueswir1
    if ((int32_t) T0 < 0)
708 e32f879d blueswir1
        env->psr |= PSR_NEG;
709 e32f879d blueswir1
    if (src1 < T1)
710 e32f879d blueswir1
        env->psr |= PSR_CARRY;
711 e32f879d blueswir1
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
712 e32f879d blueswir1
        env->psr |= PSR_OVF;
713 e32f879d blueswir1
    if ((src1 & 0x03) || (T1 & 0x03))
714 e32f879d blueswir1
        env->psr |= PSR_OVF;
715 e32f879d blueswir1
#endif
716 e32f879d blueswir1
    FORCE_RET();
717 e32f879d blueswir1
}
718 e32f879d blueswir1
719 e32f879d blueswir1
void OPPROTO op_tsub_T1_T0_ccTV(void)
720 e32f879d blueswir1
{
721 e32f879d blueswir1
    target_ulong src1;
722 e32f879d blueswir1
723 e32f879d blueswir1
    if ((T0 & 0x03) || (T1 & 0x03))
724 e32f879d blueswir1
        raise_exception(TT_TOVF);
725 e32f879d blueswir1
726 e32f879d blueswir1
    src1 = T0;
727 e32f879d blueswir1
    T0 -= T1;
728 e32f879d blueswir1
729 e32f879d blueswir1
#ifdef TARGET_SPARC64
730 e32f879d blueswir1
    if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
731 e32f879d blueswir1
         ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
732 e32f879d blueswir1
        raise_exception(TT_TOVF);
733 e32f879d blueswir1
#else
734 e32f879d blueswir1
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
735 e32f879d blueswir1
        raise_exception(TT_TOVF);
736 e32f879d blueswir1
#endif
737 e32f879d blueswir1
738 e32f879d blueswir1
    env->psr = 0;
739 e32f879d blueswir1
#ifdef TARGET_SPARC64
740 e32f879d blueswir1
    if (!(T0 & 0xffffffff))
741 e32f879d blueswir1
        env->psr |= PSR_ZERO;
742 e32f879d blueswir1
    if ((int32_t) T0 < 0)
743 e32f879d blueswir1
        env->psr |= PSR_NEG;
744 e32f879d blueswir1
    if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
745 e32f879d blueswir1
        env->psr |= PSR_CARRY;
746 e32f879d blueswir1
747 e32f879d blueswir1
    env->xcc = 0;
748 e32f879d blueswir1
    if (!T0)
749 e32f879d blueswir1
        env->xcc |= PSR_ZERO;
750 e32f879d blueswir1
    if ((int64_t) T0 < 0)
751 e32f879d blueswir1
        env->xcc |= PSR_NEG;
752 e32f879d blueswir1
    if (src1 < T1)
753 e32f879d blueswir1
        env->xcc |= PSR_CARRY;
754 e32f879d blueswir1
#else
755 e32f879d blueswir1
    if (!T0)
756 e32f879d blueswir1
        env->psr |= PSR_ZERO;
757 e32f879d blueswir1
    if ((int32_t) T0 < 0)
758 e32f879d blueswir1
        env->psr |= PSR_NEG;
759 e32f879d blueswir1
    if (src1 < T1)
760 e32f879d blueswir1
        env->psr |= PSR_CARRY;
761 e32f879d blueswir1
#endif
762 e32f879d blueswir1
    FORCE_RET();
763 e32f879d blueswir1
}
764 e32f879d blueswir1
765 cf495bcf bellard
void OPPROTO op_and_T1_T0(void)
766 7a3f1944 bellard
{
767 cf495bcf bellard
    T0 &= T1;
768 7a3f1944 bellard
}
769 7a3f1944 bellard
770 cf495bcf bellard
void OPPROTO op_or_T1_T0(void)
771 7a3f1944 bellard
{
772 cf495bcf bellard
    T0 |= T1;
773 7a3f1944 bellard
}
774 7a3f1944 bellard
775 cf495bcf bellard
void OPPROTO op_xor_T1_T0(void)
776 7a3f1944 bellard
{
777 cf495bcf bellard
    T0 ^= T1;
778 7a3f1944 bellard
}
779 7a3f1944 bellard
780 cf495bcf bellard
void OPPROTO op_andn_T1_T0(void)
781 7a3f1944 bellard
{
782 cf495bcf bellard
    T0 &= ~T1;
783 7a3f1944 bellard
}
784 7a3f1944 bellard
785 cf495bcf bellard
void OPPROTO op_orn_T1_T0(void)
786 7a3f1944 bellard
{
787 cf495bcf bellard
    T0 |= ~T1;
788 7a3f1944 bellard
}
789 7a3f1944 bellard
790 cf495bcf bellard
void OPPROTO op_xnor_T1_T0(void)
791 7a3f1944 bellard
{
792 cf495bcf bellard
    T0 ^= ~T1;
793 7a3f1944 bellard
}
794 7a3f1944 bellard
795 cf495bcf bellard
void OPPROTO op_umul_T1_T0(void)
796 7a3f1944 bellard
{
797 cf495bcf bellard
    uint64_t res;
798 af7bf89b bellard
    res = (uint64_t) T0 * (uint64_t) T1;
799 83469015 bellard
#ifdef TARGET_SPARC64
800 83469015 bellard
    T0 = res;
801 83469015 bellard
#else
802 cf495bcf bellard
    T0 = res & 0xffffffff;
803 83469015 bellard
#endif
804 cf495bcf bellard
    env->y = res >> 32;
805 7a3f1944 bellard
}
806 7a3f1944 bellard
807 cf495bcf bellard
void OPPROTO op_smul_T1_T0(void)
808 7a3f1944 bellard
{
809 cf495bcf bellard
    uint64_t res;
810 cf495bcf bellard
    res = (int64_t) ((int32_t) T0) * (int64_t) ((int32_t) T1);
811 83469015 bellard
#ifdef TARGET_SPARC64
812 83469015 bellard
    T0 = res;
813 83469015 bellard
#else
814 cf495bcf bellard
    T0 = res & 0xffffffff;
815 83469015 bellard
#endif
816 cf495bcf bellard
    env->y = res >> 32;
817 7a3f1944 bellard
}
818 7a3f1944 bellard
819 cf495bcf bellard
void OPPROTO op_mulscc_T1_T0(void)
820 7a3f1944 bellard
{
821 af7bf89b bellard
    unsigned int b1, N, V, b2;
822 af7bf89b bellard
    target_ulong src1;
823 af7bf89b bellard
824 4e8b5da2 bellard
    N = FLAG_SET(PSR_NEG);
825 cf495bcf bellard
    V = FLAG_SET(PSR_OVF);
826 4e8b5da2 bellard
    b1 = N ^ V;
827 cf495bcf bellard
    b2 = T0 & 1;
828 cf495bcf bellard
    T0 = (b1 << 31) | (T0 >> 1);
829 cf495bcf bellard
    if (!(env->y & 1))
830 cf495bcf bellard
        T1 = 0;
831 cf495bcf bellard
    /* do addition and update flags */
832 cf495bcf bellard
    src1 = T0;
833 cf495bcf bellard
    T0 += T1;
834 cf495bcf bellard
    env->psr = 0;
835 cf495bcf bellard
    if (!T0)
836 cf495bcf bellard
        env->psr |= PSR_ZERO;
837 af7bf89b bellard
    if ((int32_t) T0 < 0)
838 cf495bcf bellard
        env->psr |= PSR_NEG;
839 cf495bcf bellard
    if (T0 < src1)
840 cf495bcf bellard
        env->psr |= PSR_CARRY;
841 cf495bcf bellard
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
842 cf495bcf bellard
        env->psr |= PSR_OVF;
843 cf495bcf bellard
    env->y = (b2 << 31) | (env->y >> 1);
844 cf495bcf bellard
    FORCE_RET();
845 cf495bcf bellard
}
846 cf495bcf bellard
847 cf495bcf bellard
void OPPROTO op_udiv_T1_T0(void)
848 cf495bcf bellard
{
849 cf495bcf bellard
    uint64_t x0;
850 cf495bcf bellard
    uint32_t x1;
851 cf495bcf bellard
852 cf495bcf bellard
    x0 = T0 | ((uint64_t) (env->y) << 32);
853 cf495bcf bellard
    x1 = T1;
854 9bb234b3 ths
855 9bb234b3 ths
    if (x1 == 0) {
856 9bb234b3 ths
        raise_exception(TT_DIV_ZERO);
857 9bb234b3 ths
    }
858 9bb234b3 ths
859 cf495bcf bellard
    x0 = x0 / x1;
860 cf495bcf bellard
    if (x0 > 0xffffffff) {
861 cf495bcf bellard
        T0 = 0xffffffff;
862 cf495bcf bellard
        T1 = 1;
863 cf495bcf bellard
    } else {
864 cf495bcf bellard
        T0 = x0;
865 cf495bcf bellard
        T1 = 0;
866 cf495bcf bellard
    }
867 cf495bcf bellard
    FORCE_RET();
868 7a3f1944 bellard
}
869 7a3f1944 bellard
870 cf495bcf bellard
void OPPROTO op_sdiv_T1_T0(void)
871 7a3f1944 bellard
{
872 cf495bcf bellard
    int64_t x0;
873 cf495bcf bellard
    int32_t x1;
874 cf495bcf bellard
875 af7bf89b bellard
    x0 = T0 | ((int64_t) (env->y) << 32);
876 cf495bcf bellard
    x1 = T1;
877 9bb234b3 ths
878 9bb234b3 ths
    if (x1 == 0) {
879 9bb234b3 ths
        raise_exception(TT_DIV_ZERO);
880 9bb234b3 ths
    }
881 9bb234b3 ths
882 cf495bcf bellard
    x0 = x0 / x1;
883 cf495bcf bellard
    if ((int32_t) x0 != x0) {
884 af7bf89b bellard
        T0 = x0 < 0? 0x80000000: 0x7fffffff;
885 cf495bcf bellard
        T1 = 1;
886 cf495bcf bellard
    } else {
887 cf495bcf bellard
        T0 = x0;
888 cf495bcf bellard
        T1 = 0;
889 cf495bcf bellard
    }
890 cf495bcf bellard
    FORCE_RET();
891 7a3f1944 bellard
}
892 7a3f1944 bellard
893 cf495bcf bellard
void OPPROTO op_div_cc(void)
894 7a3f1944 bellard
{
895 cf495bcf bellard
    env->psr = 0;
896 3475187d bellard
#ifdef TARGET_SPARC64
897 3475187d bellard
    if (!T0)
898 3475187d bellard
        env->psr |= PSR_ZERO;
899 3475187d bellard
    if ((int32_t) T0 < 0)
900 3475187d bellard
        env->psr |= PSR_NEG;
901 3475187d bellard
    if (T1)
902 3475187d bellard
        env->psr |= PSR_OVF;
903 3475187d bellard
904 3475187d bellard
    env->xcc = 0;
905 3475187d bellard
    if (!T0)
906 3475187d bellard
        env->xcc |= PSR_ZERO;
907 3475187d bellard
    if ((int64_t) T0 < 0)
908 3475187d bellard
        env->xcc |= PSR_NEG;
909 3475187d bellard
#else
910 cf495bcf bellard
    if (!T0)
911 cf495bcf bellard
        env->psr |= PSR_ZERO;
912 af7bf89b bellard
    if ((int32_t) T0 < 0)
913 cf495bcf bellard
        env->psr |= PSR_NEG;
914 cf495bcf bellard
    if (T1)
915 cf495bcf bellard
        env->psr |= PSR_OVF;
916 3475187d bellard
#endif
917 cf495bcf bellard
    FORCE_RET();
918 7a3f1944 bellard
}
919 7a3f1944 bellard
920 3475187d bellard
#ifdef TARGET_SPARC64
921 3475187d bellard
void OPPROTO op_mulx_T1_T0(void)
922 3475187d bellard
{
923 3475187d bellard
    T0 *= T1;
924 3475187d bellard
    FORCE_RET();
925 3475187d bellard
}
926 3475187d bellard
927 3475187d bellard
void OPPROTO op_udivx_T1_T0(void)
928 3475187d bellard
{
929 14a1120e blueswir1
    if (T1 == 0) {
930 14a1120e blueswir1
        raise_exception(TT_DIV_ZERO);
931 14a1120e blueswir1
    }
932 3475187d bellard
    T0 /= T1;
933 3475187d bellard
    FORCE_RET();
934 3475187d bellard
}
935 3475187d bellard
936 3475187d bellard
void OPPROTO op_sdivx_T1_T0(void)
937 3475187d bellard
{
938 14a1120e blueswir1
    if (T1 == 0) {
939 14a1120e blueswir1
        raise_exception(TT_DIV_ZERO);
940 14a1120e blueswir1
    }
941 3475187d bellard
    if (T0 == INT64_MIN && T1 == -1)
942 3475187d bellard
        T0 = INT64_MIN;
943 3475187d bellard
    else
944 3475187d bellard
        T0 /= (target_long) T1;
945 3475187d bellard
    FORCE_RET();
946 3475187d bellard
}
947 3475187d bellard
#endif
948 3475187d bellard
949 cf495bcf bellard
void OPPROTO op_logic_T0_cc(void)
950 7a3f1944 bellard
{
951 cf495bcf bellard
    env->psr = 0;
952 3475187d bellard
#ifdef TARGET_SPARC64
953 3475187d bellard
    if (!(T0 & 0xffffffff))
954 3475187d bellard
        env->psr |= PSR_ZERO;
955 3475187d bellard
    if ((int32_t) T0 < 0)
956 3475187d bellard
        env->psr |= PSR_NEG;
957 3475187d bellard
958 3475187d bellard
    env->xcc = 0;
959 3475187d bellard
    if (!T0)
960 3475187d bellard
        env->xcc |= PSR_ZERO;
961 3475187d bellard
    if ((int64_t) T0 < 0)
962 3475187d bellard
        env->xcc |= PSR_NEG;
963 3475187d bellard
#else
964 cf495bcf bellard
    if (!T0)
965 cf495bcf bellard
        env->psr |= PSR_ZERO;
966 af7bf89b bellard
    if ((int32_t) T0 < 0)
967 cf495bcf bellard
        env->psr |= PSR_NEG;
968 3475187d bellard
#endif
969 cf495bcf bellard
    FORCE_RET();
970 7a3f1944 bellard
}
971 7a3f1944 bellard
972 cf495bcf bellard
void OPPROTO op_sll(void)
973 7a3f1944 bellard
{
974 8a08f9a8 blueswir1
    T0 <<= (T1 & 0x1f);
975 7a3f1944 bellard
}
976 7a3f1944 bellard
977 3475187d bellard
#ifdef TARGET_SPARC64
978 8a08f9a8 blueswir1
void OPPROTO op_sllx(void)
979 8a08f9a8 blueswir1
{
980 8a08f9a8 blueswir1
    T0 <<= (T1 & 0x3f);
981 8a08f9a8 blueswir1
}
982 8a08f9a8 blueswir1
983 3475187d bellard
void OPPROTO op_srl(void)
984 3475187d bellard
{
985 8a08f9a8 blueswir1
    T0 = (T0 & 0xffffffff) >> (T1 & 0x1f);
986 3475187d bellard
}
987 3475187d bellard
988 3475187d bellard
void OPPROTO op_srlx(void)
989 3475187d bellard
{
990 8a08f9a8 blueswir1
    T0 >>= (T1 & 0x3f);
991 3475187d bellard
}
992 3475187d bellard
993 3475187d bellard
void OPPROTO op_sra(void)
994 3475187d bellard
{
995 8a08f9a8 blueswir1
    T0 = ((int32_t) (T0 & 0xffffffff)) >> (T1 & 0x1f);
996 3475187d bellard
}
997 3475187d bellard
998 3475187d bellard
void OPPROTO op_srax(void)
999 3475187d bellard
{
1000 8a08f9a8 blueswir1
    T0 = ((int64_t) T0) >> (T1 & 0x3f);
1001 3475187d bellard
}
1002 3475187d bellard
#else
1003 cf495bcf bellard
void OPPROTO op_srl(void)
1004 7a3f1944 bellard
{
1005 8a08f9a8 blueswir1
    T0 >>= (T1 & 0x1f);
1006 7a3f1944 bellard
}
1007 7a3f1944 bellard
1008 cf495bcf bellard
void OPPROTO op_sra(void)
1009 7a3f1944 bellard
{
1010 8a08f9a8 blueswir1
    T0 = ((int32_t) T0) >> (T1 & 0x1f);
1011 7a3f1944 bellard
}
1012 3475187d bellard
#endif
1013 7a3f1944 bellard
1014 e8af50a3 bellard
/* Load and store */
1015 e8af50a3 bellard
#define MEMSUFFIX _raw
1016 e8af50a3 bellard
#include "op_mem.h"
1017 e8af50a3 bellard
#if !defined(CONFIG_USER_ONLY)
1018 e8af50a3 bellard
#define MEMSUFFIX _user
1019 e8af50a3 bellard
#include "op_mem.h"
1020 e8af50a3 bellard
1021 e8af50a3 bellard
#define MEMSUFFIX _kernel
1022 e8af50a3 bellard
#include "op_mem.h"
1023 e8af50a3 bellard
#endif
1024 e8af50a3 bellard
1025 e8af50a3 bellard
void OPPROTO op_ldfsr(void)
1026 e8af50a3 bellard
{
1027 3475187d bellard
    PUT_FSR32(env, *((uint32_t *) &FT0));
1028 8d5f07fa bellard
    helper_ldfsr();
1029 e8af50a3 bellard
}
1030 e8af50a3 bellard
1031 e8af50a3 bellard
void OPPROTO op_stfsr(void)
1032 e8af50a3 bellard
{
1033 3475187d bellard
    *((uint32_t *) &FT0) = GET_FSR32(env);
1034 e8af50a3 bellard
}
1035 e8af50a3 bellard
1036 3475187d bellard
#ifndef TARGET_SPARC64
1037 3475187d bellard
void OPPROTO op_rdpsr(void)
1038 7a3f1944 bellard
{
1039 3475187d bellard
    do_rdpsr();
1040 7a3f1944 bellard
}
1041 7a3f1944 bellard
1042 3475187d bellard
void OPPROTO op_wrpsr(void)
1043 7a3f1944 bellard
{
1044 3475187d bellard
    do_wrpsr();
1045 3475187d bellard
    FORCE_RET();
1046 7a3f1944 bellard
}
1047 7a3f1944 bellard
1048 c688a6eb bellard
void OPPROTO op_wrwim(void)
1049 c688a6eb bellard
{
1050 c688a6eb bellard
#if NWINDOWS == 32
1051 c688a6eb bellard
    env->wim = T0;
1052 c688a6eb bellard
#else
1053 c688a6eb bellard
    env->wim = T0 & ((1 << NWINDOWS) - 1);
1054 c688a6eb bellard
#endif
1055 c688a6eb bellard
}
1056 c688a6eb bellard
1057 3475187d bellard
void OPPROTO op_rett(void)
1058 cf495bcf bellard
{
1059 3475187d bellard
    helper_rett();
1060 3475187d bellard
    FORCE_RET();
1061 e8af50a3 bellard
}
1062 e8af50a3 bellard
1063 3475187d bellard
/* XXX: use another pointer for %iN registers to avoid slow wrapping
1064 3475187d bellard
   handling ? */
1065 3475187d bellard
void OPPROTO op_save(void)
1066 e8af50a3 bellard
{
1067 3475187d bellard
    uint32_t cwp;
1068 3475187d bellard
    cwp = (env->cwp - 1) & (NWINDOWS - 1); 
1069 3475187d bellard
    if (env->wim & (1 << cwp)) {
1070 3475187d bellard
        raise_exception(TT_WIN_OVF);
1071 3475187d bellard
    }
1072 3475187d bellard
    set_cwp(cwp);
1073 e8af50a3 bellard
    FORCE_RET();
1074 e8af50a3 bellard
}
1075 e8af50a3 bellard
1076 3475187d bellard
void OPPROTO op_restore(void)
1077 e8af50a3 bellard
{
1078 3475187d bellard
    uint32_t cwp;
1079 3475187d bellard
    cwp = (env->cwp + 1) & (NWINDOWS - 1); 
1080 3475187d bellard
    if (env->wim & (1 << cwp)) {
1081 3475187d bellard
        raise_exception(TT_WIN_UNF);
1082 3475187d bellard
    }
1083 3475187d bellard
    set_cwp(cwp);
1084 3475187d bellard
    FORCE_RET();
1085 3475187d bellard
}
1086 3475187d bellard
#else
1087 3475187d bellard
void OPPROTO op_rdccr(void)
1088 3475187d bellard
{
1089 3475187d bellard
    T0 = GET_CCR(env);
1090 e8af50a3 bellard
}
1091 e8af50a3 bellard
1092 3475187d bellard
void OPPROTO op_wrccr(void)
1093 e8af50a3 bellard
{
1094 3475187d bellard
    PUT_CCR(env, T0);
1095 e8af50a3 bellard
}
1096 e8af50a3 bellard
1097 3475187d bellard
void OPPROTO op_rdtick(void)
1098 e8af50a3 bellard
{
1099 3475187d bellard
    T0 = 0; // XXX read cycle counter and bit 31
1100 e8af50a3 bellard
}
1101 cf495bcf bellard
1102 3475187d bellard
void OPPROTO op_wrtick(void)
1103 7a3f1944 bellard
{
1104 e9ebed4d blueswir1
    T0 = 0; // XXX write cycle counter and bit 31
1105 7a3f1944 bellard
}
1106 7a3f1944 bellard
1107 3475187d bellard
void OPPROTO op_rdtpc(void)
1108 cf495bcf bellard
{
1109 3475187d bellard
    T0 = env->tpc[env->tl];
1110 3475187d bellard
}
1111 3475187d bellard
1112 3475187d bellard
void OPPROTO op_wrtpc(void)
1113 3475187d bellard
{
1114 3475187d bellard
    env->tpc[env->tl] = T0;
1115 3475187d bellard
}
1116 3475187d bellard
1117 3475187d bellard
void OPPROTO op_rdtnpc(void)
1118 3475187d bellard
{
1119 3475187d bellard
    T0 = env->tnpc[env->tl];
1120 3475187d bellard
}
1121 3475187d bellard
1122 3475187d bellard
void OPPROTO op_wrtnpc(void)
1123 3475187d bellard
{
1124 3475187d bellard
    env->tnpc[env->tl] = T0;
1125 3475187d bellard
}
1126 3475187d bellard
1127 3475187d bellard
void OPPROTO op_rdtstate(void)
1128 3475187d bellard
{
1129 3475187d bellard
    T0 = env->tstate[env->tl];
1130 3475187d bellard
}
1131 3475187d bellard
1132 3475187d bellard
void OPPROTO op_wrtstate(void)
1133 3475187d bellard
{
1134 3475187d bellard
    env->tstate[env->tl] = T0;
1135 3475187d bellard
}
1136 3475187d bellard
1137 3475187d bellard
void OPPROTO op_rdtt(void)
1138 3475187d bellard
{
1139 3475187d bellard
    T0 = env->tt[env->tl];
1140 3475187d bellard
}
1141 3475187d bellard
1142 3475187d bellard
void OPPROTO op_wrtt(void)
1143 3475187d bellard
{
1144 3475187d bellard
    env->tt[env->tl] = T0;
1145 3475187d bellard
}
1146 3475187d bellard
1147 3475187d bellard
void OPPROTO op_rdpstate(void)
1148 3475187d bellard
{
1149 3475187d bellard
    T0 = env->pstate;
1150 3475187d bellard
}
1151 3475187d bellard
1152 3475187d bellard
void OPPROTO op_wrpstate(void)
1153 3475187d bellard
{
1154 83469015 bellard
    do_wrpstate();
1155 3475187d bellard
}
1156 3475187d bellard
1157 3475187d bellard
// CWP handling is reversed in V9, but we still use the V8 register
1158 3475187d bellard
// order.
1159 3475187d bellard
void OPPROTO op_rdcwp(void)
1160 3475187d bellard
{
1161 3475187d bellard
    T0 = NWINDOWS - 1 - env->cwp;
1162 3475187d bellard
}
1163 3475187d bellard
1164 3475187d bellard
void OPPROTO op_wrcwp(void)
1165 3475187d bellard
{
1166 3475187d bellard
    env->cwp = NWINDOWS - 1 - T0;
1167 cf495bcf bellard
}
1168 7a3f1944 bellard
1169 cf495bcf bellard
/* XXX: use another pointer for %iN registers to avoid slow wrapping
1170 cf495bcf bellard
   handling ? */
1171 cf495bcf bellard
void OPPROTO op_save(void)
1172 7a3f1944 bellard
{
1173 af7bf89b bellard
    uint32_t cwp;
1174 cf495bcf bellard
    cwp = (env->cwp - 1) & (NWINDOWS - 1); 
1175 3475187d bellard
    if (env->cansave == 0) {
1176 3475187d bellard
        raise_exception(TT_SPILL | (env->otherwin != 0 ? 
1177 3475187d bellard
                                    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1178 3475187d bellard
                                    ((env->wstate & 0x7) << 2)));
1179 3475187d bellard
    } else {
1180 3475187d bellard
        if (env->cleanwin - env->canrestore == 0) {
1181 3475187d bellard
            // XXX Clean windows without trap
1182 3475187d bellard
            raise_exception(TT_CLRWIN);
1183 3475187d bellard
        } else {
1184 3475187d bellard
            env->cansave--;
1185 3475187d bellard
            env->canrestore++;
1186 3475187d bellard
            set_cwp(cwp);
1187 3475187d bellard
        }
1188 cf495bcf bellard
    }
1189 cf495bcf bellard
    FORCE_RET();
1190 7a3f1944 bellard
}
1191 7a3f1944 bellard
1192 cf495bcf bellard
void OPPROTO op_restore(void)
1193 7a3f1944 bellard
{
1194 af7bf89b bellard
    uint32_t cwp;
1195 cf495bcf bellard
    cwp = (env->cwp + 1) & (NWINDOWS - 1); 
1196 3475187d bellard
    if (env->canrestore == 0) {
1197 3475187d bellard
        raise_exception(TT_FILL | (env->otherwin != 0 ? 
1198 3475187d bellard
                                   (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1199 3475187d bellard
                                   ((env->wstate & 0x7) << 2)));
1200 3475187d bellard
    } else {
1201 3475187d bellard
        env->cansave++;
1202 3475187d bellard
        env->canrestore--;
1203 3475187d bellard
        set_cwp(cwp);
1204 cf495bcf bellard
    }
1205 cf495bcf bellard
    FORCE_RET();
1206 7a3f1944 bellard
}
1207 3475187d bellard
#endif
1208 7a3f1944 bellard
1209 cf495bcf bellard
void OPPROTO op_exception(void)
1210 7a3f1944 bellard
{
1211 cf495bcf bellard
    env->exception_index = PARAM1;
1212 cf495bcf bellard
    cpu_loop_exit();
1213 7a3f1944 bellard
}
1214 7a3f1944 bellard
1215 cf495bcf bellard
void OPPROTO op_trap_T0(void)
1216 7a3f1944 bellard
{
1217 cf495bcf bellard
    env->exception_index = TT_TRAP + (T0 & 0x7f);
1218 cf495bcf bellard
    cpu_loop_exit();
1219 7a3f1944 bellard
}
1220 7a3f1944 bellard
1221 cf495bcf bellard
void OPPROTO op_trapcc_T0(void)
1222 7a3f1944 bellard
{
1223 cf495bcf bellard
    if (T2) {
1224 cf495bcf bellard
        env->exception_index = TT_TRAP + (T0 & 0x7f);
1225 cf495bcf bellard
        cpu_loop_exit();
1226 cf495bcf bellard
    }
1227 cf495bcf bellard
    FORCE_RET();
1228 7a3f1944 bellard
}
1229 7a3f1944 bellard
1230 e80cfcfc bellard
void OPPROTO op_fpexception_im(void)
1231 e8af50a3 bellard
{
1232 e80cfcfc bellard
    env->exception_index = TT_FP_EXCP;
1233 e80cfcfc bellard
    env->fsr &= ~FSR_FTT_MASK;
1234 e80cfcfc bellard
    env->fsr |= PARAM1;
1235 e8af50a3 bellard
    cpu_loop_exit();
1236 e80cfcfc bellard
    FORCE_RET();
1237 e80cfcfc bellard
}
1238 e80cfcfc bellard
1239 e80cfcfc bellard
void OPPROTO op_debug(void)
1240 e80cfcfc bellard
{
1241 e80cfcfc bellard
    helper_debug();
1242 e8af50a3 bellard
}
1243 e8af50a3 bellard
1244 cf495bcf bellard
void OPPROTO op_exit_tb(void)
1245 7a3f1944 bellard
{
1246 cf495bcf bellard
    EXIT_TB();
1247 7a3f1944 bellard
}
1248 7a3f1944 bellard
1249 3475187d bellard
void OPPROTO op_eval_ba(void)
1250 3475187d bellard
{
1251 3475187d bellard
    T2 = 1;
1252 3475187d bellard
}
1253 3475187d bellard
1254 cf495bcf bellard
void OPPROTO op_eval_be(void)
1255 7a3f1944 bellard
{
1256 af7bf89b bellard
    T2 = FLAG_SET(PSR_ZERO);
1257 7a3f1944 bellard
}
1258 7a3f1944 bellard
1259 cf495bcf bellard
void OPPROTO op_eval_ble(void)
1260 7a3f1944 bellard
{
1261 af7bf89b bellard
    target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
1262 612b477d bellard
    
1263 cf495bcf bellard
    T2 = Z | (N ^ V);
1264 7a3f1944 bellard
}
1265 7a3f1944 bellard
1266 cf495bcf bellard
void OPPROTO op_eval_bl(void)
1267 7a3f1944 bellard
{
1268 af7bf89b bellard
    target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
1269 612b477d bellard
1270 cf495bcf bellard
    T2 = N ^ V;
1271 7a3f1944 bellard
}
1272 7a3f1944 bellard
1273 cf495bcf bellard
void OPPROTO op_eval_bleu(void)
1274 7a3f1944 bellard
{
1275 af7bf89b bellard
    target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
1276 612b477d bellard
1277 cf495bcf bellard
    T2 = C | Z;
1278 7a3f1944 bellard
}
1279 7a3f1944 bellard
1280 cf495bcf bellard
void OPPROTO op_eval_bcs(void)
1281 7a3f1944 bellard
{
1282 af7bf89b bellard
    T2 = FLAG_SET(PSR_CARRY);
1283 7a3f1944 bellard
}
1284 7a3f1944 bellard
1285 cf495bcf bellard
void OPPROTO op_eval_bvs(void)
1286 7a3f1944 bellard
{
1287 af7bf89b bellard
    T2 = FLAG_SET(PSR_OVF);
1288 7a3f1944 bellard
}
1289 7a3f1944 bellard
1290 3475187d bellard
void OPPROTO op_eval_bn(void)
1291 3475187d bellard
{
1292 3475187d bellard
    T2 = 0;
1293 3475187d bellard
}
1294 3475187d bellard
1295 cf495bcf bellard
void OPPROTO op_eval_bneg(void)
1296 7a3f1944 bellard
{
1297 af7bf89b bellard
    T2 = FLAG_SET(PSR_NEG);
1298 7a3f1944 bellard
}
1299 7a3f1944 bellard
1300 cf495bcf bellard
void OPPROTO op_eval_bne(void)
1301 7a3f1944 bellard
{
1302 af7bf89b bellard
    T2 = !FLAG_SET(PSR_ZERO);
1303 7a3f1944 bellard
}
1304 7a3f1944 bellard
1305 cf495bcf bellard
void OPPROTO op_eval_bg(void)
1306 7a3f1944 bellard
{
1307 af7bf89b bellard
    target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
1308 612b477d bellard
1309 cf495bcf bellard
    T2 = !(Z | (N ^ V));
1310 7a3f1944 bellard
}
1311 7a3f1944 bellard
1312 cf495bcf bellard
void OPPROTO op_eval_bge(void)
1313 7a3f1944 bellard
{
1314 af7bf89b bellard
    target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
1315 612b477d bellard
1316 cf495bcf bellard
    T2 = !(N ^ V);
1317 7a3f1944 bellard
}
1318 7a3f1944 bellard
1319 cf495bcf bellard
void OPPROTO op_eval_bgu(void)
1320 7a3f1944 bellard
{
1321 af7bf89b bellard
    target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
1322 612b477d bellard
1323 cf495bcf bellard
    T2 = !(C | Z);
1324 7a3f1944 bellard
}
1325 7a3f1944 bellard
1326 cf495bcf bellard
void OPPROTO op_eval_bcc(void)
1327 7a3f1944 bellard
{
1328 af7bf89b bellard
    T2 = !FLAG_SET(PSR_CARRY);
1329 7a3f1944 bellard
}
1330 7a3f1944 bellard
1331 cf495bcf bellard
void OPPROTO op_eval_bpos(void)
1332 cf495bcf bellard
{
1333 af7bf89b bellard
    T2 = !FLAG_SET(PSR_NEG);
1334 cf495bcf bellard
}
1335 cf495bcf bellard
1336 cf495bcf bellard
void OPPROTO op_eval_bvc(void)
1337 cf495bcf bellard
{
1338 af7bf89b bellard
    T2 = !FLAG_SET(PSR_OVF);
1339 cf495bcf bellard
}
1340 cf495bcf bellard
1341 3475187d bellard
#ifdef TARGET_SPARC64
1342 3475187d bellard
void OPPROTO op_eval_xbe(void)
1343 3475187d bellard
{
1344 3475187d bellard
    T2 = XFLAG_SET(PSR_ZERO);
1345 3475187d bellard
}
1346 e8af50a3 bellard
1347 3475187d bellard
void OPPROTO op_eval_xble(void)
1348 e8af50a3 bellard
{
1349 3475187d bellard
    target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1350 3475187d bellard
    
1351 3475187d bellard
    T2 = Z | (N ^ V);
1352 e8af50a3 bellard
}
1353 e8af50a3 bellard
1354 3475187d bellard
void OPPROTO op_eval_xbl(void)
1355 e8af50a3 bellard
{
1356 3475187d bellard
    target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1357 3475187d bellard
1358 3475187d bellard
    T2 = N ^ V;
1359 e8af50a3 bellard
}
1360 e8af50a3 bellard
1361 3475187d bellard
void OPPROTO op_eval_xbleu(void)
1362 e8af50a3 bellard
{
1363 3475187d bellard
    target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
1364 3475187d bellard
1365 3475187d bellard
    T2 = C | Z;
1366 e8af50a3 bellard
}
1367 e8af50a3 bellard
1368 3475187d bellard
void OPPROTO op_eval_xbcs(void)
1369 e8af50a3 bellard
{
1370 3475187d bellard
    T2 = XFLAG_SET(PSR_CARRY);
1371 e8af50a3 bellard
}
1372 e8af50a3 bellard
1373 3475187d bellard
void OPPROTO op_eval_xbvs(void)
1374 e8af50a3 bellard
{
1375 3475187d bellard
    T2 = XFLAG_SET(PSR_OVF);
1376 e8af50a3 bellard
}
1377 e8af50a3 bellard
1378 3475187d bellard
void OPPROTO op_eval_xbneg(void)
1379 e8af50a3 bellard
{
1380 3475187d bellard
    T2 = XFLAG_SET(PSR_NEG);
1381 e8af50a3 bellard
}
1382 e8af50a3 bellard
1383 3475187d bellard
void OPPROTO op_eval_xbne(void)
1384 e8af50a3 bellard
{
1385 3475187d bellard
    T2 = !XFLAG_SET(PSR_ZERO);
1386 e8af50a3 bellard
}
1387 e8af50a3 bellard
1388 3475187d bellard
void OPPROTO op_eval_xbg(void)
1389 e8af50a3 bellard
{
1390 3475187d bellard
    target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1391 3475187d bellard
1392 3475187d bellard
    T2 = !(Z | (N ^ V));
1393 e8af50a3 bellard
}
1394 e8af50a3 bellard
1395 3475187d bellard
void OPPROTO op_eval_xbge(void)
1396 e8af50a3 bellard
{
1397 3475187d bellard
    target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
1398 3475187d bellard
1399 3475187d bellard
    T2 = !(N ^ V);
1400 3475187d bellard
}
1401 3475187d bellard
1402 3475187d bellard
void OPPROTO op_eval_xbgu(void)
1403 3475187d bellard
{
1404 3475187d bellard
    target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
1405 3475187d bellard
1406 3475187d bellard
    T2 = !(C | Z);
1407 3475187d bellard
}
1408 3475187d bellard
1409 3475187d bellard
void OPPROTO op_eval_xbcc(void)
1410 3475187d bellard
{
1411 3475187d bellard
    T2 = !XFLAG_SET(PSR_CARRY);
1412 3475187d bellard
}
1413 3475187d bellard
1414 3475187d bellard
void OPPROTO op_eval_xbpos(void)
1415 3475187d bellard
{
1416 3475187d bellard
    T2 = !XFLAG_SET(PSR_NEG);
1417 3475187d bellard
}
1418 3475187d bellard
1419 3475187d bellard
void OPPROTO op_eval_xbvc(void)
1420 3475187d bellard
{
1421 3475187d bellard
    T2 = !XFLAG_SET(PSR_OVF);
1422 3475187d bellard
}
1423 3475187d bellard
#endif
1424 3475187d bellard
1425 3475187d bellard
#define FCC
1426 3475187d bellard
#define FFLAG_SET(x) (env->fsr & x? 1: 0)
1427 3475187d bellard
#include "fbranch_template.h"
1428 3475187d bellard
1429 3475187d bellard
#ifdef TARGET_SPARC64
1430 3475187d bellard
#define FCC _fcc1
1431 3475187d bellard
#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 32))? 1: 0)
1432 3475187d bellard
#include "fbranch_template.h"
1433 3475187d bellard
#define FCC _fcc2
1434 3475187d bellard
#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 34))? 1: 0)
1435 3475187d bellard
#include "fbranch_template.h"
1436 3475187d bellard
#define FCC _fcc3
1437 3475187d bellard
#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 36))? 1: 0)
1438 3475187d bellard
#include "fbranch_template.h"
1439 3475187d bellard
#endif
1440 3475187d bellard
1441 3475187d bellard
#ifdef TARGET_SPARC64
1442 3475187d bellard
void OPPROTO op_eval_brz(void)
1443 3475187d bellard
{
1444 83469015 bellard
    T2 = (T0 == 0);
1445 e8af50a3 bellard
}
1446 e8af50a3 bellard
1447 3475187d bellard
void OPPROTO op_eval_brnz(void)
1448 e8af50a3 bellard
{
1449 83469015 bellard
    T2 = (T0 != 0);
1450 e8af50a3 bellard
}
1451 e8af50a3 bellard
1452 3475187d bellard
void OPPROTO op_eval_brlz(void)
1453 e8af50a3 bellard
{
1454 3475187d bellard
    T2 = ((int64_t)T0 < 0);
1455 e8af50a3 bellard
}
1456 e8af50a3 bellard
1457 3475187d bellard
void OPPROTO op_eval_brlez(void)
1458 e8af50a3 bellard
{
1459 3475187d bellard
    T2 = ((int64_t)T0 <= 0);
1460 e8af50a3 bellard
}
1461 e8af50a3 bellard
1462 3475187d bellard
void OPPROTO op_eval_brgz(void)
1463 e8af50a3 bellard
{
1464 3475187d bellard
    T2 = ((int64_t)T0 > 0);
1465 e8af50a3 bellard
}
1466 e8af50a3 bellard
1467 3475187d bellard
void OPPROTO op_eval_brgez(void)
1468 e8af50a3 bellard
{
1469 3475187d bellard
    T2 = ((int64_t)T0 >= 0);
1470 e8af50a3 bellard
}
1471 e8af50a3 bellard
1472 3475187d bellard
void OPPROTO op_jmp_im64(void)
1473 3475187d bellard
{
1474 3475187d bellard
    env->pc = PARAMQ1;
1475 3475187d bellard
}
1476 3475187d bellard
1477 3475187d bellard
void OPPROTO op_movq_npc_im64(void)
1478 3475187d bellard
{
1479 3475187d bellard
    env->npc = PARAMQ1;
1480 3475187d bellard
}
1481 3475187d bellard
#endif
1482 3475187d bellard
1483 cf495bcf bellard
void OPPROTO op_jmp_im(void)
1484 cf495bcf bellard
{
1485 3475187d bellard
    env->pc = (uint32_t)PARAM1;
1486 cf495bcf bellard
}
1487 cf495bcf bellard
1488 cf495bcf bellard
void OPPROTO op_movl_npc_im(void)
1489 cf495bcf bellard
{
1490 3475187d bellard
    env->npc = (uint32_t)PARAM1;
1491 cf495bcf bellard
}
1492 7a3f1944 bellard
1493 cf495bcf bellard
void OPPROTO op_movl_npc_T0(void)
1494 7a3f1944 bellard
{
1495 d2889a3e blueswir1
    if (T0 & 0x3)
1496 d2889a3e blueswir1
        raise_exception(TT_UNALIGNED);
1497 d2889a3e blueswir1
    else
1498 d2889a3e blueswir1
        env->npc = T0;
1499 7a3f1944 bellard
}
1500 7a3f1944 bellard
1501 0bee699e bellard
void OPPROTO op_mov_pc_npc(void)
1502 0bee699e bellard
{
1503 0bee699e bellard
    env->pc = env->npc;
1504 0bee699e bellard
}
1505 0bee699e bellard
1506 cf495bcf bellard
void OPPROTO op_next_insn(void)
1507 7a3f1944 bellard
{
1508 cf495bcf bellard
    env->pc = env->npc;
1509 cf495bcf bellard
    env->npc = env->npc + 4;
1510 7a3f1944 bellard
}
1511 7a3f1944 bellard
1512 83469015 bellard
void OPPROTO op_goto_tb0(void)
1513 72cbca10 bellard
{
1514 83469015 bellard
    GOTO_TB(op_goto_tb0, PARAM1, 0);
1515 72cbca10 bellard
}
1516 72cbca10 bellard
1517 83469015 bellard
void OPPROTO op_goto_tb1(void)
1518 7a3f1944 bellard
{
1519 83469015 bellard
    GOTO_TB(op_goto_tb1, PARAM1, 1);
1520 72cbca10 bellard
}
1521 72cbca10 bellard
1522 83469015 bellard
void OPPROTO op_jmp_label(void)
1523 72cbca10 bellard
{
1524 83469015 bellard
    GOTO_LABEL_PARAM(1);
1525 83469015 bellard
}
1526 83469015 bellard
1527 83469015 bellard
void OPPROTO op_jnz_T2_label(void)
1528 83469015 bellard
{
1529 83469015 bellard
    if (T2)
1530 83469015 bellard
        GOTO_LABEL_PARAM(1);
1531 cf495bcf bellard
    FORCE_RET();
1532 7a3f1944 bellard
}
1533 7a3f1944 bellard
1534 83469015 bellard
void OPPROTO op_jz_T2_label(void)
1535 7a3f1944 bellard
{
1536 83469015 bellard
    if (!T2)
1537 83469015 bellard
        GOTO_LABEL_PARAM(1);
1538 cf495bcf bellard
    FORCE_RET();
1539 7a3f1944 bellard
}
1540 72cbca10 bellard
1541 658138bc bellard
void OPPROTO op_flush_T0(void)
1542 658138bc bellard
{
1543 658138bc bellard
    helper_flush(T0);
1544 658138bc bellard
}
1545 e8af50a3 bellard
1546 417454b0 blueswir1
void OPPROTO op_clear_ieee_excp_and_FTT(void)
1547 417454b0 blueswir1
{
1548 417454b0 blueswir1
    env->fsr &= ~(FSR_FTT_MASK | FSR_CEXC_MASK);;
1549 417454b0 blueswir1
}
1550 417454b0 blueswir1
1551 65ce8c2f bellard
#define F_OP(name, p) void OPPROTO op_f##name##p(void)
1552 65ce8c2f bellard
1553 65ce8c2f bellard
#define F_BINOP(name)                                           \
1554 65ce8c2f bellard
    F_OP(name, s)                                               \
1555 65ce8c2f bellard
    {                                                           \
1556 417454b0 blueswir1
        set_float_exception_flags(0, &env->fp_status);                \
1557 65ce8c2f bellard
        FT0 = float32_ ## name (FT0, FT1, &env->fp_status);     \
1558 417454b0 blueswir1
        check_ieee_exceptions();                                \
1559 65ce8c2f bellard
    }                                                           \
1560 65ce8c2f bellard
    F_OP(name, d)                                               \
1561 65ce8c2f bellard
    {                                                           \
1562 417454b0 blueswir1
        set_float_exception_flags(0, &env->fp_status);                \
1563 65ce8c2f bellard
        DT0 = float64_ ## name (DT0, DT1, &env->fp_status);     \
1564 417454b0 blueswir1
        check_ieee_exceptions();                                \
1565 65ce8c2f bellard
    }
1566 e8af50a3 bellard
1567 65ce8c2f bellard
F_BINOP(add);
1568 65ce8c2f bellard
F_BINOP(sub);
1569 65ce8c2f bellard
F_BINOP(mul);
1570 65ce8c2f bellard
F_BINOP(div);
1571 65ce8c2f bellard
#undef F_BINOP
1572 e8af50a3 bellard
1573 e8af50a3 bellard
void OPPROTO op_fsmuld(void)
1574 e8af50a3 bellard
{
1575 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1576 65ce8c2f bellard
    DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
1577 65ce8c2f bellard
                      float32_to_float64(FT1, &env->fp_status),
1578 65ce8c2f bellard
                      &env->fp_status);
1579 417454b0 blueswir1
    check_ieee_exceptions();
1580 e8af50a3 bellard
}
1581 e8af50a3 bellard
1582 65ce8c2f bellard
#define F_HELPER(name)    \
1583 65ce8c2f bellard
    F_OP(name, s)         \
1584 65ce8c2f bellard
    {                     \
1585 65ce8c2f bellard
        do_f##name##s();  \
1586 65ce8c2f bellard
    }                     \
1587 65ce8c2f bellard
    F_OP(name, d)         \
1588 65ce8c2f bellard
    {                     \
1589 65ce8c2f bellard
        do_f##name##d();  \
1590 65ce8c2f bellard
    }
1591 e8af50a3 bellard
1592 65ce8c2f bellard
F_HELPER(sqrt);
1593 e8af50a3 bellard
1594 65ce8c2f bellard
F_OP(neg, s)
1595 e8af50a3 bellard
{
1596 65ce8c2f bellard
    FT0 = float32_chs(FT1);
1597 e8af50a3 bellard
}
1598 e8af50a3 bellard
1599 65ce8c2f bellard
F_OP(abs, s)
1600 e8af50a3 bellard
{
1601 65ce8c2f bellard
    do_fabss();
1602 e8af50a3 bellard
}
1603 e8af50a3 bellard
1604 65ce8c2f bellard
F_HELPER(cmp);
1605 417454b0 blueswir1
F_HELPER(cmpe);
1606 e8af50a3 bellard
1607 65ce8c2f bellard
#ifdef TARGET_SPARC64
1608 65ce8c2f bellard
F_OP(neg, d)
1609 e8af50a3 bellard
{
1610 65ce8c2f bellard
    DT0 = float64_chs(DT1);
1611 e8af50a3 bellard
}
1612 e8af50a3 bellard
1613 65ce8c2f bellard
F_OP(abs, d)
1614 e8af50a3 bellard
{
1615 65ce8c2f bellard
    do_fabsd();
1616 e8af50a3 bellard
}
1617 e8af50a3 bellard
1618 3475187d bellard
void OPPROTO op_fcmps_fcc1(void)
1619 3475187d bellard
{
1620 3475187d bellard
    do_fcmps_fcc1();
1621 3475187d bellard
}
1622 3475187d bellard
1623 3475187d bellard
void OPPROTO op_fcmpd_fcc1(void)
1624 3475187d bellard
{
1625 3475187d bellard
    do_fcmpd_fcc1();
1626 3475187d bellard
}
1627 3475187d bellard
1628 3475187d bellard
void OPPROTO op_fcmps_fcc2(void)
1629 3475187d bellard
{
1630 3475187d bellard
    do_fcmps_fcc2();
1631 3475187d bellard
}
1632 3475187d bellard
1633 3475187d bellard
void OPPROTO op_fcmpd_fcc2(void)
1634 3475187d bellard
{
1635 3475187d bellard
    do_fcmpd_fcc2();
1636 3475187d bellard
}
1637 3475187d bellard
1638 3475187d bellard
void OPPROTO op_fcmps_fcc3(void)
1639 3475187d bellard
{
1640 3475187d bellard
    do_fcmps_fcc3();
1641 3475187d bellard
}
1642 3475187d bellard
1643 3475187d bellard
void OPPROTO op_fcmpd_fcc3(void)
1644 3475187d bellard
{
1645 3475187d bellard
    do_fcmpd_fcc3();
1646 3475187d bellard
}
1647 417454b0 blueswir1
1648 417454b0 blueswir1
void OPPROTO op_fcmpes_fcc1(void)
1649 417454b0 blueswir1
{
1650 417454b0 blueswir1
    do_fcmpes_fcc1();
1651 417454b0 blueswir1
}
1652 417454b0 blueswir1
1653 417454b0 blueswir1
void OPPROTO op_fcmped_fcc1(void)
1654 417454b0 blueswir1
{
1655 417454b0 blueswir1
    do_fcmped_fcc1();
1656 417454b0 blueswir1
}
1657 417454b0 blueswir1
1658 417454b0 blueswir1
void OPPROTO op_fcmpes_fcc2(void)
1659 417454b0 blueswir1
{
1660 417454b0 blueswir1
    do_fcmpes_fcc2();
1661 417454b0 blueswir1
}
1662 417454b0 blueswir1
1663 417454b0 blueswir1
void OPPROTO op_fcmped_fcc2(void)
1664 417454b0 blueswir1
{
1665 417454b0 blueswir1
    do_fcmped_fcc2();
1666 417454b0 blueswir1
}
1667 417454b0 blueswir1
1668 417454b0 blueswir1
void OPPROTO op_fcmpes_fcc3(void)
1669 417454b0 blueswir1
{
1670 417454b0 blueswir1
    do_fcmpes_fcc3();
1671 417454b0 blueswir1
}
1672 417454b0 blueswir1
1673 417454b0 blueswir1
void OPPROTO op_fcmped_fcc3(void)
1674 417454b0 blueswir1
{
1675 417454b0 blueswir1
    do_fcmped_fcc3();
1676 417454b0 blueswir1
}
1677 417454b0 blueswir1
1678 3475187d bellard
#endif
1679 3475187d bellard
1680 65ce8c2f bellard
/* Integer to float conversion.  */
1681 a0c4cb4a bellard
#ifdef USE_INT_TO_FLOAT_HELPERS
1682 65ce8c2f bellard
F_HELPER(ito);
1683 a0c4cb4a bellard
#else
1684 65ce8c2f bellard
F_OP(ito, s)
1685 a0c4cb4a bellard
{
1686 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1687 65ce8c2f bellard
    FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
1688 417454b0 blueswir1
    check_ieee_exceptions();
1689 e8af50a3 bellard
}
1690 e8af50a3 bellard
1691 65ce8c2f bellard
F_OP(ito, d)
1692 e8af50a3 bellard
{
1693 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1694 65ce8c2f bellard
    DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
1695 417454b0 blueswir1
    check_ieee_exceptions();
1696 e8af50a3 bellard
}
1697 3475187d bellard
1698 3475187d bellard
#ifdef TARGET_SPARC64
1699 65ce8c2f bellard
F_OP(xto, s)
1700 3475187d bellard
{
1701 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1702 65ce8c2f bellard
    FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
1703 417454b0 blueswir1
    check_ieee_exceptions();
1704 3475187d bellard
}
1705 3475187d bellard
1706 65ce8c2f bellard
F_OP(xto, d)
1707 3475187d bellard
{
1708 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1709 65ce8c2f bellard
    DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
1710 417454b0 blueswir1
    check_ieee_exceptions();
1711 3475187d bellard
}
1712 3475187d bellard
#endif
1713 a0c4cb4a bellard
#endif
1714 65ce8c2f bellard
#undef F_HELPER
1715 a0c4cb4a bellard
1716 65ce8c2f bellard
/* floating point conversion */
1717 a0c4cb4a bellard
void OPPROTO op_fdtos(void)
1718 a0c4cb4a bellard
{
1719 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1720 65ce8c2f bellard
    FT0 = float64_to_float32(DT1, &env->fp_status);
1721 417454b0 blueswir1
    check_ieee_exceptions();
1722 a0c4cb4a bellard
}
1723 e8af50a3 bellard
1724 e8af50a3 bellard
void OPPROTO op_fstod(void)
1725 e8af50a3 bellard
{
1726 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1727 65ce8c2f bellard
    DT0 = float32_to_float64(FT1, &env->fp_status);
1728 417454b0 blueswir1
    check_ieee_exceptions();
1729 e8af50a3 bellard
}
1730 e8af50a3 bellard
1731 65ce8c2f bellard
/* Float to integer conversion.  */
1732 e8af50a3 bellard
void OPPROTO op_fstoi(void)
1733 e8af50a3 bellard
{
1734 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1735 bd59780c ths
    *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
1736 417454b0 blueswir1
    check_ieee_exceptions();
1737 e8af50a3 bellard
}
1738 e8af50a3 bellard
1739 e8af50a3 bellard
void OPPROTO op_fdtoi(void)
1740 e8af50a3 bellard
{
1741 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1742 bd59780c ths
    *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
1743 417454b0 blueswir1
    check_ieee_exceptions();
1744 e8af50a3 bellard
}
1745 e8af50a3 bellard
1746 3475187d bellard
#ifdef TARGET_SPARC64
1747 3475187d bellard
void OPPROTO op_fstox(void)
1748 3475187d bellard
{
1749 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1750 bd59780c ths
    *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
1751 417454b0 blueswir1
    check_ieee_exceptions();
1752 3475187d bellard
}
1753 3475187d bellard
1754 3475187d bellard
void OPPROTO op_fdtox(void)
1755 3475187d bellard
{
1756 417454b0 blueswir1
    set_float_exception_flags(0, &env->fp_status);
1757 bd59780c ths
    *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
1758 417454b0 blueswir1
    check_ieee_exceptions();
1759 3475187d bellard
}
1760 3475187d bellard
1761 3475187d bellard
void OPPROTO op_fmovs_cc(void)
1762 3475187d bellard
{
1763 3475187d bellard
    if (T2)
1764 3475187d bellard
        FT0 = FT1;
1765 3475187d bellard
}
1766 3475187d bellard
1767 3475187d bellard
void OPPROTO op_fmovd_cc(void)
1768 3475187d bellard
{
1769 3475187d bellard
    if (T2)
1770 3475187d bellard
        DT0 = DT1;
1771 3475187d bellard
}
1772 3475187d bellard
1773 3475187d bellard
void OPPROTO op_mov_cc(void)
1774 3475187d bellard
{
1775 3475187d bellard
    if (T2)
1776 3475187d bellard
        T0 = T1;
1777 3475187d bellard
}
1778 3475187d bellard
1779 3475187d bellard
void OPPROTO op_flushw(void)
1780 3475187d bellard
{
1781 3475187d bellard
    if (env->cansave != NWINDOWS - 2) {
1782 3475187d bellard
        raise_exception(TT_SPILL | (env->otherwin != 0 ? 
1783 3475187d bellard
                                    (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
1784 3475187d bellard
                                    ((env->wstate & 0x7) << 2)));
1785 3475187d bellard
    }
1786 3475187d bellard
}
1787 3475187d bellard
1788 3475187d bellard
void OPPROTO op_saved(void)
1789 3475187d bellard
{
1790 3475187d bellard
    env->cansave++;
1791 3475187d bellard
    if (env->otherwin == 0)
1792 3475187d bellard
        env->canrestore--;
1793 725cb90b bellard
    else
1794 725cb90b bellard
        env->otherwin--;
1795 725cb90b bellard
    FORCE_RET();
1796 3475187d bellard
}
1797 3475187d bellard
1798 3475187d bellard
void OPPROTO op_restored(void)
1799 3475187d bellard
{
1800 3475187d bellard
    env->canrestore++;
1801 3475187d bellard
    if (env->cleanwin < NWINDOWS - 1)
1802 3475187d bellard
        env->cleanwin++;
1803 3475187d bellard
    if (env->otherwin == 0)
1804 3475187d bellard
        env->cansave--;
1805 3475187d bellard
    else
1806 3475187d bellard
        env->otherwin--;
1807 725cb90b bellard
    FORCE_RET();
1808 3475187d bellard
}
1809 3475187d bellard
1810 3475187d bellard
void OPPROTO op_popc(void)
1811 3475187d bellard
{
1812 3475187d bellard
    do_popc();
1813 3475187d bellard
}
1814 3475187d bellard
1815 3475187d bellard
void OPPROTO op_done(void)
1816 3475187d bellard
{
1817 83469015 bellard
    do_done();
1818 3475187d bellard
}
1819 3475187d bellard
1820 3475187d bellard
void OPPROTO op_retry(void)
1821 3475187d bellard
{
1822 83469015 bellard
    do_retry();
1823 3475187d bellard
}
1824 3475187d bellard
1825 3475187d bellard
void OPPROTO op_sir(void)
1826 3475187d bellard
{
1827 e9ebed4d blueswir1
    T0 = 0;  // XXX
1828 3475187d bellard
}
1829 3475187d bellard
1830 3475187d bellard
void OPPROTO op_ld_asi_reg()
1831 3475187d bellard
{
1832 3475187d bellard
    T0 += PARAM1;
1833 3475187d bellard
    helper_ld_asi(env->asi, PARAM2, PARAM3);
1834 3475187d bellard
}
1835 3475187d bellard
1836 3475187d bellard
void OPPROTO op_st_asi_reg()
1837 3475187d bellard
{
1838 3475187d bellard
    T0 += PARAM1;
1839 3475187d bellard
    helper_st_asi(env->asi, PARAM2, PARAM3);
1840 3475187d bellard
}
1841 3475187d bellard
#endif
1842 3475187d bellard
1843 e8af50a3 bellard
void OPPROTO op_ld_asi()
1844 e8af50a3 bellard
{
1845 e8af50a3 bellard
    helper_ld_asi(PARAM1, PARAM2, PARAM3);
1846 e8af50a3 bellard
}
1847 e8af50a3 bellard
1848 e8af50a3 bellard
void OPPROTO op_st_asi()
1849 e8af50a3 bellard
{
1850 e8af50a3 bellard
    helper_st_asi(PARAM1, PARAM2, PARAM3);
1851 e8af50a3 bellard
}
1852 e8af50a3 bellard
1853 725cb90b bellard
#ifdef TARGET_SPARC64
1854 e9ebed4d blueswir1
// This function uses non-native bit order
1855 e9ebed4d blueswir1
#define GET_FIELD(X, FROM, TO)                                  \
1856 e9ebed4d blueswir1
    ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
1857 e9ebed4d blueswir1
1858 e9ebed4d blueswir1
// This function uses the order in the manuals, i.e. bit 0 is 2^0
1859 e9ebed4d blueswir1
#define GET_FIELD_SP(X, FROM, TO)               \
1860 e9ebed4d blueswir1
    GET_FIELD(X, 63 - (TO), 63 - (FROM))
1861 e9ebed4d blueswir1
1862 e9ebed4d blueswir1
void OPPROTO op_array8()
1863 e9ebed4d blueswir1
{
1864 e9ebed4d blueswir1
    T0 = (GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
1865 e9ebed4d blueswir1
        (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
1866 e9ebed4d blueswir1
        (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
1867 e9ebed4d blueswir1
        (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
1868 e9ebed4d blueswir1
        (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
1869 e9ebed4d blueswir1
        (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12);
1870 e9ebed4d blueswir1
}
1871 e9ebed4d blueswir1
1872 e9ebed4d blueswir1
void OPPROTO op_array16()
1873 e9ebed4d blueswir1
{
1874 e9ebed4d blueswir1
    T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
1875 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
1876 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
1877 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
1878 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
1879 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 1;
1880 e9ebed4d blueswir1
}
1881 e9ebed4d blueswir1
1882 e9ebed4d blueswir1
void OPPROTO op_array32()
1883 e9ebed4d blueswir1
{
1884 e9ebed4d blueswir1
    T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
1885 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
1886 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
1887 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
1888 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
1889 e9ebed4d blueswir1
          (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 2;
1890 e9ebed4d blueswir1
}
1891 e9ebed4d blueswir1
1892 725cb90b bellard
void OPPROTO op_alignaddr()
1893 725cb90b bellard
{
1894 725cb90b bellard
    uint64_t tmp;
1895 725cb90b bellard
1896 725cb90b bellard
    tmp = T0 + T1;
1897 725cb90b bellard
    env->gsr &= ~7ULL;
1898 725cb90b bellard
    env->gsr |= tmp & 7ULL;
1899 725cb90b bellard
    T0 = tmp & ~7ULL;
1900 725cb90b bellard
}
1901 725cb90b bellard
1902 725cb90b bellard
void OPPROTO op_faligndata()
1903 725cb90b bellard
{
1904 725cb90b bellard
    uint64_t tmp;
1905 725cb90b bellard
1906 725cb90b bellard
    tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
1907 725cb90b bellard
    tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
1908 e9ebed4d blueswir1
    *((uint64_t *)&DT0) = tmp;
1909 725cb90b bellard
}
1910 3299908c blueswir1
1911 3299908c blueswir1
void OPPROTO op_movl_FT0_0(void)
1912 3299908c blueswir1
{
1913 e9ebed4d blueswir1
    *((uint32_t *)&FT0) = 0;
1914 3299908c blueswir1
}
1915 3299908c blueswir1
1916 3299908c blueswir1
void OPPROTO op_movl_DT0_0(void)
1917 3299908c blueswir1
{
1918 e9ebed4d blueswir1
    *((uint64_t *)&DT0) = 0;
1919 3299908c blueswir1
}
1920 3299908c blueswir1
1921 3299908c blueswir1
void OPPROTO op_movl_FT0_1(void)
1922 3299908c blueswir1
{
1923 e9ebed4d blueswir1
    *((uint32_t *)&FT0) = 0xffffffff;
1924 3299908c blueswir1
}
1925 3299908c blueswir1
1926 3299908c blueswir1
void OPPROTO op_movl_DT0_1(void)
1927 3299908c blueswir1
{
1928 e9ebed4d blueswir1
    *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
1929 e9ebed4d blueswir1
}
1930 e9ebed4d blueswir1
1931 e9ebed4d blueswir1
void OPPROTO op_fnot(void)
1932 e9ebed4d blueswir1
{
1933 e9ebed4d blueswir1
    *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
1934 e9ebed4d blueswir1
}
1935 e9ebed4d blueswir1
1936 e9ebed4d blueswir1
void OPPROTO op_fnots(void)
1937 e9ebed4d blueswir1
{
1938 e9ebed4d blueswir1
    *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
1939 e9ebed4d blueswir1
}
1940 e9ebed4d blueswir1
1941 e9ebed4d blueswir1
void OPPROTO op_fnor(void)
1942 e9ebed4d blueswir1
{
1943 e9ebed4d blueswir1
    *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
1944 e9ebed4d blueswir1
}
1945 e9ebed4d blueswir1
1946 e9ebed4d blueswir1
void OPPROTO op_fnors(void)
1947 e9ebed4d blueswir1
{
1948 e9ebed4d blueswir1
    *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
1949 e9ebed4d blueswir1
}
1950 e9ebed4d blueswir1
1951 e9ebed4d blueswir1
void OPPROTO op_for(void)
1952 e9ebed4d blueswir1
{
1953 e9ebed4d blueswir1
    *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
1954 e9ebed4d blueswir1
}
1955 e9ebed4d blueswir1
1956 e9ebed4d blueswir1
void OPPROTO op_fors(void)
1957 e9ebed4d blueswir1
{
1958 e9ebed4d blueswir1
    *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
1959 e9ebed4d blueswir1
}
1960 e9ebed4d blueswir1
1961 e9ebed4d blueswir1
void OPPROTO op_fxor(void)
1962 e9ebed4d blueswir1
{
1963 e9ebed4d blueswir1
    *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
1964 e9ebed4d blueswir1
}
1965 e9ebed4d blueswir1
1966 e9ebed4d blueswir1
void OPPROTO op_fxors(void)
1967 e9ebed4d blueswir1
{
1968 e9ebed4d blueswir1
    *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
1969 e9ebed4d blueswir1
}
1970 e9ebed4d blueswir1
1971 e9ebed4d blueswir1
void OPPROTO op_fand(void)
1972 e9ebed4d blueswir1
{
1973 e9ebed4d blueswir1
    *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
1974 e9ebed4d blueswir1
}
1975 e9ebed4d blueswir1
1976 e9ebed4d blueswir1
void OPPROTO op_fands(void)
1977 e9ebed4d blueswir1
{
1978 e9ebed4d blueswir1
    *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
1979 e9ebed4d blueswir1
}
1980 e9ebed4d blueswir1
1981 e9ebed4d blueswir1
void OPPROTO op_fornot(void)
1982 e9ebed4d blueswir1
{
1983 e9ebed4d blueswir1
    *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
1984 e9ebed4d blueswir1
}
1985 e9ebed4d blueswir1
1986 e9ebed4d blueswir1
void OPPROTO op_fornots(void)
1987 e9ebed4d blueswir1
{
1988 e9ebed4d blueswir1
    *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
1989 e9ebed4d blueswir1
}
1990 e9ebed4d blueswir1
1991 e9ebed4d blueswir1
void OPPROTO op_fandnot(void)
1992 e9ebed4d blueswir1
{
1993 e9ebed4d blueswir1
    *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
1994 e9ebed4d blueswir1
}
1995 e9ebed4d blueswir1
1996 e9ebed4d blueswir1
void OPPROTO op_fandnots(void)
1997 e9ebed4d blueswir1
{
1998 e9ebed4d blueswir1
    *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
1999 e9ebed4d blueswir1
}
2000 e9ebed4d blueswir1
2001 e9ebed4d blueswir1
void OPPROTO op_fnand(void)
2002 e9ebed4d blueswir1
{
2003 e9ebed4d blueswir1
    *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
2004 e9ebed4d blueswir1
}
2005 e9ebed4d blueswir1
2006 e9ebed4d blueswir1
void OPPROTO op_fnands(void)
2007 e9ebed4d blueswir1
{
2008 e9ebed4d blueswir1
    *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
2009 e9ebed4d blueswir1
}
2010 e9ebed4d blueswir1
2011 e9ebed4d blueswir1
void OPPROTO op_fxnor(void)
2012 e9ebed4d blueswir1
{
2013 e9ebed4d blueswir1
    *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
2014 e9ebed4d blueswir1
}
2015 e9ebed4d blueswir1
2016 e9ebed4d blueswir1
void OPPROTO op_fxnors(void)
2017 e9ebed4d blueswir1
{
2018 e9ebed4d blueswir1
    *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
2019 e9ebed4d blueswir1
}
2020 e9ebed4d blueswir1
2021 e9ebed4d blueswir1
#ifdef WORDS_BIGENDIAN
2022 e9ebed4d blueswir1
#define VIS_B64(n) b[7 - (n)]
2023 e9ebed4d blueswir1
#define VIS_W64(n) w[3 - (n)]
2024 e9ebed4d blueswir1
#define VIS_SW64(n) sw[3 - (n)]
2025 e9ebed4d blueswir1
#define VIS_L64(n) l[1 - (n)]
2026 e9ebed4d blueswir1
#define VIS_B32(n) b[3 - (n)]
2027 e9ebed4d blueswir1
#define VIS_W32(n) w[1 - (n)]
2028 e9ebed4d blueswir1
#else
2029 e9ebed4d blueswir1
#define VIS_B64(n) b[n]
2030 e9ebed4d blueswir1
#define VIS_W64(n) w[n]
2031 e9ebed4d blueswir1
#define VIS_SW64(n) sw[n]
2032 e9ebed4d blueswir1
#define VIS_L64(n) l[n]
2033 e9ebed4d blueswir1
#define VIS_B32(n) b[n]
2034 e9ebed4d blueswir1
#define VIS_W32(n) w[n]
2035 e9ebed4d blueswir1
#endif
2036 e9ebed4d blueswir1
2037 e9ebed4d blueswir1
typedef union {
2038 e9ebed4d blueswir1
    uint8_t b[8];
2039 e9ebed4d blueswir1
    uint16_t w[4];
2040 e9ebed4d blueswir1
    int16_t sw[4];
2041 e9ebed4d blueswir1
    uint32_t l[2];
2042 e9ebed4d blueswir1
    float64 d;
2043 e9ebed4d blueswir1
} vis64;
2044 e9ebed4d blueswir1
2045 e9ebed4d blueswir1
typedef union {
2046 e9ebed4d blueswir1
    uint8_t b[4];
2047 e9ebed4d blueswir1
    uint16_t w[2];
2048 e9ebed4d blueswir1
    uint32_t l;
2049 e9ebed4d blueswir1
    float32 f;
2050 e9ebed4d blueswir1
} vis32;
2051 e9ebed4d blueswir1
2052 e9ebed4d blueswir1
void OPPROTO op_fpmerge(void)
2053 e9ebed4d blueswir1
{
2054 e9ebed4d blueswir1
    vis64 s, d;
2055 e9ebed4d blueswir1
2056 e9ebed4d blueswir1
    s.d = DT0;
2057 e9ebed4d blueswir1
    d.d = DT1;
2058 e9ebed4d blueswir1
2059 e9ebed4d blueswir1
    // Reverse calculation order to handle overlap
2060 e9ebed4d blueswir1
    d.VIS_B64(7) = s.VIS_B64(3);
2061 e9ebed4d blueswir1
    d.VIS_B64(6) = d.VIS_B64(3);
2062 e9ebed4d blueswir1
    d.VIS_B64(5) = s.VIS_B64(2);
2063 e9ebed4d blueswir1
    d.VIS_B64(4) = d.VIS_B64(2);
2064 e9ebed4d blueswir1
    d.VIS_B64(3) = s.VIS_B64(1);
2065 e9ebed4d blueswir1
    d.VIS_B64(2) = d.VIS_B64(1);
2066 e9ebed4d blueswir1
    d.VIS_B64(1) = s.VIS_B64(0);
2067 e9ebed4d blueswir1
    //d.VIS_B64(0) = d.VIS_B64(0);
2068 e9ebed4d blueswir1
2069 e9ebed4d blueswir1
    DT0 = d.d;
2070 e9ebed4d blueswir1
}
2071 e9ebed4d blueswir1
2072 e9ebed4d blueswir1
void OPPROTO op_fmul8x16(void)
2073 e9ebed4d blueswir1
{
2074 e9ebed4d blueswir1
    vis64 s, d;
2075 e9ebed4d blueswir1
    uint32_t tmp;
2076 e9ebed4d blueswir1
2077 e9ebed4d blueswir1
    s.d = DT0;
2078 e9ebed4d blueswir1
    d.d = DT1;
2079 e9ebed4d blueswir1
2080 e9ebed4d blueswir1
#define PMUL(r)                                                 \
2081 e9ebed4d blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r);       \
2082 e9ebed4d blueswir1
    if ((tmp & 0xff) > 0x7f)                                    \
2083 e9ebed4d blueswir1
        tmp += 0x100;                                           \
2084 e9ebed4d blueswir1
    d.VIS_W64(r) = tmp >> 8;
2085 e9ebed4d blueswir1
2086 e9ebed4d blueswir1
    PMUL(0);
2087 e9ebed4d blueswir1
    PMUL(1);
2088 e9ebed4d blueswir1
    PMUL(2);
2089 e9ebed4d blueswir1
    PMUL(3);
2090 e9ebed4d blueswir1
#undef PMUL
2091 e9ebed4d blueswir1
2092 e9ebed4d blueswir1
    DT0 = d.d;
2093 e9ebed4d blueswir1
}
2094 e9ebed4d blueswir1
2095 e9ebed4d blueswir1
void OPPROTO op_fmul8x16al(void)
2096 e9ebed4d blueswir1
{
2097 e9ebed4d blueswir1
    vis64 s, d;
2098 e9ebed4d blueswir1
    uint32_t tmp;
2099 e9ebed4d blueswir1
2100 e9ebed4d blueswir1
    s.d = DT0;
2101 e9ebed4d blueswir1
    d.d = DT1;
2102 e9ebed4d blueswir1
2103 e9ebed4d blueswir1
#define PMUL(r)                                                 \
2104 e9ebed4d blueswir1
    tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r);       \
2105 e9ebed4d blueswir1
    if ((tmp & 0xff) > 0x7f)                                    \
2106 e9ebed4d blueswir1
        tmp += 0x100;                                           \
2107 e9ebed4d blueswir1
    d.VIS_W64(r) = tmp >> 8;
2108 e9ebed4d blueswir1
2109 e9ebed4d blueswir1
    PMUL(0);
2110 e9ebed4d blueswir1
    PMUL(1);
2111 e9ebed4d blueswir1
    PMUL(2);
2112 e9ebed4d blueswir1
    PMUL(3);
2113 e9ebed4d blueswir1
#undef PMUL
2114 e9ebed4d blueswir1
2115 e9ebed4d blueswir1
    DT0 = d.d;
2116 3299908c blueswir1
}
2117 e9ebed4d blueswir1
2118 e9ebed4d blueswir1
void OPPROTO op_fmul8x16au(void)
2119 e9ebed4d blueswir1
{
2120 e9ebed4d blueswir1
    vis64 s, d;
2121 e9ebed4d blueswir1
    uint32_t tmp;
2122 e9ebed4d blueswir1
2123 e9ebed4d blueswir1
    s.d = DT0;
2124 e9ebed4d blueswir1
    d.d = DT1;
2125 e9ebed4d blueswir1
2126 e9ebed4d blueswir1
#define PMUL(r)                                                 \
2127 e9ebed4d blueswir1
    tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r);       \
2128 e9ebed4d blueswir1
    if ((tmp & 0xff) > 0x7f)                                    \
2129 e9ebed4d blueswir1
        tmp += 0x100;                                           \
2130 e9ebed4d blueswir1
    d.VIS_W64(r) = tmp >> 8;
2131 e9ebed4d blueswir1
2132 e9ebed4d blueswir1
    PMUL(0);
2133 e9ebed4d blueswir1
    PMUL(1);
2134 e9ebed4d blueswir1
    PMUL(2);
2135 e9ebed4d blueswir1
    PMUL(3);
2136 e9ebed4d blueswir1
#undef PMUL
2137 e9ebed4d blueswir1
2138 e9ebed4d blueswir1
    DT0 = d.d;
2139 e9ebed4d blueswir1
}
2140 e9ebed4d blueswir1
2141 e9ebed4d blueswir1
void OPPROTO op_fmul8sux16(void)
2142 e9ebed4d blueswir1
{
2143 e9ebed4d blueswir1
    vis64 s, d;
2144 e9ebed4d blueswir1
    uint32_t tmp;
2145 e9ebed4d blueswir1
2146 e9ebed4d blueswir1
    s.d = DT0;
2147 e9ebed4d blueswir1
    d.d = DT1;
2148 e9ebed4d blueswir1
2149 e9ebed4d blueswir1
#define PMUL(r)                                                         \
2150 e9ebed4d blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8);       \
2151 e9ebed4d blueswir1
    if ((tmp & 0xff) > 0x7f)                                            \
2152 e9ebed4d blueswir1
        tmp += 0x100;                                                   \
2153 e9ebed4d blueswir1
    d.VIS_W64(r) = tmp >> 8;
2154 e9ebed4d blueswir1
2155 e9ebed4d blueswir1
    PMUL(0);
2156 e9ebed4d blueswir1
    PMUL(1);
2157 e9ebed4d blueswir1
    PMUL(2);
2158 e9ebed4d blueswir1
    PMUL(3);
2159 e9ebed4d blueswir1
#undef PMUL
2160 e9ebed4d blueswir1
2161 e9ebed4d blueswir1
    DT0 = d.d;
2162 e9ebed4d blueswir1
}
2163 e9ebed4d blueswir1
2164 e9ebed4d blueswir1
void OPPROTO op_fmul8ulx16(void)
2165 e9ebed4d blueswir1
{
2166 e9ebed4d blueswir1
    vis64 s, d;
2167 e9ebed4d blueswir1
    uint32_t tmp;
2168 e9ebed4d blueswir1
2169 e9ebed4d blueswir1
    s.d = DT0;
2170 e9ebed4d blueswir1
    d.d = DT1;
2171 e9ebed4d blueswir1
2172 e9ebed4d blueswir1
#define PMUL(r)                                                         \
2173 e9ebed4d blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2));        \
2174 e9ebed4d blueswir1
    if ((tmp & 0xff) > 0x7f)                                            \
2175 e9ebed4d blueswir1
        tmp += 0x100;                                                   \
2176 e9ebed4d blueswir1
    d.VIS_W64(r) = tmp >> 8;
2177 e9ebed4d blueswir1
2178 e9ebed4d blueswir1
    PMUL(0);
2179 e9ebed4d blueswir1
    PMUL(1);
2180 e9ebed4d blueswir1
    PMUL(2);
2181 e9ebed4d blueswir1
    PMUL(3);
2182 e9ebed4d blueswir1
#undef PMUL
2183 e9ebed4d blueswir1
2184 e9ebed4d blueswir1
    DT0 = d.d;
2185 e9ebed4d blueswir1
}
2186 e9ebed4d blueswir1
2187 e9ebed4d blueswir1
void OPPROTO op_fmuld8sux16(void)
2188 e9ebed4d blueswir1
{
2189 e9ebed4d blueswir1
    vis64 s, d;
2190 e9ebed4d blueswir1
    uint32_t tmp;
2191 e9ebed4d blueswir1
2192 e9ebed4d blueswir1
    s.d = DT0;
2193 e9ebed4d blueswir1
    d.d = DT1;
2194 e9ebed4d blueswir1
2195 e9ebed4d blueswir1
#define PMUL(r)                                                         \
2196 e9ebed4d blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8);       \
2197 e9ebed4d blueswir1
    if ((tmp & 0xff) > 0x7f)                                            \
2198 e9ebed4d blueswir1
        tmp += 0x100;                                                   \
2199 e9ebed4d blueswir1
    d.VIS_L64(r) = tmp;
2200 e9ebed4d blueswir1
2201 e9ebed4d blueswir1
    // Reverse calculation order to handle overlap
2202 e9ebed4d blueswir1
    PMUL(1);
2203 e9ebed4d blueswir1
    PMUL(0);
2204 e9ebed4d blueswir1
#undef PMUL
2205 e9ebed4d blueswir1
2206 e9ebed4d blueswir1
    DT0 = d.d;
2207 e9ebed4d blueswir1
}
2208 e9ebed4d blueswir1
2209 e9ebed4d blueswir1
void OPPROTO op_fmuld8ulx16(void)
2210 e9ebed4d blueswir1
{
2211 e9ebed4d blueswir1
    vis64 s, d;
2212 e9ebed4d blueswir1
    uint32_t tmp;
2213 e9ebed4d blueswir1
2214 e9ebed4d blueswir1
    s.d = DT0;
2215 e9ebed4d blueswir1
    d.d = DT1;
2216 e9ebed4d blueswir1
2217 e9ebed4d blueswir1
#define PMUL(r)                                                         \
2218 e9ebed4d blueswir1
    tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2));        \
2219 e9ebed4d blueswir1
    if ((tmp & 0xff) > 0x7f)                                            \
2220 e9ebed4d blueswir1
        tmp += 0x100;                                                   \
2221 e9ebed4d blueswir1
    d.VIS_L64(r) = tmp;
2222 e9ebed4d blueswir1
2223 e9ebed4d blueswir1
    // Reverse calculation order to handle overlap
2224 e9ebed4d blueswir1
    PMUL(1);
2225 e9ebed4d blueswir1
    PMUL(0);
2226 e9ebed4d blueswir1
#undef PMUL
2227 e9ebed4d blueswir1
2228 e9ebed4d blueswir1
    DT0 = d.d;
2229 e9ebed4d blueswir1
}
2230 e9ebed4d blueswir1
2231 e9ebed4d blueswir1
void OPPROTO op_fexpand(void)
2232 e9ebed4d blueswir1
{
2233 e9ebed4d blueswir1
    vis32 s;
2234 e9ebed4d blueswir1
    vis64 d;
2235 e9ebed4d blueswir1
2236 e9ebed4d blueswir1
    s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
2237 e9ebed4d blueswir1
    d.d = DT1;
2238 e9ebed4d blueswir1
    d.VIS_L64(0) = s.VIS_W32(0) << 4;
2239 e9ebed4d blueswir1
    d.VIS_L64(1) = s.VIS_W32(1) << 4;
2240 e9ebed4d blueswir1
    d.VIS_L64(2) = s.VIS_W32(2) << 4;
2241 e9ebed4d blueswir1
    d.VIS_L64(3) = s.VIS_W32(3) << 4;
2242 e9ebed4d blueswir1
2243 e9ebed4d blueswir1
    DT0 = d.d;
2244 e9ebed4d blueswir1
}
2245 e9ebed4d blueswir1
2246 e9ebed4d blueswir1
#define VIS_OP(name, F)                                 \
2247 e9ebed4d blueswir1
    void OPPROTO name##16(void)                         \
2248 e9ebed4d blueswir1
    {                                                   \
2249 e9ebed4d blueswir1
        vis64 s, d;                                     \
2250 e9ebed4d blueswir1
                                                        \
2251 e9ebed4d blueswir1
        s.d = DT0;                                      \
2252 e9ebed4d blueswir1
        d.d = DT1;                                      \
2253 e9ebed4d blueswir1
                                                        \
2254 e9ebed4d blueswir1
        d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0));   \
2255 e9ebed4d blueswir1
        d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1));   \
2256 e9ebed4d blueswir1
        d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2));   \
2257 e9ebed4d blueswir1
        d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3));   \
2258 e9ebed4d blueswir1
                                                        \
2259 e9ebed4d blueswir1
        DT0 = d.d;                                      \
2260 e9ebed4d blueswir1
    }                                                   \
2261 e9ebed4d blueswir1
                                                        \
2262 e9ebed4d blueswir1
    void OPPROTO name##16s(void)                        \
2263 e9ebed4d blueswir1
    {                                                   \
2264 e9ebed4d blueswir1
        vis32 s, d;                                     \
2265 e9ebed4d blueswir1
                                                        \
2266 e9ebed4d blueswir1
        s.f = FT0;                                      \
2267 e9ebed4d blueswir1
        d.f = FT1;                                      \
2268 e9ebed4d blueswir1
                                                        \
2269 e9ebed4d blueswir1
        d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0));   \
2270 e9ebed4d blueswir1
        d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1));   \
2271 e9ebed4d blueswir1
                                                        \
2272 e9ebed4d blueswir1
        FT0 = d.f;                                      \
2273 e9ebed4d blueswir1
    }                                                   \
2274 e9ebed4d blueswir1
                                                        \
2275 e9ebed4d blueswir1
    void OPPROTO name##32(void)                         \
2276 e9ebed4d blueswir1
    {                                                   \
2277 e9ebed4d blueswir1
        vis64 s, d;                                     \
2278 e9ebed4d blueswir1
                                                        \
2279 e9ebed4d blueswir1
        s.d = DT0;                                      \
2280 e9ebed4d blueswir1
        d.d = DT1;                                      \
2281 e9ebed4d blueswir1
                                                        \
2282 e9ebed4d blueswir1
        d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0));   \
2283 e9ebed4d blueswir1
        d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1));   \
2284 e9ebed4d blueswir1
                                                        \
2285 e9ebed4d blueswir1
        DT0 = d.d;                                      \
2286 e9ebed4d blueswir1
    }                                                   \
2287 e9ebed4d blueswir1
                                                        \
2288 e9ebed4d blueswir1
    void OPPROTO name##32s(void)                        \
2289 e9ebed4d blueswir1
    {                                                   \
2290 e9ebed4d blueswir1
        vis32 s, d;                                     \
2291 e9ebed4d blueswir1
                                                        \
2292 e9ebed4d blueswir1
        s.f = FT0;                                      \
2293 e9ebed4d blueswir1
        d.f = FT1;                                      \
2294 e9ebed4d blueswir1
                                                        \
2295 e9ebed4d blueswir1
        d.l = F(d.l, s.l);                              \
2296 e9ebed4d blueswir1
                                                        \
2297 e9ebed4d blueswir1
        FT0 = d.f;                                      \
2298 e9ebed4d blueswir1
    }
2299 e9ebed4d blueswir1
2300 e9ebed4d blueswir1
#define FADD(a, b) ((a) + (b))
2301 e9ebed4d blueswir1
#define FSUB(a, b) ((a) - (b))
2302 e9ebed4d blueswir1
VIS_OP(op_fpadd, FADD)
2303 e9ebed4d blueswir1
VIS_OP(op_fpsub, FSUB)
2304 e9ebed4d blueswir1
2305 e9ebed4d blueswir1
#define VIS_CMPOP(name, F)                                        \
2306 e9ebed4d blueswir1
    void OPPROTO name##16(void)                                   \
2307 e9ebed4d blueswir1
    {                                                             \
2308 e9ebed4d blueswir1
        vis64 s, d;                                               \
2309 e9ebed4d blueswir1
                                                                  \
2310 e9ebed4d blueswir1
        s.d = DT0;                                                \
2311 e9ebed4d blueswir1
        d.d = DT1;                                                \
2312 e9ebed4d blueswir1
                                                                  \
2313 e9ebed4d blueswir1
        d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0;       \
2314 e9ebed4d blueswir1
        d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0;      \
2315 e9ebed4d blueswir1
        d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0;      \
2316 e9ebed4d blueswir1
        d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0;      \
2317 e9ebed4d blueswir1
                                                                  \
2318 e9ebed4d blueswir1
        DT0 = d.d;                                                \
2319 e9ebed4d blueswir1
    }                                                             \
2320 e9ebed4d blueswir1
                                                                  \
2321 e9ebed4d blueswir1
    void OPPROTO name##32(void)                                   \
2322 e9ebed4d blueswir1
    {                                                             \
2323 e9ebed4d blueswir1
        vis64 s, d;                                               \
2324 e9ebed4d blueswir1
                                                                  \
2325 e9ebed4d blueswir1
        s.d = DT0;                                                \
2326 e9ebed4d blueswir1
        d.d = DT1;                                                \
2327 e9ebed4d blueswir1
                                                                  \
2328 e9ebed4d blueswir1
        d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0;       \
2329 e9ebed4d blueswir1
        d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0;      \
2330 e9ebed4d blueswir1
                                                                  \
2331 e9ebed4d blueswir1
        DT0 = d.d;                                                \
2332 e9ebed4d blueswir1
    }
2333 e9ebed4d blueswir1
2334 e9ebed4d blueswir1
#define FCMPGT(a, b) ((a) > (b))
2335 e9ebed4d blueswir1
#define FCMPEQ(a, b) ((a) == (b))
2336 e9ebed4d blueswir1
#define FCMPLE(a, b) ((a) <= (b))
2337 e9ebed4d blueswir1
#define FCMPNE(a, b) ((a) != (b))
2338 e9ebed4d blueswir1
2339 e9ebed4d blueswir1
VIS_CMPOP(op_fcmpgt, FCMPGT)
2340 e9ebed4d blueswir1
VIS_CMPOP(op_fcmpeq, FCMPEQ)
2341 e9ebed4d blueswir1
VIS_CMPOP(op_fcmple, FCMPLE)
2342 e9ebed4d blueswir1
VIS_CMPOP(op_fcmpne, FCMPNE)
2343 e9ebed4d blueswir1
2344 725cb90b bellard
#endif