Revision 5dcb6b91 hw/fdc.c
| b/hw/fdc.c | ||
|---|---|---|
| 370 | 370 |
/* HW */ |
| 371 | 371 |
qemu_irq irq; |
| 372 | 372 |
int dma_chann; |
| 373 |
uint32_t io_base;
|
|
| 373 |
target_phys_addr_t io_base;
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|
| 374 | 374 |
/* Controller state */ |
| 375 | 375 |
QEMUTimer *result_timer; |
| 376 | 376 |
uint8_t state; |
| ... | ... | |
| 464 | 464 |
|
| 465 | 465 |
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg) |
| 466 | 466 |
{
|
| 467 |
return fdctrl_read(opaque, reg); |
|
| 467 |
return fdctrl_read(opaque, (uint32_t)reg);
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|
| 468 | 468 |
} |
| 469 | 469 |
|
| 470 | 470 |
static void fdctrl_write_mem (void *opaque, |
| 471 | 471 |
target_phys_addr_t reg, uint32_t value) |
| 472 | 472 |
{
|
| 473 |
fdctrl_write(opaque, reg, value); |
|
| 473 |
fdctrl_write(opaque, (uint32_t)reg, value);
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|
| 474 | 474 |
} |
| 475 | 475 |
|
| 476 | 476 |
static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
|
| ... | ... | |
| 579 | 579 |
} |
| 580 | 580 |
|
| 581 | 581 |
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, |
| 582 |
uint32_t io_base,
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|
| 582 |
target_phys_addr_t io_base,
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|
| 583 | 583 |
BlockDriverState **fds) |
| 584 | 584 |
{
|
| 585 | 585 |
fdctrl_t *fdctrl; |
| ... | ... | |
| 613 | 613 |
io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write, fdctrl); |
| 614 | 614 |
cpu_register_physical_memory(io_base, 0x08, io_mem); |
| 615 | 615 |
} else {
|
| 616 |
register_ioport_read(io_base + 0x01, 5, 1, &fdctrl_read, fdctrl); |
|
| 617 |
register_ioport_read(io_base + 0x07, 1, 1, &fdctrl_read, fdctrl); |
|
| 618 |
register_ioport_write(io_base + 0x01, 5, 1, &fdctrl_write, fdctrl); |
|
| 619 |
register_ioport_write(io_base + 0x07, 1, 1, &fdctrl_write, fdctrl); |
|
| 616 |
register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read, |
|
| 617 |
fdctrl); |
|
| 618 |
register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read, |
|
| 619 |
fdctrl); |
|
| 620 |
register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write, |
|
| 621 |
fdctrl); |
|
| 622 |
register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write, |
|
| 623 |
fdctrl); |
|
| 620 | 624 |
} |
| 621 | 625 |
register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
|
| 622 | 626 |
qemu_register_reset(fdctrl_external_reset, fdctrl); |
Also available in: Unified diff