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/*
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* QEMU Parallel PORT emulation
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2007 Marko Kohtala
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-char.h" |
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#include "isa.h" |
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#include "pc.h" |
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//#define DEBUG_PARALLEL
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#ifdef DEBUG_PARALLEL
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#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg) |
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#else
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#define pdebug(fmt, arg...) ((void)0) |
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#endif
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#define PARA_REG_DATA 0 |
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#define PARA_REG_STS 1 |
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#define PARA_REG_CTR 2 |
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#define PARA_REG_EPP_ADDR 3 |
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#define PARA_REG_EPP_DATA 4 |
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/*
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* These are the definitions for the Printer Status Register
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*/
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#define PARA_STS_BUSY 0x80 /* Busy complement */ |
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#define PARA_STS_ACK 0x40 /* Acknowledge */ |
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#define PARA_STS_PAPER 0x20 /* Out of paper */ |
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#define PARA_STS_ONLINE 0x10 /* Online */ |
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#define PARA_STS_ERROR 0x08 /* Error complement */ |
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#define PARA_STS_TMOUT 0x01 /* EPP timeout */ |
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/*
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* These are the definitions for the Printer Control Register
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*/
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#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ |
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#define PARA_CTR_INTEN 0x10 /* IRQ Enable */ |
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#define PARA_CTR_SELECT 0x08 /* Select In complement */ |
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#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ |
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#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ |
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#define PARA_CTR_STROBE 0x01 /* Strobe complement */ |
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#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
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struct ParallelState {
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uint8_t dataw; |
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uint8_t datar; |
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uint8_t status; |
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uint8_t control; |
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qemu_irq irq; |
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int irq_pending;
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CharDriverState *chr; |
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int hw_driver;
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int epp_timeout;
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uint32_t last_read_offset; /* For debugging */
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/* Memory-mapped interface */
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int it_shift;
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}; |
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static void parallel_update_irq(ParallelState *s) |
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{ |
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if (s->irq_pending)
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qemu_irq_raise(s->irq); |
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else
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qemu_irq_lower(s->irq); |
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} |
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static void |
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parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
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{ |
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ParallelState *s = opaque; |
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pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
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addr &= 7;
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switch(addr) {
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case PARA_REG_DATA:
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s->dataw = val; |
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parallel_update_irq(s); |
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break;
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case PARA_REG_CTR:
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val |= 0xc0;
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if ((val & PARA_CTR_INIT) == 0 ) { |
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s->status = PARA_STS_BUSY; |
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s->status |= PARA_STS_ACK; |
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s->status |= PARA_STS_ONLINE; |
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s->status |= PARA_STS_ERROR; |
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} |
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else if (val & PARA_CTR_SELECT) { |
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if (val & PARA_CTR_STROBE) {
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s->status &= ~PARA_STS_BUSY; |
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if ((s->control & PARA_CTR_STROBE) == 0) |
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qemu_chr_write(s->chr, &s->dataw, 1);
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} else {
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if (s->control & PARA_CTR_INTEN) {
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s->irq_pending = 1;
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} |
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} |
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} |
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parallel_update_irq(s); |
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s->control = val; |
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break;
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} |
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} |
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static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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ParallelState *s = opaque; |
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uint8_t parm = val; |
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int dir;
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/* Sometimes programs do several writes for timing purposes on old
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HW. Take care not to waste time on writes that do nothing. */
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s->last_read_offset = ~0U;
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addr &= 7;
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switch(addr) {
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case PARA_REG_DATA:
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if (s->dataw == val)
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return;
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pdebug("wd%02x\n", val);
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); |
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s->dataw = val; |
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break;
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case PARA_REG_STS:
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pdebug("ws%02x\n", val);
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if (val & PARA_STS_TMOUT)
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s->epp_timeout = 0;
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break;
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case PARA_REG_CTR:
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val |= 0xc0;
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if (s->control == val)
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return;
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pdebug("wc%02x\n", val);
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if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
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if (val & PARA_CTR_DIR) {
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dir = 1;
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} else {
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dir = 0;
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} |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); |
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parm &= ~PARA_CTR_DIR; |
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} |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
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s->control = val; |
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break;
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case PARA_REG_EPP_ADDR:
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
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/* Controls not correct for EPP address cycle, so do nothing */
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pdebug("wa%02x s\n", val);
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else {
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struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
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if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
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s->epp_timeout = 1;
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pdebug("wa%02x t\n", val);
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} |
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else
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pdebug("wa%02x\n", val);
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} |
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break;
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case PARA_REG_EPP_DATA:
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
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/* Controls not correct for EPP data cycle, so do nothing */
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pdebug("we%02x s\n", val);
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else {
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struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
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if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
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s->epp_timeout = 1;
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pdebug("we%02x t\n", val);
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} |
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else
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pdebug("we%02x\n", val);
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} |
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break;
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} |
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} |
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static void |
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parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
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{ |
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ParallelState *s = opaque; |
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uint16_t eppdata = cpu_to_le16(val); |
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int err;
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struct ParallelIOArg ioarg = {
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.buffer = &eppdata, .count = sizeof(eppdata)
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}; |
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
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/* Controls not correct for EPP data cycle, so do nothing */
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pdebug("we%04x s\n", val);
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return;
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} |
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err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
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if (err) {
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s->epp_timeout = 1;
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pdebug("we%04x t\n", val);
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} |
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else
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pdebug("we%04x\n", val);
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} |
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static void |
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parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
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{ |
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ParallelState *s = opaque; |
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uint32_t eppdata = cpu_to_le32(val); |
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int err;
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struct ParallelIOArg ioarg = {
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.buffer = &eppdata, .count = sizeof(eppdata)
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}; |
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
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/* Controls not correct for EPP data cycle, so do nothing */
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pdebug("we%08x s\n", val);
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return;
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} |
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err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
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if (err) {
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s->epp_timeout = 1;
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pdebug("we%08x t\n", val);
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} |
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else
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pdebug("we%08x\n", val);
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} |
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static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) |
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{ |
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ParallelState *s = opaque; |
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uint32_t ret = 0xff;
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addr &= 7;
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switch(addr) {
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case PARA_REG_DATA:
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if (s->control & PARA_CTR_DIR)
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ret = s->datar; |
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else
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ret = s->dataw; |
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break;
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case PARA_REG_STS:
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ret = s->status; |
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s->irq_pending = 0;
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if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { |
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/* XXX Fixme: wait 5 microseconds */
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if (s->status & PARA_STS_ACK)
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s->status &= ~PARA_STS_ACK; |
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else {
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/* XXX Fixme: wait 5 microseconds */
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s->status |= PARA_STS_ACK; |
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s->status |= PARA_STS_BUSY; |
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} |
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} |
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parallel_update_irq(s); |
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break;
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case PARA_REG_CTR:
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ret = s->control; |
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break;
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} |
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pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
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return ret;
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} |
283 |
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static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) |
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{ |
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ParallelState *s = opaque; |
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uint8_t ret = 0xff;
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addr &= 7;
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switch(addr) {
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case PARA_REG_DATA:
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); |
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if (s->last_read_offset != addr || s->datar != ret)
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pdebug("rd%02x\n", ret);
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s->datar = ret; |
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break;
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case PARA_REG_STS:
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); |
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ret &= ~PARA_STS_TMOUT; |
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if (s->epp_timeout)
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ret |= PARA_STS_TMOUT; |
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if (s->last_read_offset != addr || s->status != ret)
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pdebug("rs%02x\n", ret);
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s->status = ret; |
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break;
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case PARA_REG_CTR:
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/* s->control has some bits fixed to 1. It is zero only when
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it has not been yet written to. */
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if (s->control == 0) { |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); |
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if (s->last_read_offset != addr)
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pdebug("rc%02x\n", ret);
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s->control = ret; |
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} |
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else {
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ret = s->control; |
316 |
if (s->last_read_offset != addr)
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pdebug("rc%02x\n", ret);
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} |
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break;
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case PARA_REG_EPP_ADDR:
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
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/* Controls not correct for EPP addr cycle, so do nothing */
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pdebug("ra%02x s\n", ret);
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else {
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struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
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if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
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s->epp_timeout = 1;
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pdebug("ra%02x t\n", ret);
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} |
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else
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pdebug("ra%02x\n", ret);
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} |
333 |
break;
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case PARA_REG_EPP_DATA:
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
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/* Controls not correct for EPP data cycle, so do nothing */
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pdebug("re%02x s\n", ret);
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else {
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struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
340 |
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
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s->epp_timeout = 1;
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pdebug("re%02x t\n", ret);
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} |
344 |
else
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pdebug("re%02x\n", ret);
|
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} |
347 |
break;
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} |
349 |
s->last_read_offset = addr; |
350 |
return ret;
|
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} |
352 |
|
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static uint32_t
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parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
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{ |
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ParallelState *s = opaque; |
357 |
uint32_t ret; |
358 |
uint16_t eppdata = ~0;
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359 |
int err;
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360 |
struct ParallelIOArg ioarg = {
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.buffer = &eppdata, .count = sizeof(eppdata)
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}; |
363 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
364 |
/* Controls not correct for EPP data cycle, so do nothing */
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365 |
pdebug("re%04x s\n", eppdata);
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return eppdata;
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} |
368 |
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
369 |
ret = le16_to_cpu(eppdata); |
370 |
|
371 |
if (err) {
|
372 |
s->epp_timeout = 1;
|
373 |
pdebug("re%04x t\n", ret);
|
374 |
} |
375 |
else
|
376 |
pdebug("re%04x\n", ret);
|
377 |
return ret;
|
378 |
} |
379 |
|
380 |
static uint32_t
|
381 |
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
|
382 |
{ |
383 |
ParallelState *s = opaque; |
384 |
uint32_t ret; |
385 |
uint32_t eppdata = ~0U;
|
386 |
int err;
|
387 |
struct ParallelIOArg ioarg = {
|
388 |
.buffer = &eppdata, .count = sizeof(eppdata)
|
389 |
}; |
390 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
391 |
/* Controls not correct for EPP data cycle, so do nothing */
|
392 |
pdebug("re%08x s\n", eppdata);
|
393 |
return eppdata;
|
394 |
} |
395 |
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
396 |
ret = le32_to_cpu(eppdata); |
397 |
|
398 |
if (err) {
|
399 |
s->epp_timeout = 1;
|
400 |
pdebug("re%08x t\n", ret);
|
401 |
} |
402 |
else
|
403 |
pdebug("re%08x\n", ret);
|
404 |
return ret;
|
405 |
} |
406 |
|
407 |
static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) |
408 |
{ |
409 |
addr &= 7;
|
410 |
pdebug("wecp%d=%02x\n", addr, val);
|
411 |
} |
412 |
|
413 |
static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) |
414 |
{ |
415 |
uint8_t ret = 0xff;
|
416 |
addr &= 7;
|
417 |
pdebug("recp%d:%02x\n", addr, ret);
|
418 |
return ret;
|
419 |
} |
420 |
|
421 |
static void parallel_reset(void *opaque) |
422 |
{ |
423 |
ParallelState *s = opaque; |
424 |
|
425 |
s->datar = ~0;
|
426 |
s->dataw = ~0;
|
427 |
s->status = PARA_STS_BUSY; |
428 |
s->status |= PARA_STS_ACK; |
429 |
s->status |= PARA_STS_ONLINE; |
430 |
s->status |= PARA_STS_ERROR; |
431 |
s->status |= PARA_STS_TMOUT; |
432 |
s->control = PARA_CTR_SELECT; |
433 |
s->control |= PARA_CTR_INIT; |
434 |
s->control |= 0xc0;
|
435 |
s->irq_pending = 0;
|
436 |
s->hw_driver = 0;
|
437 |
s->epp_timeout = 0;
|
438 |
s->last_read_offset = ~0U;
|
439 |
} |
440 |
|
441 |
/* If fd is zero, it means that the parallel device uses the console */
|
442 |
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
|
443 |
{ |
444 |
ParallelState *s; |
445 |
uint8_t dummy; |
446 |
|
447 |
s = qemu_mallocz(sizeof(ParallelState));
|
448 |
if (!s)
|
449 |
return NULL; |
450 |
s->irq = irq; |
451 |
s->chr = chr; |
452 |
parallel_reset(s); |
453 |
qemu_register_reset(parallel_reset, s); |
454 |
|
455 |
if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { |
456 |
s->hw_driver = 1;
|
457 |
s->status = dummy; |
458 |
} |
459 |
|
460 |
if (s->hw_driver) {
|
461 |
register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s); |
462 |
register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s); |
463 |
register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s); |
464 |
register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s); |
465 |
register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s); |
466 |
register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s); |
467 |
register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s); |
468 |
register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s); |
469 |
} |
470 |
else {
|
471 |
register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s); |
472 |
register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s); |
473 |
} |
474 |
return s;
|
475 |
} |
476 |
|
477 |
/* Memory mapped interface */
|
478 |
static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr) |
479 |
{ |
480 |
ParallelState *s = opaque; |
481 |
|
482 |
return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; |
483 |
} |
484 |
|
485 |
static void parallel_mm_writeb (void *opaque, |
486 |
target_phys_addr_t addr, uint32_t value) |
487 |
{ |
488 |
ParallelState *s = opaque; |
489 |
|
490 |
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
|
491 |
} |
492 |
|
493 |
static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr) |
494 |
{ |
495 |
ParallelState *s = opaque; |
496 |
|
497 |
return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; |
498 |
} |
499 |
|
500 |
static void parallel_mm_writew (void *opaque, |
501 |
target_phys_addr_t addr, uint32_t value) |
502 |
{ |
503 |
ParallelState *s = opaque; |
504 |
|
505 |
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
|
506 |
} |
507 |
|
508 |
static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr) |
509 |
{ |
510 |
ParallelState *s = opaque; |
511 |
|
512 |
return parallel_ioport_read_sw(s, addr >> s->it_shift);
|
513 |
} |
514 |
|
515 |
static void parallel_mm_writel (void *opaque, |
516 |
target_phys_addr_t addr, uint32_t value) |
517 |
{ |
518 |
ParallelState *s = opaque; |
519 |
|
520 |
parallel_ioport_write_sw(s, addr >> s->it_shift, value); |
521 |
} |
522 |
|
523 |
static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
|
524 |
¶llel_mm_readb, |
525 |
¶llel_mm_readw, |
526 |
¶llel_mm_readl, |
527 |
}; |
528 |
|
529 |
static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
|
530 |
¶llel_mm_writeb, |
531 |
¶llel_mm_writew, |
532 |
¶llel_mm_writel, |
533 |
}; |
534 |
|
535 |
/* If fd is zero, it means that the parallel device uses the console */
|
536 |
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
|
537 |
{ |
538 |
ParallelState *s; |
539 |
int io_sw;
|
540 |
|
541 |
s = qemu_mallocz(sizeof(ParallelState));
|
542 |
if (!s)
|
543 |
return NULL; |
544 |
s->irq = irq; |
545 |
s->chr = chr; |
546 |
s->it_shift = it_shift; |
547 |
parallel_reset(s); |
548 |
qemu_register_reset(parallel_reset, s); |
549 |
|
550 |
io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
|
551 |
cpu_register_physical_memory(base, 8 << it_shift, io_sw);
|
552 |
return s;
|
553 |
} |