root / tcg / tcg-opc.h @ 5e143c43
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| 1 | c896fe29 | bellard | /*
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| 2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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| 3 | c896fe29 | bellard | *
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| 4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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| 5 | c896fe29 | bellard | *
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| 6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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| 7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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| 8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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| 9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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| 10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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| 11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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| 12 | c896fe29 | bellard | *
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| 13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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| 14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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| 15 | c896fe29 | bellard | *
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| 16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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| 20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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| 21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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| 22 | c896fe29 | bellard | * THE SOFTWARE.
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| 23 | c896fe29 | bellard | */
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| 24 | c896fe29 | bellard | #ifndef DEF2
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| 25 | c896fe29 | bellard | #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0) |
| 26 | c896fe29 | bellard | #endif
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| 27 | c896fe29 | bellard | |
| 28 | c896fe29 | bellard | /* predefined ops */
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| 29 | c896fe29 | bellard | DEF2(end, 0, 0, 0, 0) /* must be kept first */ |
| 30 | c896fe29 | bellard | DEF2(nop, 0, 0, 0, 0) |
| 31 | c896fe29 | bellard | DEF2(nop1, 0, 0, 1, 0) |
| 32 | c896fe29 | bellard | DEF2(nop2, 0, 0, 2, 0) |
| 33 | c896fe29 | bellard | DEF2(nop3, 0, 0, 3, 0) |
| 34 | c896fe29 | bellard | DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */ |
| 35 | c896fe29 | bellard | |
| 36 | 5ff9d6a4 | bellard | DEF2(discard, 1, 0, 0, 0) |
| 37 | 5ff9d6a4 | bellard | |
| 38 | c896fe29 | bellard | DEF2(set_label, 0, 0, 1, 0) |
| 39 | 5ff9d6a4 | bellard | DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ |
| 40 | 5ff9d6a4 | bellard | DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 41 | 5ff9d6a4 | bellard | DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 42 | c896fe29 | bellard | |
| 43 | c896fe29 | bellard | DEF2(mov_i32, 1, 1, 0, 0) |
| 44 | c896fe29 | bellard | DEF2(movi_i32, 1, 0, 1, 0) |
| 45 | c896fe29 | bellard | /* load/store */
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| 46 | c896fe29 | bellard | DEF2(ld8u_i32, 1, 1, 1, 0) |
| 47 | c896fe29 | bellard | DEF2(ld8s_i32, 1, 1, 1, 0) |
| 48 | c896fe29 | bellard | DEF2(ld16u_i32, 1, 1, 1, 0) |
| 49 | c896fe29 | bellard | DEF2(ld16s_i32, 1, 1, 1, 0) |
| 50 | c896fe29 | bellard | DEF2(ld_i32, 1, 1, 1, 0) |
| 51 | 5ff9d6a4 | bellard | DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 52 | 5ff9d6a4 | bellard | DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 53 | 5ff9d6a4 | bellard | DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 54 | c896fe29 | bellard | /* arith */
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| 55 | c896fe29 | bellard | DEF2(add_i32, 1, 2, 0, 0) |
| 56 | c896fe29 | bellard | DEF2(sub_i32, 1, 2, 0, 0) |
| 57 | c896fe29 | bellard | DEF2(mul_i32, 1, 2, 0, 0) |
| 58 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i32
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| 59 | c896fe29 | bellard | DEF2(div_i32, 1, 2, 0, 0) |
| 60 | c896fe29 | bellard | DEF2(divu_i32, 1, 2, 0, 0) |
| 61 | c896fe29 | bellard | DEF2(rem_i32, 1, 2, 0, 0) |
| 62 | c896fe29 | bellard | DEF2(remu_i32, 1, 2, 0, 0) |
| 63 | c896fe29 | bellard | #else
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| 64 | c896fe29 | bellard | DEF2(div2_i32, 2, 3, 0, 0) |
| 65 | c896fe29 | bellard | DEF2(divu2_i32, 2, 3, 0, 0) |
| 66 | c896fe29 | bellard | #endif
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| 67 | c896fe29 | bellard | DEF2(and_i32, 1, 2, 0, 0) |
| 68 | c896fe29 | bellard | DEF2(or_i32, 1, 2, 0, 0) |
| 69 | c896fe29 | bellard | DEF2(xor_i32, 1, 2, 0, 0) |
| 70 | d42f183c | aurel32 | /* shifts/rotates */
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| 71 | c896fe29 | bellard | DEF2(shl_i32, 1, 2, 0, 0) |
| 72 | c896fe29 | bellard | DEF2(shr_i32, 1, 2, 0, 0) |
| 73 | c896fe29 | bellard | DEF2(sar_i32, 1, 2, 0, 0) |
| 74 | f31e9370 | aurel32 | #ifdef TCG_TARGET_HAS_rot_i32
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| 75 | d42f183c | aurel32 | DEF2(rotl_i32, 1, 2, 0, 0) |
| 76 | d42f183c | aurel32 | DEF2(rotr_i32, 1, 2, 0, 0) |
| 77 | f31e9370 | aurel32 | #endif
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| 78 | c896fe29 | bellard | |
| 79 | 5ff9d6a4 | bellard | DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 80 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
| 81 | c896fe29 | bellard | DEF2(add2_i32, 2, 4, 0, 0) |
| 82 | c896fe29 | bellard | DEF2(sub2_i32, 2, 4, 0, 0) |
| 83 | 5ff9d6a4 | bellard | DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 84 | c896fe29 | bellard | DEF2(mulu2_i32, 2, 2, 0, 0) |
| 85 | c896fe29 | bellard | #endif
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| 86 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i32
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| 87 | c896fe29 | bellard | DEF2(ext8s_i32, 1, 1, 0, 0) |
| 88 | c896fe29 | bellard | #endif
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| 89 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i32
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| 90 | c896fe29 | bellard | DEF2(ext16s_i32, 1, 1, 0, 0) |
| 91 | c896fe29 | bellard | #endif
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| 92 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext8u_i32
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| 93 | cfc86988 | Aurelien Jarno | DEF2(ext8u_i32, 1, 1, 0, 0) |
| 94 | cfc86988 | Aurelien Jarno | #endif
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| 95 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext16u_i32
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| 96 | cfc86988 | Aurelien Jarno | DEF2(ext16u_i32, 1, 1, 0, 0) |
| 97 | cfc86988 | Aurelien Jarno | #endif
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| 98 | 84aafb06 | aurel32 | #ifdef TCG_TARGET_HAS_bswap16_i32
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| 99 | 84aafb06 | aurel32 | DEF2(bswap16_i32, 1, 1, 0, 0) |
| 100 | 84aafb06 | aurel32 | #endif
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| 101 | 66896cb8 | aurel32 | #ifdef TCG_TARGET_HAS_bswap32_i32
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| 102 | 66896cb8 | aurel32 | DEF2(bswap32_i32, 1, 1, 0, 0) |
| 103 | c896fe29 | bellard | #endif
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| 104 | 0dd0dd55 | aurel32 | #ifdef TCG_TARGET_HAS_not_i32
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| 105 | 0dd0dd55 | aurel32 | DEF2(not_i32, 1, 1, 0, 0) |
| 106 | 0dd0dd55 | aurel32 | #endif
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| 107 | 0dd0dd55 | aurel32 | #ifdef TCG_TARGET_HAS_neg_i32
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| 108 | 0dd0dd55 | aurel32 | DEF2(neg_i32, 1, 1, 0, 0) |
| 109 | 0dd0dd55 | aurel32 | #endif
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| 110 | c896fe29 | bellard | |
| 111 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 64 |
| 112 | c896fe29 | bellard | DEF2(mov_i64, 1, 1, 0, 0) |
| 113 | c896fe29 | bellard | DEF2(movi_i64, 1, 0, 1, 0) |
| 114 | c896fe29 | bellard | /* load/store */
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| 115 | c896fe29 | bellard | DEF2(ld8u_i64, 1, 1, 1, 0) |
| 116 | c896fe29 | bellard | DEF2(ld8s_i64, 1, 1, 1, 0) |
| 117 | c896fe29 | bellard | DEF2(ld16u_i64, 1, 1, 1, 0) |
| 118 | c896fe29 | bellard | DEF2(ld16s_i64, 1, 1, 1, 0) |
| 119 | c896fe29 | bellard | DEF2(ld32u_i64, 1, 1, 1, 0) |
| 120 | c896fe29 | bellard | DEF2(ld32s_i64, 1, 1, 1, 0) |
| 121 | c896fe29 | bellard | DEF2(ld_i64, 1, 1, 1, 0) |
| 122 | 5ff9d6a4 | bellard | DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 123 | 5ff9d6a4 | bellard | DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 124 | 5ff9d6a4 | bellard | DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 125 | 5ff9d6a4 | bellard | DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 126 | c896fe29 | bellard | /* arith */
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| 127 | c896fe29 | bellard | DEF2(add_i64, 1, 2, 0, 0) |
| 128 | c896fe29 | bellard | DEF2(sub_i64, 1, 2, 0, 0) |
| 129 | c896fe29 | bellard | DEF2(mul_i64, 1, 2, 0, 0) |
| 130 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i64
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| 131 | c896fe29 | bellard | DEF2(div_i64, 1, 2, 0, 0) |
| 132 | c896fe29 | bellard | DEF2(divu_i64, 1, 2, 0, 0) |
| 133 | c896fe29 | bellard | DEF2(rem_i64, 1, 2, 0, 0) |
| 134 | c896fe29 | bellard | DEF2(remu_i64, 1, 2, 0, 0) |
| 135 | c896fe29 | bellard | #else
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| 136 | c896fe29 | bellard | DEF2(div2_i64, 2, 3, 0, 0) |
| 137 | c896fe29 | bellard | DEF2(divu2_i64, 2, 3, 0, 0) |
| 138 | c896fe29 | bellard | #endif
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| 139 | c896fe29 | bellard | DEF2(and_i64, 1, 2, 0, 0) |
| 140 | c896fe29 | bellard | DEF2(or_i64, 1, 2, 0, 0) |
| 141 | c896fe29 | bellard | DEF2(xor_i64, 1, 2, 0, 0) |
| 142 | d42f183c | aurel32 | /* shifts/rotates */
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| 143 | c896fe29 | bellard | DEF2(shl_i64, 1, 2, 0, 0) |
| 144 | c896fe29 | bellard | DEF2(shr_i64, 1, 2, 0, 0) |
| 145 | c896fe29 | bellard | DEF2(sar_i64, 1, 2, 0, 0) |
| 146 | f31e9370 | aurel32 | #ifdef TCG_TARGET_HAS_rot_i64
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| 147 | d42f183c | aurel32 | DEF2(rotl_i64, 1, 2, 0, 0) |
| 148 | d42f183c | aurel32 | DEF2(rotr_i64, 1, 2, 0, 0) |
| 149 | f31e9370 | aurel32 | #endif
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| 150 | c896fe29 | bellard | |
| 151 | 5ff9d6a4 | bellard | DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 152 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i64
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| 153 | c896fe29 | bellard | DEF2(ext8s_i64, 1, 1, 0, 0) |
| 154 | c896fe29 | bellard | #endif
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| 155 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i64
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| 156 | c896fe29 | bellard | DEF2(ext16s_i64, 1, 1, 0, 0) |
| 157 | c896fe29 | bellard | #endif
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| 158 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext32s_i64
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| 159 | c896fe29 | bellard | DEF2(ext32s_i64, 1, 1, 0, 0) |
| 160 | c896fe29 | bellard | #endif
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| 161 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext8u_i64
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| 162 | cfc86988 | Aurelien Jarno | DEF2(ext8u_i64, 1, 1, 0, 0) |
| 163 | cfc86988 | Aurelien Jarno | #endif
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| 164 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext16u_i64
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| 165 | cfc86988 | Aurelien Jarno | DEF2(ext16u_i64, 1, 1, 0, 0) |
| 166 | cfc86988 | Aurelien Jarno | #endif
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| 167 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext32u_i64
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| 168 | cfc86988 | Aurelien Jarno | DEF2(ext32u_i64, 1, 1, 0, 0) |
| 169 | cfc86988 | Aurelien Jarno | #endif
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| 170 | 9a5c57fd | aurel32 | #ifdef TCG_TARGET_HAS_bswap16_i64
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| 171 | 9a5c57fd | aurel32 | DEF2(bswap16_i64, 1, 1, 0, 0) |
| 172 | 9a5c57fd | aurel32 | #endif
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| 173 | 9a5c57fd | aurel32 | #ifdef TCG_TARGET_HAS_bswap32_i64
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| 174 | 9a5c57fd | aurel32 | DEF2(bswap32_i64, 1, 1, 0, 0) |
| 175 | 9a5c57fd | aurel32 | #endif
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| 176 | 66896cb8 | aurel32 | #ifdef TCG_TARGET_HAS_bswap64_i64
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| 177 | 66896cb8 | aurel32 | DEF2(bswap64_i64, 1, 1, 0, 0) |
| 178 | c896fe29 | bellard | #endif
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| 179 | d2604285 | aurel32 | #ifdef TCG_TARGET_HAS_not_i64
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| 180 | d2604285 | aurel32 | DEF2(not_i64, 1, 1, 0, 0) |
| 181 | d2604285 | aurel32 | #endif
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| 182 | 390efc54 | pbrook | #ifdef TCG_TARGET_HAS_neg_i64
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| 183 | 390efc54 | pbrook | DEF2(neg_i64, 1, 1, 0, 0) |
| 184 | 390efc54 | pbrook | #endif
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| 185 | 0dd0dd55 | aurel32 | #endif
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| 186 | c896fe29 | bellard | |
| 187 | c896fe29 | bellard | /* QEMU specific */
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| 188 | 7e4597d7 | bellard | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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| 189 | 7e4597d7 | bellard | DEF2(debug_insn_start, 0, 0, 2, 0) |
| 190 | 7e4597d7 | bellard | #else
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| 191 | 7e4597d7 | bellard | DEF2(debug_insn_start, 0, 0, 1, 0) |
| 192 | 7e4597d7 | bellard | #endif
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| 193 | 5ff9d6a4 | bellard | DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 194 | 5ff9d6a4 | bellard | DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 195 | c896fe29 | bellard | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
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| 196 | c896fe29 | bellard | constants must be defined */
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| 197 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
| 198 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 199 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 200 | c896fe29 | bellard | #else
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| 201 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 202 | c896fe29 | bellard | #endif
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| 203 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 204 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 205 | c896fe29 | bellard | #else
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| 206 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 207 | c896fe29 | bellard | #endif
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| 208 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 209 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 210 | c896fe29 | bellard | #else
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| 211 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 212 | c896fe29 | bellard | #endif
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| 213 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 214 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 215 | c896fe29 | bellard | #else
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| 216 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 217 | c896fe29 | bellard | #endif
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| 218 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 219 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 220 | c896fe29 | bellard | #else
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| 221 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 222 | c896fe29 | bellard | #endif
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| 223 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 224 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 225 | c896fe29 | bellard | #else
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| 226 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 227 | c896fe29 | bellard | #endif
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| 228 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 229 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 230 | c896fe29 | bellard | #else
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| 231 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 232 | c896fe29 | bellard | #endif
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| 233 | c896fe29 | bellard | |
| 234 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 235 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 236 | c896fe29 | bellard | #else
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| 237 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 238 | c896fe29 | bellard | #endif
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| 239 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 240 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 241 | c896fe29 | bellard | #else
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| 242 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 243 | c896fe29 | bellard | #endif
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| 244 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 245 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 246 | c896fe29 | bellard | #else
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| 247 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 248 | c896fe29 | bellard | #endif
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| 249 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 250 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 251 | c896fe29 | bellard | #else
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| 252 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 253 | c896fe29 | bellard | #endif
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| 254 | c896fe29 | bellard | |
| 255 | c896fe29 | bellard | #else /* TCG_TARGET_REG_BITS == 32 */ |
| 256 | c896fe29 | bellard | |
| 257 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 258 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 259 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 260 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 261 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 262 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 263 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 264 | c896fe29 | bellard | |
| 265 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 266 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 267 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 268 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 269 | c896fe29 | bellard | |
| 270 | c896fe29 | bellard | #endif /* TCG_TARGET_REG_BITS != 32 */ |
| 271 | c896fe29 | bellard | |
| 272 | c896fe29 | bellard | #undef DEF2 |