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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM virtual CPU header
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #ifndef CPU_ARM_H
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21 | 2c0262af | bellard | #define CPU_ARM_H
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22 | 2c0262af | bellard | |
23 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
24 | 3cf1e035 | bellard | |
25 | 9042c0e2 | ths | #define ELF_MACHINE EM_ARM
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26 | 9042c0e2 | ths | |
27 | 2c0262af | bellard | #include "cpu-defs.h" |
28 | 2c0262af | bellard | |
29 | 53cd6637 | bellard | #include "softfloat.h" |
30 | 53cd6637 | bellard | |
31 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
32 | 1fddef4b | bellard | |
33 | b8a9e8f1 | bellard | #define EXCP_UDEF 1 /* undefined instruction */ |
34 | b8a9e8f1 | bellard | #define EXCP_SWI 2 /* software interrupt */ |
35 | b8a9e8f1 | bellard | #define EXCP_PREFETCH_ABORT 3 |
36 | b8a9e8f1 | bellard | #define EXCP_DATA_ABORT 4 |
37 | b5ff1b31 | bellard | #define EXCP_IRQ 5 |
38 | b5ff1b31 | bellard | #define EXCP_FIQ 6 |
39 | 06c949e6 | pbrook | #define EXCP_BKPT 7 |
40 | 9ee6e8bb | pbrook | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
41 | 9ee6e8bb | pbrook | |
42 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_RESET 1 |
43 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_NMI 2 |
44 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_HARD 3 |
45 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_MEM 4 |
46 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_BUS 5 |
47 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_USAGE 6 |
48 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_SVC 11 |
49 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_DEBUG 12 |
50 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_PENDSV 14 |
51 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_SYSTICK 15 |
52 | 2c0262af | bellard | |
53 | c1713132 | balrog | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
54 | c1713132 | balrog | int srcreg, int operand, uint32_t value); |
55 | c1713132 | balrog | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, |
56 | c1713132 | balrog | int dstreg, int operand); |
57 | c1713132 | balrog | |
58 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
59 | 6ebbf390 | j_mayer | |
60 | b7bcbe95 | bellard | /* We currently assume float and double are IEEE single and double
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61 | b7bcbe95 | bellard | precision respectively.
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62 | b7bcbe95 | bellard | Doing runtime conversions is tricky because VFP registers may contain
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63 | b7bcbe95 | bellard | integer values (eg. as the result of a FTOSI instruction).
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64 | 8e96005d | bellard | s<2n> maps to the least significant half of d<n>
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65 | 8e96005d | bellard | s<2n+1> maps to the most significant half of d<n>
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66 | 8e96005d | bellard | */
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67 | b7bcbe95 | bellard | |
68 | 2c0262af | bellard | typedef struct CPUARMState { |
69 | b5ff1b31 | bellard | /* Regs for current mode. */
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70 | 2c0262af | bellard | uint32_t regs[16];
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71 | b5ff1b31 | bellard | /* Frequently accessed CPSR bits are stored separately for efficiently.
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72 | d37aca66 | pbrook | This contains all the other bits. Use cpsr_{read,write} to access
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73 | b5ff1b31 | bellard | the whole CPSR. */
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74 | b5ff1b31 | bellard | uint32_t uncached_cpsr; |
75 | b5ff1b31 | bellard | uint32_t spsr; |
76 | b5ff1b31 | bellard | |
77 | b5ff1b31 | bellard | /* Banked registers. */
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78 | b5ff1b31 | bellard | uint32_t banked_spsr[6];
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79 | b5ff1b31 | bellard | uint32_t banked_r13[6];
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80 | b5ff1b31 | bellard | uint32_t banked_r14[6];
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81 | 3b46e624 | ths | |
82 | b5ff1b31 | bellard | /* These hold r8-r12. */
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83 | b5ff1b31 | bellard | uint32_t usr_regs[5];
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84 | b5ff1b31 | bellard | uint32_t fiq_regs[5];
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85 | 3b46e624 | ths | |
86 | 2c0262af | bellard | /* cpsr flag cache for faster execution */
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87 | 2c0262af | bellard | uint32_t CF; /* 0 or 1 */
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88 | 2c0262af | bellard | uint32_t VF; /* V is the bit 31. All other bits are undefined */
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89 | 2c0262af | bellard | uint32_t NZF; /* N is bit 31. Z is computed from NZF */
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90 | 99c475ab | bellard | uint32_t QF; /* 0 or 1 */
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91 | 9ee6e8bb | pbrook | uint32_t GE; /* cpsr[19:16] */
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92 | b26eefb6 | pbrook | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
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93 | 9ee6e8bb | pbrook | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
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94 | 2c0262af | bellard | |
95 | b5ff1b31 | bellard | /* System control coprocessor (cp15) */
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96 | b5ff1b31 | bellard | struct {
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97 | 40f137e1 | pbrook | uint32_t c0_cpuid; |
98 | c1713132 | balrog | uint32_t c0_cachetype; |
99 | 9ee6e8bb | pbrook | uint32_t c0_c1[8]; /* Feature registers. */ |
100 | 9ee6e8bb | pbrook | uint32_t c0_c2[8]; /* Instruction set registers. */ |
101 | b5ff1b31 | bellard | uint32_t c1_sys; /* System control register. */
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102 | b5ff1b31 | bellard | uint32_t c1_coproc; /* Coprocessor access register. */
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103 | 610c3c8a | balrog | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
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104 | 9ee6e8bb | pbrook | uint32_t c2_base0; /* MMU translation table base 0. */
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105 | 9ee6e8bb | pbrook | uint32_t c2_base1; /* MMU translation table base 1. */
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106 | 9ee6e8bb | pbrook | uint32_t c2_mask; /* MMU translation table base mask. */
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107 | ce819861 | pbrook | uint32_t c2_data; /* MPU data cachable bits. */
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108 | ce819861 | pbrook | uint32_t c2_insn; /* MPU instruction cachable bits. */
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109 | ce819861 | pbrook | uint32_t c3; /* MMU domain access control register
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110 | ce819861 | pbrook | MPU write buffer control. */
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111 | b5ff1b31 | bellard | uint32_t c5_insn; /* Fault status registers. */
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112 | b5ff1b31 | bellard | uint32_t c5_data; |
113 | ce819861 | pbrook | uint32_t c6_region[8]; /* MPU base/size registers. */ |
114 | b5ff1b31 | bellard | uint32_t c6_insn; /* Fault address registers. */
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115 | b5ff1b31 | bellard | uint32_t c6_data; |
116 | b5ff1b31 | bellard | uint32_t c9_insn; /* Cache lockdown registers. */
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117 | b5ff1b31 | bellard | uint32_t c9_data; |
118 | b5ff1b31 | bellard | uint32_t c13_fcse; /* FCSE PID. */
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119 | b5ff1b31 | bellard | uint32_t c13_context; /* Context ID. */
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120 | 9ee6e8bb | pbrook | uint32_t c13_tls1; /* User RW Thread register. */
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121 | 9ee6e8bb | pbrook | uint32_t c13_tls2; /* User RO Thread register. */
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122 | 9ee6e8bb | pbrook | uint32_t c13_tls3; /* Privileged Thread register. */
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123 | c1713132 | balrog | uint32_t c15_cpar; /* XScale Coprocessor Access Register */
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124 | c3d2689d | balrog | uint32_t c15_ticonfig; /* TI925T configuration byte. */
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125 | c3d2689d | balrog | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
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126 | c3d2689d | balrog | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
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127 | c3d2689d | balrog | uint32_t c15_threadid; /* TI debugger thread-ID. */
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128 | b5ff1b31 | bellard | } cp15; |
129 | 40f137e1 | pbrook | |
130 | 9ee6e8bb | pbrook | struct {
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131 | 9ee6e8bb | pbrook | uint32_t other_sp; |
132 | 9ee6e8bb | pbrook | uint32_t vecbase; |
133 | 9ee6e8bb | pbrook | uint32_t basepri; |
134 | 9ee6e8bb | pbrook | uint32_t control; |
135 | 9ee6e8bb | pbrook | int current_sp;
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136 | 9ee6e8bb | pbrook | int exception;
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137 | 9ee6e8bb | pbrook | int pending_exception;
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138 | 9ee6e8bb | pbrook | void *nvic;
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139 | 9ee6e8bb | pbrook | } v7m; |
140 | 9ee6e8bb | pbrook | |
141 | c1713132 | balrog | /* Coprocessor IO used by peripherals */
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142 | c1713132 | balrog | struct {
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143 | c1713132 | balrog | ARMReadCPFunc *cp_read; |
144 | c1713132 | balrog | ARMWriteCPFunc *cp_write; |
145 | c1713132 | balrog | void *opaque;
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146 | c1713132 | balrog | } cp[15];
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147 | c1713132 | balrog | |
148 | 40f137e1 | pbrook | /* Internal CPU feature flags. */
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149 | 40f137e1 | pbrook | uint32_t features; |
150 | 40f137e1 | pbrook | |
151 | 9ee6e8bb | pbrook | /* Callback for vectored interrupt controller. */
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152 | 9ee6e8bb | pbrook | int (*get_irq_vector)(struct CPUARMState *); |
153 | 9ee6e8bb | pbrook | void *irq_opaque;
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154 | 9ee6e8bb | pbrook | |
155 | 2c0262af | bellard | /* exception/interrupt handling */
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156 | 2c0262af | bellard | jmp_buf jmp_env; |
157 | 2c0262af | bellard | int exception_index;
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158 | 2c0262af | bellard | int interrupt_request;
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159 | 2c0262af | bellard | int user_mode_only;
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160 | 9332f9da | bellard | int halted;
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161 | 2c0262af | bellard | |
162 | b7bcbe95 | bellard | /* VFP coprocessor state. */
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163 | b7bcbe95 | bellard | struct {
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164 | 9ee6e8bb | pbrook | float64 regs[32];
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165 | b7bcbe95 | bellard | |
166 | 40f137e1 | pbrook | uint32_t xregs[16];
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167 | b7bcbe95 | bellard | /* We store these fpcsr fields separately for convenience. */
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168 | b7bcbe95 | bellard | int vec_len;
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169 | b7bcbe95 | bellard | int vec_stride;
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170 | b7bcbe95 | bellard | |
171 | 9ee6e8bb | pbrook | /* scratch space when Tn are not sufficient. */
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172 | 9ee6e8bb | pbrook | uint32_t scratch[8];
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173 | 3b46e624 | ths | |
174 | 53cd6637 | bellard | float_status fp_status; |
175 | b7bcbe95 | bellard | } vfp; |
176 | 9ee6e8bb | pbrook | #if defined(CONFIG_USER_ONLY)
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177 | 9ee6e8bb | pbrook | struct mmon_state *mmon_entry;
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178 | 9ee6e8bb | pbrook | #else
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179 | 9ee6e8bb | pbrook | uint32_t mmon_addr; |
180 | 9ee6e8bb | pbrook | #endif
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181 | b7bcbe95 | bellard | |
182 | 18c9b560 | balrog | /* iwMMXt coprocessor state. */
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183 | 18c9b560 | balrog | struct {
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184 | 18c9b560 | balrog | uint64_t regs[16];
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185 | 18c9b560 | balrog | uint64_t val; |
186 | 18c9b560 | balrog | |
187 | 18c9b560 | balrog | uint32_t cregs[16];
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188 | 18c9b560 | balrog | } iwmmxt; |
189 | 18c9b560 | balrog | |
190 | ce4defa0 | pbrook | #if defined(CONFIG_USER_ONLY)
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191 | ce4defa0 | pbrook | /* For usermode syscall translation. */
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192 | ce4defa0 | pbrook | int eabi;
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193 | ce4defa0 | pbrook | #endif
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194 | ce4defa0 | pbrook | |
195 | a316d335 | bellard | CPU_COMMON |
196 | a316d335 | bellard | |
197 | 9d551997 | balrog | /* These fields after the common ones so they are preserved on reset. */
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198 | f3d6b95e | pbrook | int ram_size;
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199 | f3d6b95e | pbrook | const char *kernel_filename; |
200 | f3d6b95e | pbrook | const char *kernel_cmdline; |
201 | f3d6b95e | pbrook | const char *initrd_filename; |
202 | f3d6b95e | pbrook | int board_id;
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203 | 9d551997 | balrog | target_phys_addr_t loader_start; |
204 | 2c0262af | bellard | } CPUARMState; |
205 | 2c0262af | bellard | |
206 | aaed909a | bellard | CPUARMState *cpu_arm_init(const char *cpu_model); |
207 | b26eefb6 | pbrook | void arm_translate_init(void); |
208 | 2c0262af | bellard | int cpu_arm_exec(CPUARMState *s);
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209 | 2c0262af | bellard | void cpu_arm_close(CPUARMState *s);
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210 | b5ff1b31 | bellard | void do_interrupt(CPUARMState *);
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211 | b5ff1b31 | bellard | void switch_mode(CPUARMState *, int); |
212 | 9ee6e8bb | pbrook | uint32_t do_arm_semihosting(CPUARMState *env); |
213 | b5ff1b31 | bellard | |
214 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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215 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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216 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
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217 | 5fafdf24 | ths | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
218 | 2c0262af | bellard | void *puc);
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219 | 2c0262af | bellard | |
220 | 9ee6e8bb | pbrook | void cpu_lock(void); |
221 | 9ee6e8bb | pbrook | void cpu_unlock(void); |
222 | 9ee6e8bb | pbrook | |
223 | b5ff1b31 | bellard | #define CPSR_M (0x1f) |
224 | b5ff1b31 | bellard | #define CPSR_T (1 << 5) |
225 | b5ff1b31 | bellard | #define CPSR_F (1 << 6) |
226 | b5ff1b31 | bellard | #define CPSR_I (1 << 7) |
227 | b5ff1b31 | bellard | #define CPSR_A (1 << 8) |
228 | b5ff1b31 | bellard | #define CPSR_E (1 << 9) |
229 | b5ff1b31 | bellard | #define CPSR_IT_2_7 (0xfc00) |
230 | 9ee6e8bb | pbrook | #define CPSR_GE (0xf << 16) |
231 | 9ee6e8bb | pbrook | #define CPSR_RESERVED (0xf << 20) |
232 | b5ff1b31 | bellard | #define CPSR_J (1 << 24) |
233 | b5ff1b31 | bellard | #define CPSR_IT_0_1 (3 << 25) |
234 | b5ff1b31 | bellard | #define CPSR_Q (1 << 27) |
235 | 9ee6e8bb | pbrook | #define CPSR_V (1 << 28) |
236 | 9ee6e8bb | pbrook | #define CPSR_C (1 << 29) |
237 | 9ee6e8bb | pbrook | #define CPSR_Z (1 << 30) |
238 | 9ee6e8bb | pbrook | #define CPSR_N (1 << 31) |
239 | 9ee6e8bb | pbrook | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
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240 | 9ee6e8bb | pbrook | |
241 | 9ee6e8bb | pbrook | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
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242 | 9ee6e8bb | pbrook | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
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243 | 9ee6e8bb | pbrook | /* Bits writable in user mode. */
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244 | 9ee6e8bb | pbrook | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
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245 | 9ee6e8bb | pbrook | /* Execution state bits. MRS read as zero, MSR writes ignored. */
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246 | 9ee6e8bb | pbrook | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
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247 | b5ff1b31 | bellard | |
248 | b5ff1b31 | bellard | /* Return the current CPSR value. */
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249 | 2f4a40e5 | balrog | uint32_t cpsr_read(CPUARMState *env); |
250 | 2f4a40e5 | balrog | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
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251 | 2f4a40e5 | balrog | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
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252 | 9ee6e8bb | pbrook | |
253 | 9ee6e8bb | pbrook | /* Return the current xPSR value. */
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254 | 9ee6e8bb | pbrook | static inline uint32_t xpsr_read(CPUARMState *env) |
255 | 9ee6e8bb | pbrook | { |
256 | 9ee6e8bb | pbrook | int ZF;
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257 | 9ee6e8bb | pbrook | ZF = (env->NZF == 0);
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258 | 9ee6e8bb | pbrook | return (env->NZF & 0x80000000) | (ZF << 30) |
259 | 9ee6e8bb | pbrook | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
260 | 9ee6e8bb | pbrook | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) |
261 | 9ee6e8bb | pbrook | | ((env->condexec_bits & 0xfc) << 8) |
262 | 9ee6e8bb | pbrook | | env->v7m.exception; |
263 | b5ff1b31 | bellard | } |
264 | b5ff1b31 | bellard | |
265 | 9ee6e8bb | pbrook | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
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266 | 9ee6e8bb | pbrook | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
267 | 9ee6e8bb | pbrook | { |
268 | 9ee6e8bb | pbrook | /* NOTE: N = 1 and Z = 1 cannot be stored currently */
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269 | 9ee6e8bb | pbrook | if (mask & CPSR_NZCV) {
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270 | 9ee6e8bb | pbrook | env->NZF = (val & 0xc0000000) ^ 0x40000000; |
271 | 9ee6e8bb | pbrook | env->CF = (val >> 29) & 1; |
272 | 9ee6e8bb | pbrook | env->VF = (val << 3) & 0x80000000; |
273 | 9ee6e8bb | pbrook | } |
274 | 9ee6e8bb | pbrook | if (mask & CPSR_Q)
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275 | 9ee6e8bb | pbrook | env->QF = ((val & CPSR_Q) != 0);
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276 | 9ee6e8bb | pbrook | if (mask & (1 << 24)) |
277 | 9ee6e8bb | pbrook | env->thumb = ((val & (1 << 24)) != 0); |
278 | 9ee6e8bb | pbrook | if (mask & CPSR_IT_0_1) {
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279 | 9ee6e8bb | pbrook | env->condexec_bits &= ~3;
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280 | 9ee6e8bb | pbrook | env->condexec_bits |= (val >> 25) & 3; |
281 | 9ee6e8bb | pbrook | } |
282 | 9ee6e8bb | pbrook | if (mask & CPSR_IT_2_7) {
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283 | 9ee6e8bb | pbrook | env->condexec_bits &= 3;
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284 | 9ee6e8bb | pbrook | env->condexec_bits |= (val >> 8) & 0xfc; |
285 | 9ee6e8bb | pbrook | } |
286 | 9ee6e8bb | pbrook | if (mask & 0x1ff) { |
287 | 9ee6e8bb | pbrook | env->v7m.exception = val & 0x1ff;
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288 | 9ee6e8bb | pbrook | } |
289 | 9ee6e8bb | pbrook | } |
290 | 9ee6e8bb | pbrook | |
291 | b5ff1b31 | bellard | enum arm_cpu_mode {
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292 | b5ff1b31 | bellard | ARM_CPU_MODE_USR = 0x10,
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293 | b5ff1b31 | bellard | ARM_CPU_MODE_FIQ = 0x11,
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294 | b5ff1b31 | bellard | ARM_CPU_MODE_IRQ = 0x12,
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295 | b5ff1b31 | bellard | ARM_CPU_MODE_SVC = 0x13,
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296 | b5ff1b31 | bellard | ARM_CPU_MODE_ABT = 0x17,
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297 | b5ff1b31 | bellard | ARM_CPU_MODE_UND = 0x1b,
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298 | b5ff1b31 | bellard | ARM_CPU_MODE_SYS = 0x1f
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299 | b5ff1b31 | bellard | }; |
300 | b5ff1b31 | bellard | |
301 | 40f137e1 | pbrook | /* VFP system registers. */
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302 | 40f137e1 | pbrook | #define ARM_VFP_FPSID 0 |
303 | 40f137e1 | pbrook | #define ARM_VFP_FPSCR 1 |
304 | 9ee6e8bb | pbrook | #define ARM_VFP_MVFR1 6 |
305 | 9ee6e8bb | pbrook | #define ARM_VFP_MVFR0 7 |
306 | 40f137e1 | pbrook | #define ARM_VFP_FPEXC 8 |
307 | 40f137e1 | pbrook | #define ARM_VFP_FPINST 9 |
308 | 40f137e1 | pbrook | #define ARM_VFP_FPINST2 10 |
309 | 40f137e1 | pbrook | |
310 | 18c9b560 | balrog | /* iwMMXt coprocessor control registers. */
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311 | 18c9b560 | balrog | #define ARM_IWMMXT_wCID 0 |
312 | 18c9b560 | balrog | #define ARM_IWMMXT_wCon 1 |
313 | 18c9b560 | balrog | #define ARM_IWMMXT_wCSSF 2 |
314 | 18c9b560 | balrog | #define ARM_IWMMXT_wCASF 3 |
315 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR0 8 |
316 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR1 9 |
317 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR2 10 |
318 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR3 11 |
319 | 18c9b560 | balrog | |
320 | 40f137e1 | pbrook | enum arm_features {
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321 | 40f137e1 | pbrook | ARM_FEATURE_VFP, |
322 | c1713132 | balrog | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
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323 | c1713132 | balrog | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
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324 | ce819861 | pbrook | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
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325 | 9ee6e8bb | pbrook | ARM_FEATURE_V6, |
326 | 9ee6e8bb | pbrook | ARM_FEATURE_V6K, |
327 | 9ee6e8bb | pbrook | ARM_FEATURE_V7, |
328 | 9ee6e8bb | pbrook | ARM_FEATURE_THUMB2, |
329 | c3d2689d | balrog | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
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330 | 9ee6e8bb | pbrook | ARM_FEATURE_VFP3, |
331 | 9ee6e8bb | pbrook | ARM_FEATURE_NEON, |
332 | 9ee6e8bb | pbrook | ARM_FEATURE_DIV, |
333 | 9ee6e8bb | pbrook | ARM_FEATURE_M, /* Microcontroller profile. */
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334 | c3d2689d | balrog | ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */
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335 | 40f137e1 | pbrook | }; |
336 | 40f137e1 | pbrook | |
337 | 40f137e1 | pbrook | static inline int arm_feature(CPUARMState *env, int feature) |
338 | 40f137e1 | pbrook | { |
339 | 40f137e1 | pbrook | return (env->features & (1u << feature)) != 0; |
340 | 40f137e1 | pbrook | } |
341 | 40f137e1 | pbrook | |
342 | c732abe2 | j_mayer | void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
343 | 40f137e1 | pbrook | |
344 | 9ee6e8bb | pbrook | /* Interface between CPU and Interrupt controller. */
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345 | 9ee6e8bb | pbrook | void armv7m_nvic_set_pending(void *opaque, int irq); |
346 | 9ee6e8bb | pbrook | int armv7m_nvic_acknowledge_irq(void *opaque); |
347 | 9ee6e8bb | pbrook | void armv7m_nvic_complete_irq(void *opaque, int irq); |
348 | 9ee6e8bb | pbrook | |
349 | c1713132 | balrog | void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
350 | c1713132 | balrog | ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
351 | c1713132 | balrog | void *opaque);
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352 | c1713132 | balrog | |
353 | 9ee6e8bb | pbrook | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
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354 | 9ee6e8bb | pbrook | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
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355 | 9ee6e8bb | pbrook | conventional cores (ie. Application or Realtime profile). */
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356 | 9ee6e8bb | pbrook | |
357 | 9ee6e8bb | pbrook | #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
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358 | 9ee6e8bb | pbrook | #define ARM_CPUID(env) (env->cp15.c0_cpuid)
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359 | 9ee6e8bb | pbrook | |
360 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM1026 0x4106a262 |
361 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM926 0x41069265 |
362 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM946 0x41059461 |
363 | 9ee6e8bb | pbrook | #define ARM_CPUID_TI915T 0x54029152 |
364 | 9ee6e8bb | pbrook | #define ARM_CPUID_TI925T 0x54029252 |
365 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA250 0x69052100 |
366 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA255 0x69052d00 |
367 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA260 0x69052903 |
368 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA261 0x69052d05 |
369 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA262 0x69052d06 |
370 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270 0x69054110 |
371 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_A0 0x69054110 |
372 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_A1 0x69054111 |
373 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_B0 0x69054112 |
374 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_B1 0x69054113 |
375 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_C0 0x69054114 |
376 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_C5 0x69054117 |
377 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM1136 0x4117b363 |
378 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM11MPCORE 0x410fb022 |
379 | 9ee6e8bb | pbrook | #define ARM_CPUID_CORTEXA8 0x410fc080 |
380 | 9ee6e8bb | pbrook | #define ARM_CPUID_CORTEXM3 0x410fc231 |
381 | 9ee6e8bb | pbrook | #define ARM_CPUID_ANY 0xffffffff |
382 | 40f137e1 | pbrook | |
383 | b5ff1b31 | bellard | #if defined(CONFIG_USER_ONLY)
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384 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
385 | b5ff1b31 | bellard | #else
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386 | b5ff1b31 | bellard | /* The ARM MMU allows 1k pages. */
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387 | b5ff1b31 | bellard | /* ??? Linux doesn't actually use these, and they're deprecated in recent
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388 | 82d17978 | balrog | architecture revisions. Maybe a configure option to disable them. */
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389 | b5ff1b31 | bellard | #define TARGET_PAGE_BITS 10 |
390 | b5ff1b31 | bellard | #endif
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391 | 9467d44c | ths | |
392 | 9467d44c | ths | #define CPUState CPUARMState
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393 | 9467d44c | ths | #define cpu_init cpu_arm_init
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394 | 9467d44c | ths | #define cpu_exec cpu_arm_exec
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395 | 9467d44c | ths | #define cpu_gen_code cpu_arm_gen_code
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396 | 9467d44c | ths | #define cpu_signal_handler cpu_arm_signal_handler
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397 | c732abe2 | j_mayer | #define cpu_list arm_cpu_list
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398 | 9467d44c | ths | |
399 | 9ee6e8bb | pbrook | #define ARM_CPU_SAVE_VERSION 1 |
400 | 9ee6e8bb | pbrook | |
401 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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402 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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403 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
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404 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
405 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
406 | 6ebbf390 | j_mayer | { |
407 | 6ebbf390 | j_mayer | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; |
408 | 6ebbf390 | j_mayer | } |
409 | 6ebbf390 | j_mayer | |
410 | 2c0262af | bellard | #include "cpu-all.h" |
411 | 2c0262af | bellard | |
412 | 2c0262af | bellard | #endif |