root / hw / firmware_abi.h @ 5e65a310
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1 | d2c63fc1 | blueswir1 | #ifndef FIRMWARE_ABI_H
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2 | d2c63fc1 | blueswir1 | #define FIRMWARE_ABI_H
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3 | d2c63fc1 | blueswir1 | |
4 | d2c63fc1 | blueswir1 | #ifndef __ASSEMBLY__
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5 | d2c63fc1 | blueswir1 | /* Open Hack'Ware NVRAM configuration structure */
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6 | d2c63fc1 | blueswir1 | |
7 | d2c63fc1 | blueswir1 | /* Version 3 */
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8 | d2c63fc1 | blueswir1 | typedef struct ohwcfg_v3_t ohwcfg_v3_t; |
9 | d2c63fc1 | blueswir1 | struct ohwcfg_v3_t {
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10 | d2c63fc1 | blueswir1 | /* 0x00: structure identifier */
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11 | d2c63fc1 | blueswir1 | uint8_t struct_ident[0x10];
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12 | d2c63fc1 | blueswir1 | /* 0x10: structure version and NVRAM description */
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13 | d2c63fc1 | blueswir1 | uint32_t struct_version; |
14 | d2c63fc1 | blueswir1 | uint16_t nvram_size; |
15 | d2c63fc1 | blueswir1 | uint16_t pad0; |
16 | d2c63fc1 | blueswir1 | uint16_t nvram_arch_ptr; |
17 | d2c63fc1 | blueswir1 | uint16_t nvram_arch_size; |
18 | d2c63fc1 | blueswir1 | uint16_t nvram_arch_crc; |
19 | d2c63fc1 | blueswir1 | uint8_t pad1[0x02];
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20 | d2c63fc1 | blueswir1 | /* 0x20: host architecture */
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21 | d2c63fc1 | blueswir1 | uint8_t arch[0x10];
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22 | d2c63fc1 | blueswir1 | /* 0x30: RAM/ROM description */
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23 | d2c63fc1 | blueswir1 | uint64_t RAM0_base; |
24 | d2c63fc1 | blueswir1 | uint64_t RAM0_size; |
25 | d2c63fc1 | blueswir1 | uint64_t RAM1_base; |
26 | d2c63fc1 | blueswir1 | uint64_t RAM1_size; |
27 | d2c63fc1 | blueswir1 | uint64_t RAM2_base; |
28 | d2c63fc1 | blueswir1 | uint64_t RAM2_size; |
29 | d2c63fc1 | blueswir1 | uint64_t RAM3_base; |
30 | d2c63fc1 | blueswir1 | uint64_t RAM3_size; |
31 | d2c63fc1 | blueswir1 | uint64_t ROM_base; |
32 | d2c63fc1 | blueswir1 | uint64_t ROM_size; |
33 | d2c63fc1 | blueswir1 | /* 0x80: Kernel description */
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34 | d2c63fc1 | blueswir1 | uint64_t kernel_image; |
35 | d2c63fc1 | blueswir1 | uint64_t kernel_size; |
36 | d2c63fc1 | blueswir1 | /* 0x90: Kernel command line */
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37 | d2c63fc1 | blueswir1 | uint64_t cmdline; |
38 | d2c63fc1 | blueswir1 | uint64_t cmdline_size; |
39 | d2c63fc1 | blueswir1 | /* 0xA0: Kernel boot image */
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40 | d2c63fc1 | blueswir1 | uint64_t initrd_image; |
41 | d2c63fc1 | blueswir1 | uint64_t initrd_size; |
42 | d2c63fc1 | blueswir1 | /* 0xB0: NVRAM image */
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43 | d2c63fc1 | blueswir1 | uint64_t NVRAM_image; |
44 | d2c63fc1 | blueswir1 | uint8_t pad2[8];
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45 | d2c63fc1 | blueswir1 | /* 0xC0: graphic configuration */
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46 | d2c63fc1 | blueswir1 | uint16_t width; |
47 | d2c63fc1 | blueswir1 | uint16_t height; |
48 | d2c63fc1 | blueswir1 | uint16_t depth; |
49 | d2c63fc1 | blueswir1 | uint16_t graphic_flags; |
50 | d2c63fc1 | blueswir1 | /* 0xC8: CPUs description */
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51 | d2c63fc1 | blueswir1 | uint8_t nb_cpus; |
52 | d2c63fc1 | blueswir1 | uint8_t boot_cpu; |
53 | d2c63fc1 | blueswir1 | uint8_t nboot_devices; |
54 | d2c63fc1 | blueswir1 | uint8_t pad3[5];
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55 | d2c63fc1 | blueswir1 | /* 0xD0: boot devices */
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56 | d2c63fc1 | blueswir1 | uint8_t boot_devices[0x10];
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57 | d2c63fc1 | blueswir1 | /* 0xE0 */
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58 | d2c63fc1 | blueswir1 | uint8_t pad4[0x1C]; /* 28 */ |
59 | d2c63fc1 | blueswir1 | /* 0xFC: checksum */
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60 | d2c63fc1 | blueswir1 | uint16_t crc; |
61 | d2c63fc1 | blueswir1 | uint8_t pad5[0x02];
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62 | d2c63fc1 | blueswir1 | } __attribute__ (( packed )); |
63 | d2c63fc1 | blueswir1 | |
64 | d2c63fc1 | blueswir1 | #define OHW_GF_NOGRAPHICS 0x0001 |
65 | d2c63fc1 | blueswir1 | |
66 | d2c63fc1 | blueswir1 | static inline uint16_t |
67 | d2c63fc1 | blueswir1 | OHW_crc_update (uint16_t prev, uint16_t value) |
68 | d2c63fc1 | blueswir1 | { |
69 | d2c63fc1 | blueswir1 | uint16_t tmp; |
70 | d2c63fc1 | blueswir1 | uint16_t pd, pd1, pd2; |
71 | d2c63fc1 | blueswir1 | |
72 | d2c63fc1 | blueswir1 | tmp = prev >> 8;
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73 | d2c63fc1 | blueswir1 | pd = prev ^ value; |
74 | d2c63fc1 | blueswir1 | pd1 = pd & 0x000F;
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75 | d2c63fc1 | blueswir1 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
76 | d2c63fc1 | blueswir1 | tmp ^= (pd1 << 3) | (pd1 << 8); |
77 | d2c63fc1 | blueswir1 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
78 | d2c63fc1 | blueswir1 | |
79 | d2c63fc1 | blueswir1 | return tmp;
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80 | d2c63fc1 | blueswir1 | } |
81 | d2c63fc1 | blueswir1 | |
82 | d2c63fc1 | blueswir1 | static inline uint16_t |
83 | d2c63fc1 | blueswir1 | OHW_compute_crc (ohwcfg_v3_t *header, uint32_t start, uint32_t count) |
84 | d2c63fc1 | blueswir1 | { |
85 | d2c63fc1 | blueswir1 | uint32_t i; |
86 | d2c63fc1 | blueswir1 | uint16_t crc = 0xFFFF;
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87 | d2c63fc1 | blueswir1 | uint8_t *ptr = (uint8_t *)header; |
88 | d2c63fc1 | blueswir1 | int odd;
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89 | d2c63fc1 | blueswir1 | |
90 | d2c63fc1 | blueswir1 | odd = count & 1;
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91 | d2c63fc1 | blueswir1 | count &= ~1;
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92 | d2c63fc1 | blueswir1 | for (i = 0; i != count; i++) { |
93 | d2c63fc1 | blueswir1 | crc = OHW_crc_update(crc, (ptr[start + i] << 8) | ptr[start + i + 1]); |
94 | d2c63fc1 | blueswir1 | } |
95 | d2c63fc1 | blueswir1 | if (odd) {
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96 | d2c63fc1 | blueswir1 | crc = OHW_crc_update(crc, ptr[start + i] << 8);
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97 | d2c63fc1 | blueswir1 | } |
98 | d2c63fc1 | blueswir1 | |
99 | d2c63fc1 | blueswir1 | return crc;
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100 | d2c63fc1 | blueswir1 | } |
101 | d2c63fc1 | blueswir1 | |
102 | d2c63fc1 | blueswir1 | /* Sparc32 runtime NVRAM structure for SMP CPU boot */
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103 | d2c63fc1 | blueswir1 | struct sparc_arch_cfg {
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104 | d2c63fc1 | blueswir1 | uint32_t smp_ctx; |
105 | d2c63fc1 | blueswir1 | uint32_t smp_ctxtbl; |
106 | d2c63fc1 | blueswir1 | uint32_t smp_entry; |
107 | d2c63fc1 | blueswir1 | uint8_t valid; |
108 | d2c63fc1 | blueswir1 | uint8_t unused[51];
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109 | d2c63fc1 | blueswir1 | }; |
110 | d2c63fc1 | blueswir1 | |
111 | d2c63fc1 | blueswir1 | /* OpenBIOS NVRAM partition */
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112 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 {
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113 | d2c63fc1 | blueswir1 | uint8_t signature; |
114 | d2c63fc1 | blueswir1 | uint8_t checksum; |
115 | d2c63fc1 | blueswir1 | uint16_t len; // BE, length divided by 16
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116 | d2c63fc1 | blueswir1 | char name[12]; |
117 | d2c63fc1 | blueswir1 | }; |
118 | d2c63fc1 | blueswir1 | |
119 | d2c63fc1 | blueswir1 | #define OPENBIOS_PART_SYSTEM 0x70 |
120 | d2c63fc1 | blueswir1 | #define OPENBIOS_PART_FREE 0x7f |
121 | d2c63fc1 | blueswir1 | |
122 | d2c63fc1 | blueswir1 | static inline void |
123 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(struct OpenBIOS_nvpart_v1 *header, uint32_t size)
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124 | d2c63fc1 | blueswir1 | { |
125 | d2c63fc1 | blueswir1 | unsigned int i, sum; |
126 | d2c63fc1 | blueswir1 | uint8_t *tmpptr; |
127 | d2c63fc1 | blueswir1 | |
128 | d2c63fc1 | blueswir1 | // Length divided by 16
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129 | d2c63fc1 | blueswir1 | header->len = cpu_to_be16(size >> 4);
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130 | d2c63fc1 | blueswir1 | |
131 | d2c63fc1 | blueswir1 | // Checksum
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132 | d2c63fc1 | blueswir1 | tmpptr = (uint8_t *)header; |
133 | d2c63fc1 | blueswir1 | sum = *tmpptr; |
134 | d2c63fc1 | blueswir1 | for (i = 0; i < 14; i++) { |
135 | d2c63fc1 | blueswir1 | sum += tmpptr[2 + i];
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136 | d2c63fc1 | blueswir1 | sum = (sum + ((sum & 0xff00) >> 8)) & 0xff; |
137 | d2c63fc1 | blueswir1 | } |
138 | d2c63fc1 | blueswir1 | header->checksum = sum & 0xff;
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139 | d2c63fc1 | blueswir1 | } |
140 | d2c63fc1 | blueswir1 | |
141 | d2c63fc1 | blueswir1 | static inline uint32_t |
142 | e7fb1406 | blueswir1 | OpenBIOS_set_var(uint8_t *nvram, uint32_t addr, const char *str) |
143 | d2c63fc1 | blueswir1 | { |
144 | d2c63fc1 | blueswir1 | uint32_t len; |
145 | d2c63fc1 | blueswir1 | |
146 | d2c63fc1 | blueswir1 | len = strlen(str) + 1;
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147 | d2c63fc1 | blueswir1 | memcpy(&nvram[addr], str, len); |
148 | d2c63fc1 | blueswir1 | |
149 | d2c63fc1 | blueswir1 | return addr + len;
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150 | d2c63fc1 | blueswir1 | } |
151 | d2c63fc1 | blueswir1 | |
152 | d2c63fc1 | blueswir1 | /* Sun IDPROM structure at the end of NVRAM */
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153 | d2c63fc1 | blueswir1 | struct Sun_nvram {
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154 | d2c63fc1 | blueswir1 | uint8_t type; |
155 | d2c63fc1 | blueswir1 | uint8_t machine_id; |
156 | d2c63fc1 | blueswir1 | uint8_t macaddr[6];
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157 | d2c63fc1 | blueswir1 | uint8_t unused[7];
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158 | d2c63fc1 | blueswir1 | uint8_t checksum; |
159 | d2c63fc1 | blueswir1 | }; |
160 | d2c63fc1 | blueswir1 | |
161 | d2c63fc1 | blueswir1 | static inline void |
162 | d2c63fc1 | blueswir1 | Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id) |
163 | d2c63fc1 | blueswir1 | { |
164 | d2c63fc1 | blueswir1 | uint8_t tmp, *tmpptr; |
165 | d2c63fc1 | blueswir1 | unsigned int i; |
166 | d2c63fc1 | blueswir1 | |
167 | d2c63fc1 | blueswir1 | header->type = 1;
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168 | d2c63fc1 | blueswir1 | header->machine_id = machine_id & 0xff;
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169 | d2c63fc1 | blueswir1 | memcpy(&header->macaddr, macaddr, 6);
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170 | d2c63fc1 | blueswir1 | /* Calculate checksum */
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171 | d2c63fc1 | blueswir1 | tmp = 0;
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172 | d2c63fc1 | blueswir1 | tmpptr = (uint8_t *)header; |
173 | d2c63fc1 | blueswir1 | for (i = 0; i < 15; i++) |
174 | d2c63fc1 | blueswir1 | tmp ^= tmpptr[i]; |
175 | d2c63fc1 | blueswir1 | |
176 | d2c63fc1 | blueswir1 | header->checksum = tmp; |
177 | d2c63fc1 | blueswir1 | } |
178 | d2c63fc1 | blueswir1 | |
179 | d2c63fc1 | blueswir1 | #else /* __ASSEMBLY__ */ |
180 | d2c63fc1 | blueswir1 | |
181 | d2c63fc1 | blueswir1 | /* Structure offsets for asm use */
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182 | d2c63fc1 | blueswir1 | |
183 | d2c63fc1 | blueswir1 | /* Open Hack'Ware NVRAM configuration structure */
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184 | d2c63fc1 | blueswir1 | #define OHW_ARCH_PTR 0x18 |
185 | d2c63fc1 | blueswir1 | #define OHW_RAM_SIZE 0x38 |
186 | d2c63fc1 | blueswir1 | #define OHW_BOOT_CPU 0xC9 |
187 | d2c63fc1 | blueswir1 | |
188 | d2c63fc1 | blueswir1 | /* Sparc32 runtime NVRAM structure for SMP CPU boot */
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189 | d2c63fc1 | blueswir1 | #define SPARC_SMP_CTX 0x0 |
190 | d2c63fc1 | blueswir1 | #define SPARC_SMP_CTXTBL 0x4 |
191 | d2c63fc1 | blueswir1 | #define SPARC_SMP_ENTRY 0x8 |
192 | d2c63fc1 | blueswir1 | #define SPARC_SMP_VALID 0xc |
193 | d2c63fc1 | blueswir1 | |
194 | d2c63fc1 | blueswir1 | /* Sun IDPROM structure at the end of NVRAM */
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195 | d2c63fc1 | blueswir1 | #define SPARC_MACHINE_ID 0x1fd9 |
196 | d2c63fc1 | blueswir1 | |
197 | d2c63fc1 | blueswir1 | #endif /* __ASSEMBLY__ */ |
198 | d2c63fc1 | blueswir1 | #endif /* FIRMWARE_ABI_H */ |