root / hw / mips_r4k.c @ 5e65a310
History | View | Annotate | Download (8.6 kB)
1 | e16fe40c | ths | /*
|
---|---|---|---|
2 | e16fe40c | ths | * QEMU/MIPS pseudo-board
|
3 | e16fe40c | ths | *
|
4 | e16fe40c | ths | * emulates a simple machine with ISA-like bus.
|
5 | e16fe40c | ths | * ISA IO space mapped to the 0x14000000 (PHYS) and
|
6 | e16fe40c | ths | * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
|
7 | e16fe40c | ths | * All peripherial devices are attached to this "bus" with
|
8 | e16fe40c | ths | * the standard PC ISA addresses.
|
9 | e16fe40c | ths | */
|
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "mips.h" |
12 | 87ecb68b | pbrook | #include "pc.h" |
13 | 87ecb68b | pbrook | #include "isa.h" |
14 | 87ecb68b | pbrook | #include "net.h" |
15 | 87ecb68b | pbrook | #include "sysemu.h" |
16 | 87ecb68b | pbrook | #include "boards.h" |
17 | b305b5ba | ths | #include "flash.h" |
18 | 6af0bf9c | bellard | |
19 | 2909b29a | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
20 | 6af0bf9c | bellard | #define BIOS_FILENAME "mips_bios.bin" |
21 | f7bcd4e3 | ths | #else
|
22 | f7bcd4e3 | ths | #define BIOS_FILENAME "mipsel_bios.bin" |
23 | f7bcd4e3 | ths | #endif
|
24 | 44cbbf18 | ths | |
25 | c6ee607c | pbrook | #define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff) |
26 | 6af0bf9c | bellard | |
27 | 5dc4b744 | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
28 | 66a93e0f | bellard | |
29 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
30 | e4bcb14c | ths | |
31 | 58126404 | pbrook | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
32 | 58126404 | pbrook | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
33 | 58126404 | pbrook | static const int ide_irq[2] = { 14, 15 }; |
34 | 58126404 | pbrook | |
35 | eddbd288 | ths | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
36 | eddbd288 | ths | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
37 | eddbd288 | ths | |
38 | 6af0bf9c | bellard | extern FILE *logfile;
|
39 | 6af0bf9c | bellard | |
40 | e16fe40c | ths | static PITState *pit; /* PIT i8254 */ |
41 | 697584ab | bellard | |
42 | 1b66074b | ths | /* i8254 PIT is attached to the IRQ0 at PIC i8259 */
|
43 | 6af0bf9c | bellard | |
44 | 7df526e3 | ths | static struct _loaderparams { |
45 | 7df526e3 | ths | int ram_size;
|
46 | 7df526e3 | ths | const char *kernel_filename; |
47 | 7df526e3 | ths | const char *kernel_cmdline; |
48 | 7df526e3 | ths | const char *initrd_filename; |
49 | 7df526e3 | ths | } loaderparams; |
50 | 7df526e3 | ths | |
51 | 6ae81775 | ths | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
52 | 6ae81775 | ths | uint32_t val) |
53 | 6ae81775 | ths | { |
54 | 6ae81775 | ths | if ((addr & 0xffff) == 0 && val == 42) |
55 | 6ae81775 | ths | qemu_system_reset_request (); |
56 | 6ae81775 | ths | else if ((addr & 0xffff) == 4 && val == 42) |
57 | 6ae81775 | ths | qemu_system_shutdown_request (); |
58 | 6ae81775 | ths | } |
59 | 6ae81775 | ths | |
60 | 6ae81775 | ths | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) |
61 | 6ae81775 | ths | { |
62 | 6ae81775 | ths | return 0; |
63 | 6ae81775 | ths | } |
64 | 6ae81775 | ths | |
65 | 6ae81775 | ths | static CPUWriteMemoryFunc *mips_qemu_write[] = {
|
66 | 6ae81775 | ths | &mips_qemu_writel, |
67 | 6ae81775 | ths | &mips_qemu_writel, |
68 | 6ae81775 | ths | &mips_qemu_writel, |
69 | 6ae81775 | ths | }; |
70 | 6ae81775 | ths | |
71 | 6ae81775 | ths | static CPUReadMemoryFunc *mips_qemu_read[] = {
|
72 | 6ae81775 | ths | &mips_qemu_readl, |
73 | 6ae81775 | ths | &mips_qemu_readl, |
74 | 6ae81775 | ths | &mips_qemu_readl, |
75 | 6ae81775 | ths | }; |
76 | 6ae81775 | ths | |
77 | 6ae81775 | ths | static int mips_qemu_iomemtype = 0; |
78 | 6ae81775 | ths | |
79 | 7df526e3 | ths | static void load_kernel (CPUState *env) |
80 | 6ae81775 | ths | { |
81 | 74287114 | ths | int64_t entry, kernel_low, kernel_high; |
82 | 6ae81775 | ths | long kernel_size, initrd_size;
|
83 | 74287114 | ths | ram_addr_t initrd_offset; |
84 | 6ae81775 | ths | |
85 | 7df526e3 | ths | kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
86 | 74287114 | ths | &entry, &kernel_low, &kernel_high); |
87 | c570fd16 | ths | if (kernel_size >= 0) { |
88 | c570fd16 | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
89 | 5dc4b744 | ths | entry = (int32_t)entry; |
90 | b5dc7732 | ths | env->active_tc.PC = entry; |
91 | c570fd16 | ths | } else {
|
92 | 9042c0e2 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
93 | 7df526e3 | ths | loaderparams.kernel_filename); |
94 | 9042c0e2 | ths | exit(1);
|
95 | 6ae81775 | ths | } |
96 | 6ae81775 | ths | |
97 | 6ae81775 | ths | /* load initrd */
|
98 | 6ae81775 | ths | initrd_size = 0;
|
99 | 74287114 | ths | initrd_offset = 0;
|
100 | 7df526e3 | ths | if (loaderparams.initrd_filename) {
|
101 | 7df526e3 | ths | initrd_size = get_image_size (loaderparams.initrd_filename); |
102 | 74287114 | ths | if (initrd_size > 0) { |
103 | 74287114 | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
104 | 74287114 | ths | if (initrd_offset + initrd_size > ram_size) {
|
105 | 74287114 | ths | fprintf(stderr, |
106 | 74287114 | ths | "qemu: memory too small for initial ram disk '%s'\n",
|
107 | 7df526e3 | ths | loaderparams.initrd_filename); |
108 | 74287114 | ths | exit(1);
|
109 | 74287114 | ths | } |
110 | 7df526e3 | ths | initrd_size = load_image(loaderparams.initrd_filename, |
111 | 74287114 | ths | phys_ram_base + initrd_offset); |
112 | 74287114 | ths | } |
113 | 6ae81775 | ths | if (initrd_size == (target_ulong) -1) { |
114 | 6ae81775 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
115 | 7df526e3 | ths | loaderparams.initrd_filename); |
116 | 6ae81775 | ths | exit(1);
|
117 | 6ae81775 | ths | } |
118 | 6ae81775 | ths | } |
119 | 6ae81775 | ths | |
120 | 6ae81775 | ths | /* Store command line. */
|
121 | 6ae81775 | ths | if (initrd_size > 0) { |
122 | 6ae81775 | ths | int ret;
|
123 | 6ae81775 | ths | ret = sprintf(phys_ram_base + (16 << 20) - 256, |
124 | 3594c774 | ths | "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", |
125 | 74287114 | ths | PHYS_TO_VIRT((uint32_t)initrd_offset), |
126 | 6ae81775 | ths | initrd_size); |
127 | 7df526e3 | ths | strcpy (phys_ram_base + (16 << 20) - 256 + ret, |
128 | 7df526e3 | ths | loaderparams.kernel_cmdline); |
129 | 6ae81775 | ths | } |
130 | 6ae81775 | ths | else {
|
131 | 7df526e3 | ths | strcpy (phys_ram_base + (16 << 20) - 256, |
132 | 7df526e3 | ths | loaderparams.kernel_cmdline); |
133 | 6ae81775 | ths | } |
134 | 6ae81775 | ths | |
135 | 44cbbf18 | ths | *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
136 | 44cbbf18 | ths | *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); |
137 | 6ae81775 | ths | } |
138 | 6ae81775 | ths | |
139 | 6ae81775 | ths | static void main_cpu_reset(void *opaque) |
140 | 6ae81775 | ths | { |
141 | 6ae81775 | ths | CPUState *env = opaque; |
142 | 6ae81775 | ths | cpu_reset(env); |
143 | 6ae81775 | ths | |
144 | 7df526e3 | ths | if (loaderparams.kernel_filename)
|
145 | 7df526e3 | ths | load_kernel (env); |
146 | 6ae81775 | ths | } |
147 | 66a93e0f | bellard | |
148 | b305b5ba | ths | static const int sector_len = 32 * 1024; |
149 | 70705261 | ths | static
|
150 | 00f82b8a | aurel32 | void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size, |
151 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
152 | 6af0bf9c | bellard | const char *kernel_filename, const char *kernel_cmdline, |
153 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
154 | 6af0bf9c | bellard | { |
155 | 6af0bf9c | bellard | char buf[1024]; |
156 | 6af0bf9c | bellard | unsigned long bios_offset; |
157 | f7bcd4e3 | ths | int bios_size;
|
158 | c68ea704 | bellard | CPUState *env; |
159 | 153a08db | ths | RTCState *rtc_state; |
160 | 58126404 | pbrook | int i;
|
161 | d537cf6c | pbrook | qemu_irq *i8259; |
162 | e4bcb14c | ths | int index;
|
163 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
164 | c68ea704 | bellard | |
165 | 33d68b5f | ths | /* init CPUs */
|
166 | 33d68b5f | ths | if (cpu_model == NULL) { |
167 | 60aa19ab | ths | #ifdef TARGET_MIPS64
|
168 | 33d68b5f | ths | cpu_model = "R4000";
|
169 | 33d68b5f | ths | #else
|
170 | 1c32f43e | ths | cpu_model = "24Kf";
|
171 | 33d68b5f | ths | #endif
|
172 | 33d68b5f | ths | } |
173 | aaed909a | bellard | env = cpu_init(cpu_model); |
174 | aaed909a | bellard | if (!env) {
|
175 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
|
176 | aaed909a | bellard | exit(1);
|
177 | aaed909a | bellard | } |
178 | 6ae81775 | ths | qemu_register_reset(main_cpu_reset, env); |
179 | c68ea704 | bellard | |
180 | 6af0bf9c | bellard | /* allocate RAM */
|
181 | 6af0bf9c | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
182 | 66a93e0f | bellard | |
183 | 6ae81775 | ths | if (!mips_qemu_iomemtype) {
|
184 | 6ae81775 | ths | mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
|
185 | 33d68b5f | ths | mips_qemu_write, NULL);
|
186 | 6ae81775 | ths | } |
187 | 6ae81775 | ths | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); |
188 | 6ae81775 | ths | |
189 | 66a93e0f | bellard | /* Try to load a BIOS image. If this fails, we continue regardless,
|
190 | 66a93e0f | bellard | but initialize the hardware ourselves. When a kernel gets
|
191 | 66a93e0f | bellard | preloaded we also initialize the hardware, since the BIOS wasn't
|
192 | 66a93e0f | bellard | run. */
|
193 | 6af0bf9c | bellard | bios_offset = ram_size + vga_ram_size; |
194 | 1192dad8 | j_mayer | if (bios_name == NULL) |
195 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
196 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
197 | f7bcd4e3 | ths | bios_size = load_image(buf, phys_ram_base + bios_offset); |
198 | 2909b29a | ths | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { |
199 | 44cbbf18 | ths | cpu_register_physical_memory(0x1fc00000,
|
200 | 66a93e0f | bellard | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
201 | b305b5ba | ths | } else if ((index = drive_get_index(IF_PFLASH, 0, 0)) > -1) { |
202 | b305b5ba | ths | uint32_t mips_rom = 0x00400000;
|
203 | b305b5ba | ths | cpu_register_physical_memory(0x1fc00000, mips_rom,
|
204 | b305b5ba | ths | qemu_ram_alloc(mips_rom) | IO_MEM_ROM); |
205 | b305b5ba | ths | if (!pflash_cfi01_register(0x1fc00000, qemu_ram_alloc(mips_rom), |
206 | b305b5ba | ths | drives_table[index].bdrv, sector_len, mips_rom / sector_len, |
207 | b305b5ba | ths | 4, 0, 0, 0, 0)) { |
208 | b305b5ba | ths | fprintf(stderr, "qemu: Error registering flash memory.\n");
|
209 | b305b5ba | ths | } |
210 | b305b5ba | ths | } |
211 | b305b5ba | ths | else {
|
212 | 66a93e0f | bellard | /* not fatal */
|
213 | 66a93e0f | bellard | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
|
214 | 66a93e0f | bellard | buf); |
215 | 6af0bf9c | bellard | } |
216 | 66a93e0f | bellard | |
217 | 66a93e0f | bellard | if (kernel_filename) {
|
218 | 7df526e3 | ths | loaderparams.ram_size = ram_size; |
219 | 7df526e3 | ths | loaderparams.kernel_filename = kernel_filename; |
220 | 7df526e3 | ths | loaderparams.kernel_cmdline = kernel_cmdline; |
221 | 7df526e3 | ths | loaderparams.initrd_filename = initrd_filename; |
222 | 7df526e3 | ths | load_kernel (env); |
223 | 6af0bf9c | bellard | } |
224 | 6af0bf9c | bellard | |
225 | e16fe40c | ths | /* Init CPU internal devices */
|
226 | d537cf6c | pbrook | cpu_mips_irq_init_cpu(env); |
227 | c68ea704 | bellard | cpu_mips_clock_init(env); |
228 | 6af0bf9c | bellard | cpu_mips_irqctrl_init(); |
229 | 6af0bf9c | bellard | |
230 | d537cf6c | pbrook | /* The PIC is attached to the MIPS CPU INT0 pin */
|
231 | d537cf6c | pbrook | i8259 = i8259_init(env->irq[2]);
|
232 | d537cf6c | pbrook | |
233 | d537cf6c | pbrook | rtc_state = rtc_init(0x70, i8259[8]); |
234 | afdfa781 | ths | |
235 | 0699b548 | bellard | /* Register 64 KB of ISA IO space at 0x14000000 */
|
236 | aef445bd | pbrook | isa_mmio_init(0x14000000, 0x00010000); |
237 | 0699b548 | bellard | isa_mem_base = 0x10000000;
|
238 | 0699b548 | bellard | |
239 | d537cf6c | pbrook | pit = pit_init(0x40, i8259[0]); |
240 | afdfa781 | ths | |
241 | eddbd288 | ths | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
242 | eddbd288 | ths | if (serial_hds[i]) {
|
243 | b6cd0ea1 | aurel32 | serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
|
244 | b6cd0ea1 | aurel32 | serial_hds[i]); |
245 | eddbd288 | ths | } |
246 | eddbd288 | ths | } |
247 | eddbd288 | ths | |
248 | 5fafdf24 | ths | isa_vga_init(ds, phys_ram_base + ram_size, ram_size, |
249 | 89b6b508 | bellard | vga_ram_size); |
250 | 9827e95c | bellard | |
251 | a41b2ff2 | pbrook | if (nd_table[0].vlan) { |
252 | a41b2ff2 | pbrook | if (nd_table[0].model == NULL |
253 | a41b2ff2 | pbrook | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
254 | d537cf6c | pbrook | isa_ne2000_init(0x300, i8259[9], &nd_table[0]); |
255 | c4a7060c | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
256 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
|
257 | c4a7060c | blueswir1 | exit (1);
|
258 | a41b2ff2 | pbrook | } else {
|
259 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
260 | a41b2ff2 | pbrook | exit (1);
|
261 | a41b2ff2 | pbrook | } |
262 | a41b2ff2 | pbrook | } |
263 | 58126404 | pbrook | |
264 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
265 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
266 | e4bcb14c | ths | exit(1);
|
267 | e4bcb14c | ths | } |
268 | e4bcb14c | ths | |
269 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
270 | e4bcb14c | ths | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
271 | e4bcb14c | ths | if (index != -1) |
272 | e4bcb14c | ths | hd[i] = drives_table[index].bdrv; |
273 | e4bcb14c | ths | else
|
274 | e4bcb14c | ths | hd[i] = NULL;
|
275 | e4bcb14c | ths | } |
276 | e4bcb14c | ths | |
277 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS; i++) |
278 | d537cf6c | pbrook | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
279 | e4bcb14c | ths | hd[MAX_IDE_DEVS * i], |
280 | e4bcb14c | ths | hd[MAX_IDE_DEVS * i + 1]);
|
281 | 70705261 | ths | |
282 | d537cf6c | pbrook | i8042_init(i8259[1], i8259[12], 0x60); |
283 | 6af0bf9c | bellard | } |
284 | 6af0bf9c | bellard | |
285 | 6af0bf9c | bellard | QEMUMachine mips_machine = { |
286 | 6af0bf9c | bellard | "mips",
|
287 | 6af0bf9c | bellard | "mips r4k platform",
|
288 | 6af0bf9c | bellard | mips_r4k_init, |
289 | 7fb4fdcf | balrog | VGA_RAM_SIZE + BIOS_SIZE, |
290 | 6af0bf9c | bellard | }; |