acpi/piix4pm: convert ACPI PCI hotplug to use hotplug-handler API
Split piix4_device_hotplug() into hotplug/unplug callbacksand register them as "hotplug-handler" interface implementation ofPIIX4_PM device.
Replace pci_bus_hotplug() wiring with setting link on...
pci/shpc: convert SHPC hotplug to use hotplug-handler API
Split shpc_device_hotplug() into hotplug/unplug callbacksand register them as "hotplug-handler" interface implementation ofPCI_BRIDGE_DEV device.
Replace pci_bus_hotplug() wiring with setting link on PCI BUS...
pci/pcie: convert PCIE hotplug to use hotplug-handler API
Split pcie_cap_slot_hotplug() into hotplug/unplug callbacksand register them as "hotplug-handler" interface implementation ofPCIE_SLOT device.
hw/pci: switch to a generic hotplug handling for PCIDevice
make qdev_unplug()/device_set_realized() to call hotplug handler'splug/unplug methods if available and remove not needed anymorehot(un)plug handling from PCIDevice.
In case if hotplug handler is not available, revert to the legacy...
qdev:pci: refactor PCIDevice to use generic "hotpluggable" property
Get rid of PCIDevice specific PCIDeviceClass.no_hotplug and usegeneric DeviceClass.hotpluggable field instead.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Michael S. Tsirkin <mst@redhat.com>...
hw/acpi: move typeinfo to the file end
do so to avoid not necessary forward declarations andplace typeinfo registration at the file end where it'susually expected.
loader: document that errno is set
Document that get_image_size sets errnoon failure.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Eric Blake <eblake@redhat.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
define hotplug interface
Provide a generic hotplug interface for hotplug handlers.Intended for replacing hotplug mechanism used byPCI/PCIE/SHPC code and will be used for memory hotplug.
qdev: add to BusState "hotplug-handler" link
It will allow to reuse field with different BUSes,reducing code duplication. Field is intended forreplacing 'hotplug_qdev' field in PCIBus and alsowill allow to avoid adding equivalent field toDimmBus with possiblitity to refactor other BUSes...
qdev: add "hotpluggable" property to Device
Currently it's possible to make PCIDevice not hotpluggableby using no_hotplug field of PCIDeviceClass. However itlimits this only to PCI devices and prevents fromgeneralizing hotplug code.
So add similar field to DeviceClass so it could be reused...
pcihp: remove unused AcpiPciHpPciStatus.device_present field
Remove now unused 'device_present' field wich was obsoleted bypatch "pcihp: reduce number of device check events"
hw:piix4:acpi: reuse pcihp code for legacy PCI hotplug
reduces acpi PCI hotplug code duplication by ~200LOC
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
qtest: don't report signals if qtest driver enabled
qtest driver always uses signals to kill qemuno need to report it, whatever the accelerator state.
Add API to detect qtest driver, and suppress reportingsignals in this case.
Reported-by: Andreas Färber <afaerber@suse.de>...
pc_piix: enable legacy hotplug for Xen
xenfv has no fwcfg and so does not load acpi from QEMU.as such new acpi features don't work.
Reported-by: Sander Eikelenboom <linux@eikelenboom.it>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
pc.c: better error message on initrd sizing failure
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
pcihp: reduce number of device check events
PIIX created a made-up value for the UP register since it was read byguest 32 times for each interrupt.There's no reason to do this for the new PCIHP: register is only readonce for each interrupt, so clean up code by making read act as an...
pcihp: replace enable|disable_device() with oneliners
enable_device() and disable_device() functions aren't reused anywere,so replace them with respective oneliners at call sites.
pcihp: make PCI hotplug mmio handlers indifferent to PCI_HOTPLUG_ADDR
... removes dependency of mmio handler on PCI_HOTPLUG_ADDR.It will be needed in case of Q35 where base could be different.
pcihp: make pci_read() mmio calback compatible with legacy ACPI hotplug
due to recent change introduced by:"pcihp: reduce number of device check events"
'up' field is cleared right after it's read.This is incompatible with legacy BIOS ACPI codewhere PCNF ACPI method reads this field 32 times....
Merge remote-tracking branch 'remotes/borntraeger/tags/kvm-s390-20140131' into staging
This patch set contains the sclp defines and events for cpu hotplug,the initial sclp defines (without code yet) for standby memory (somesort of memory hotplug) as well as a cleanup of the kvm register...
Merge remote-tracking branch 'remotes/mcayland/qemu-openbios' into staging
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
cris: Remove the CRIS PIC glue
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
linux-user: Fix trampoline code for CRIS
__put_user can write bytes, words (2 bytes) or longwords (4 bytes).Here obviously words should have been written, but bytes were written,so values like 0x9c5f were truncated to 0x5f.
Fix this by changing retcode from uint8_t to to uint16_t in...
cris: Abort when a v10 takes interrupts while in a delayslot
This is an internal error as the CRISv10 should mask interruptswhile executing delay slots. Bail out sooner rather than later.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
cris: Add interrupt signals to the CPU device
axis-dev88: Connect the PIC upstream IRQs directly to the CPU
cris: Add "any" as alias for "crisv32" in user emulation
Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Merge remote-tracking branch 'qmp-unstable/queue/qmp' into staging
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140131' into staging
target-arm queue: * implementation of first part of the A64 Neon instruction set * v8 AArch32 rounding and 16<->64 fp conversion instructions * fix MIDR value on Zynq boards...
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-pci-for-qemu-20140128.0' into staging
vfio-pci updates include: - Destroy MemoryRegions on device teardown - Print warnings around PCI option ROM failures - Skip bogus mappings from 64bit BAR sizing...
Merge remote-tracking branch 'remotes/sstabellini/xen-140130' into staging
arm_gic: Introduce define for GIC_NR_SGIS
Instead of hardcoding 16 various places in the code, use a define tomake it more clear what is going on.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes
Fix two bugs that would allow changing the state of SGIs through theICPENDR and ISPENDRs.
target-arm: A64: Add top level decode for SIMD 3-same group
Add top level decode for the A64 SIMD three regs same group(C3.6.16), splitting it into the pairwise, logical, float andinteger subgroups.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Add logic ops from SIMD 3 same group
Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL,BIT and BIF) from the SIMD 3 register same group (C3.6.16).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Add integer ops from SIMD 3-same group
Add some of the integer operations in the SIMD 3-same group:specifically, the comparisons, addition and subtraction.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add simple SIMD 3-same floating point ops
Implement a simple subset of the SIMD 3-same floating pointoperations. This includes a common helper function used for bothscalar and vector ops; FABD is the only currently implementedshared op....
target-arm: A64: Add SIMD shift by immediate
This implements a subset of the AdvSIMD shift operations (namely all thenone saturating or narrowing ones). The actual shift generation codeitself is common for both the scalar and vector cases but wrapped with...
target-arm: A64: Add SIMD three-different multiply accumulate insns
Add support for the multiply-accumulate instructions from theSIMD three-different instructions group (C3.6.15): * skeleton decode of unallocated encodings and split of the group into its three sub-parts...
target-arm: A64: Add SIMD three-different ABDL instructions
Implement the absolute-difference instructions in the SIMDthree-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,SABDL2, UABDL, UABDL2.
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
Implement the add, sub and compare ops from the SIMD "scalar three same" group.
target-arm: Add set_neon_rmode helper
This helper sets the rounding mode in the standard_fp_status word toallow NEON instructions to modify the rounding mode whilst using thestandard FPSCR values for everything else.
Signed-off-by: Will Newton <will.newton@linaro.org>...
target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTPVRINTM and VRINTZ instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM
Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTPand VCVTM instructions.
target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM
Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTPand VCVTM instructions.
target-arm: Add support for AArch32 FP VRINTR
Add support for the AArch32 floating-point VRINTR instruction.
target-arm: Add support for AArch32 FP VRINTZ
Add support for the AArch32 floating-point VRINTZ instruction.
target-arm: Add support for AArch32 FP VRINTX
Add support for the AArch32 floating-point VRINTX instruction.
target-arm: Add support for AArch32 SIMD VRINTX
Add support for the AArch32 Advanced SIMD VRINTX instruction.
Signed-off-by: Will Newton <will.newton@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
ZYNQ: Implement board MIDR control for Zynq
This patch uses the fact that the midr variable is now a propertyThis patch sets the midr variable to the boards custom midr
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>Message-id: a3754b10d150af72e4688a993e484fa2b9b8fa21.1390176489.git.alistair.francis@xilinx.com...
display: avoid multi-statement macro
For blizzard, pl110 and tc6393xb this is harmless, but for pxa2xxCoverity noticed that it is used inside an "if" statement.Fix it because it's the file with the highest number of defectsin the whole QEMU tree! Use "do...while (0)", or just remove the...
target-arm: Move arm_rmode_to_sf to a shared location.
This function will be needed for AArch32 ARMv8 support, so move it tohelper.c where it can be used by both targets. Also moves the code outof line, but as it is quite a large function I don't believe this...
target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTMinstructions.
target-arm: A64: Add SIMD modified immediate group
This patch adds support for the AdvSIMD modified immediate group(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf <agraf@suse.de>[AJB: new decode struct, minor bug fixes, optimisation]...
target-arm: A64: Add SIMD scalar copy instructions
Add support for the SIMD scalar copy instruction group (C3.6.7),which consists of the single instruction DUP (element, scalar).
hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting
The code which decides whether to set up the ATAGS data structure onreset was using the wrong conditional, which meant we were creatingan ATAGS structure when doing a device-tree boot if the dtb was...
ARM: Convert MIDR to a property
Convert the MIDR register to a property. This allows boards to later seta custom MIDR value. This has been done in such a way to maintaincompatibility with all existing CPUs and boards
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>...
target-arm: A64: Add SIMD TBL/TBLX
Add support for the SIMD TBL/TBLX instructions (group C3.6.2).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: rewritten to do more of the decode in translate-a64.c, and to do only one 64 bit pass at a time in the helper]...
target-arm: A64: Add SIMD ZIP/UZP/TRN
Add support for the SIMD ZIP/UZIP/TRN instruction group(C3.6.3).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: use new do_vec_get/set etc functions and generally update to new codebase standards; refactor to pull per-element loop outside switch]...
target-arm: A64: Add SIMD across-lanes instructions
Add support for the SIMD "across lanes" instruction group (C3.6.4).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: Updated to current codebase, added fp min/max ops, added unallocated encoding checks]...
target-arm: A64: Add SIMD copy operations
This adds support for the all the AdvSIMD vector copy operations(ARM ARM 3.6.5).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD ld/st multiple
This adds support support for the SIMD load/storemultiple category of instructions.
This also brings in a couple of helper functions for manipulatingsections of the SIMD registers:
target-arm: A64: Add SIMD ld/st single
Implement the SIMD ld/st single structure instructions.
target-arm: A64: Add decode skeleton for SIMD data processing insns
Add decode skeleton and function placeholders for all the SIMD dataprocessing instructions. Due to the complexity of this part of thetable the normal extract and switch approach gets very messy very...
target-arm: A64: Add SIMD EXT
Add support for the SIMD EXT instruction (the only one in itsgroup, C3.6.1).
Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into staging
Tracing pull request
s390x/kvm: cleanup partial register handling
The partial register handling (introduced with commits420840e58b85f7f4e5493dca3f273566f261090a and3474b679486caa8f6448bae974e131370f360c13 ) aimed to improve intercepthandling performance.
It made the code more complicated though. During development for life...
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
acpi,pci,pc,virtio fixes and enhancements
This includes new unit-tests for acpi by Marcel,hotplug for pci bridges by myself (piix only so far)and cpu hotplug for q35.And a bunch of fixes all over the place as usual....
Merge remote-tracking branch 'sstabellini/xen-170114' into staging
Message-id: alpine.DEB.2.02.1401171537140.21510@kaball.uk.xensource.com...
Merge remote-tracking branch 'stefanha/tags/net-pull-request' into staging
Net patches
Merge remote-tracking branch 'rth/tcg-movbe' into staging
address_space_translate: do not cross page boundaries
The following commit:
commit 149f54b53b7666a3facd45e86eece60ce7d3b114Author: Paolo Bonzini <pbonzini@redhat.com>Date: Fri May 24 12:59:37 2013 +0200
memory: add address_space_translate
breaks Xen support in QEMU, in particular the Xen mapcache. The effect...
Merge remote-tracking branch 'mjt/tags/trivial-patches-2014-01-16' into staging
trivial-patches for 2014-01-16
TCG: Fix I64-on-32bit-host temporaries
We have cache pools of temporaries that we can reuse later when they'vealready been allocated before.
These cache pools differenciate between the target TCG variable type theycontain. So we have one pool for I32 and one pool for I64 variables....
monitor: Cleanup mon->outbuf on write error
In case monitor_flush() fails to write the contents of mon->outbuf tothe output device, mon->outbuf is not cleaned up properly. Check thereturn code of the qemu_chr_fe_write() function and cleanup the outbufif it fails....
virtio_rng: replace custom backend API with UserCreatable.complete() callback
in addition fix default backend leak by releasing it if itsinitialization failed.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>...
add optional 2nd stage initialization to -object/object-add commands
Introduces USER_CREATABLE interface that must be implemented byobjects which are designed to created with -object CLI option orobject-add QMP command.
Interface provides an ability to do an optional second stage...
object_add: consolidate error handling
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
vl.c: -object: don't ignore duplicate 'id'
object_property_add_child() may fail if 'id' matchesan already existing object. Which means an incorrectcommand line.So instead of silently ignoring error, report it andterminate QEMU.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>...
vfio: correct debug macro typo
Change to DEBUG_VFIO in vfio_msi_interrupt() for debugmessages to get printed
Signed-off-by: Bandan Das <bsd@redhat.com>Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
sclp-s390: Define new SCLP codes and structures
Define new SCLP codes and structures that will be needed fors390 memory hotplug.
Signed-off-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com>Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
tracing: start trace processing thread in final child process
When running with trace backend e.g. "simple" the writer thread needs to beimplemented in the same process context as the trace points that will beprocessed. Under libvirtd control, qemu gets first started in daemonized...
trace: [simple] Do not include "trace/simple.h" in generated tracer headers
The header is not necessary, given that the simple backend does not define anyinlined tracing routines.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
trace: add glib 2.32+ static GMutex support
The GStaticMutex API was deprecated in glib 2.32. We cannot switch overto GMutex unconditionally since we would drop support for older glibversions. But the deprecated API warnings during build are annoying so...
trace: fix simple trace "disable" keyword
The trace-events "disable" keyword turns an event into a nop atcompile-time. This is important for high-frequency events that canimpact performance.
The "disable" keyword is currently broken in the simple trace backend....
net: Use g_strdup_printf instead of snprintf.
assign_name() in net/net.c is using snprintf + g_strdup to get the sameresult as g_strdup_printf.
Signed-off-by: Hani Benhabiles <kroosec@gmail.com>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Fix lan9118 TX "CMD A" handling
The 9118 ethernet controller supports transmission of multi-buffer packetswith arbitrary byte alignment of the start and end bytes. All writes tothe packet fifo are 32 bits, so the controller discards bytes at the beginning...
Fix lan9118 buffer length handling
tap-linux: Get features once and use it many times
Signed-off-by: Kusanagi Kouichi <slash@ac.auone-net.jp>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
acpi-test: update expected AML since recent changes
hw/pci: fix error flow in pci multifunction init
Scenario: - There is a non multifunction pci device A on 00:0X.0. - Hot-plug another multifunction pci device B at 00:0X.1. - The operation will fail of course. - Try to hot-plug the B device 2-3 more times, qemu will crash....
pc: Save size of RAM below 4GB
The ram_below_4g value will be useful in other places, such as the ACPItable code, and other code that currently requires passingbelow_4g_mem_size around in function arguments.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>...
acpi: Fix PCI hole handling on build_srat()
The original SeaBIOS code used the RamSize variable, that was used bySeaBIOS for the size of RAM below 4GB, not for all RAM. When copied toQEMU, the code was changed to use the full RAM size, and this broke the...
q35: gigabyte alignment for ram
Map 2G (q35) of memory below 4G, so the RAM piecesare nicely aligned to gigabyte borders.
Keep old memory layout for (a) old machine types and (b) in case allmemory fits below 4G and thus we don't have to split RAM into pieces...
q35: document gigabyte_align
Document the logic behind the below/above 4G split.
MAINTAINERS: add self as virtio co-maintainer
This will help make sure I get Cc'd on patches.
pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources
... for range defined at hw/acpi/ich9.c:ICH9_PROC_BASE
pc: ACPI: expose PRST IO range via _CRS
.. so OSPM could notice resource conflict if there is any.
pc: ACPI: unify source of CPU hotplug IO base/len
use C headers defines as source of IO base/len for respectivevalues in ASL code.
pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated