Revision 5eb7995e target-ppc/helper.c
| b/target-ppc/helper.c | ||
|---|---|---|
| 1013 | 1013 |
env->spr[SPR_405_SLER] = val; |
| 1014 | 1014 |
} |
| 1015 | 1015 |
|
| 1016 |
int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
|
| 1017 |
target_ulong address, int rw, |
|
| 1018 |
int access_type) |
|
| 1019 |
{
|
|
| 1020 |
ppcemb_tlb_t *tlb; |
|
| 1021 |
target_phys_addr_t raddr; |
|
| 1022 |
int i, prot, ret; |
|
| 1023 |
|
|
| 1024 |
ret = -1; |
|
| 1025 |
raddr = -1; |
|
| 1026 |
for (i = 0; i < env->nb_tlb; i++) {
|
|
| 1027 |
tlb = &env->tlb[i].tlbe; |
|
| 1028 |
if (ppcemb_tlb_check(env, tlb, &raddr, address, |
|
| 1029 |
env->spr[SPR_BOOKE_PID], 1, i) < 0) |
|
| 1030 |
continue; |
|
| 1031 |
if (msr_pr) |
|
| 1032 |
prot = tlb->prot & 0xF; |
|
| 1033 |
else |
|
| 1034 |
prot = (tlb->prot >> 4) & 0xF; |
|
| 1035 |
/* Check the address space */ |
|
| 1036 |
if (access_type == ACCESS_CODE) {
|
|
| 1037 |
if (msr_is != (tlb->attr & 1)) |
|
| 1038 |
continue; |
|
| 1039 |
ctx->prot = prot; |
|
| 1040 |
if (prot & PAGE_EXEC) {
|
|
| 1041 |
ret = 0; |
|
| 1042 |
break; |
|
| 1043 |
} |
|
| 1044 |
ret = -3; |
|
| 1045 |
} else {
|
|
| 1046 |
if (msr_ds != (tlb->attr & 1)) |
|
| 1047 |
continue; |
|
| 1048 |
ctx->prot = prot; |
|
| 1049 |
if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
|
| 1050 |
ret = 0; |
|
| 1051 |
break; |
|
| 1052 |
} |
|
| 1053 |
ret = -2; |
|
| 1054 |
} |
|
| 1055 |
} |
|
| 1056 |
if (ret >= 0) |
|
| 1057 |
ctx->raddr = raddr; |
|
| 1058 |
|
|
| 1059 |
return ret; |
|
| 1060 |
} |
|
| 1061 |
|
|
| 1016 | 1062 |
static int check_physical (CPUState *env, mmu_ctx_t *ctx, |
| 1017 | 1063 |
target_ulong eaddr, int rw) |
| 1018 | 1064 |
{
|
| ... | ... | |
| 1115 | 1161 |
cpu_abort(env, "601 MMU model not implemented\n"); |
| 1116 | 1162 |
return -1; |
| 1117 | 1163 |
case PPC_FLAGS_MMU_BOOKE: |
| 1118 |
/* XXX: TODO */
|
|
| 1119 |
cpu_abort(env, "BookeE MMU model not implemented\n");
|
|
| 1120 |
return -1;
|
|
| 1164 |
ret = mmubooke_get_physical_address(env, ctx, eaddr,
|
|
| 1165 |
rw, access_type);
|
|
| 1166 |
break;
|
|
| 1121 | 1167 |
case PPC_FLAGS_MMU_BOOKE_FSL: |
| 1122 | 1168 |
/* XXX: TODO */ |
| 1123 | 1169 |
cpu_abort(env, "BookE FSL MMU model not implemented\n"); |
| ... | ... | |
| 1950 | 1996 |
cpu_abort(env, "Floating point assist exception " |
| 1951 | 1997 |
"is not implemented yet !\n"); |
| 1952 | 1998 |
goto store_next; |
| 1953 |
/* 64 bits PowerPC exceptions */
|
|
| 1999 |
/* 64 bits PowerPC exceptions */ |
|
| 1954 | 2000 |
case EXCP_DSEG: /* 0x0380 */ |
| 1955 | 2001 |
/* XXX: TODO */ |
| 1956 | 2002 |
cpu_abort(env, "Data segment exception is not implemented yet !\n"); |
| ... | ... | |
| 2446 | 2492 |
void cpu_ppc_reset (void *opaque) |
| 2447 | 2493 |
{
|
| 2448 | 2494 |
CPUPPCState *env; |
| 2495 |
int i; |
|
| 2449 | 2496 |
|
| 2450 | 2497 |
env = opaque; |
| 2498 |
/* XXX: some of those flags initialisation values could depend |
|
| 2499 |
* on the actual PowerPC implementation |
|
| 2500 |
*/ |
|
| 2501 |
for (i = 0; i < 63; i++) |
|
| 2502 |
env->msr[i] = 0; |
|
| 2503 |
#if defined(TARGET_PPC64) |
|
| 2504 |
msr_hv = 0; /* Should be 1... */ |
|
| 2505 |
#endif |
|
| 2506 |
msr_ap = 0; /* TO BE CHECKED */ |
|
| 2507 |
msr_sa = 0; /* TO BE CHECKED */ |
|
| 2508 |
msr_ip = 0; /* TO BE CHECKED */ |
|
| 2451 | 2509 |
#if defined (DO_SINGLE_STEP) && 0 |
| 2452 | 2510 |
/* Single step trace mode */ |
| 2453 | 2511 |
msr_se = 1; |
| 2454 | 2512 |
msr_be = 1; |
| 2455 | 2513 |
#endif |
| 2456 |
msr_fp = 1; /* Allow floating point exceptions */ |
|
| 2457 |
msr_me = 1; /* Allow machine check exceptions */ |
|
| 2458 |
#if defined(TARGET_PPC64) |
|
| 2459 |
msr_sf = 0; /* Boot in 32 bits mode */ |
|
| 2460 |
msr_cm = 0; |
|
| 2461 |
#endif |
|
| 2462 | 2514 |
#if defined(CONFIG_USER_ONLY) |
| 2515 |
msr_fp = 1; /* Allow floating point exceptions */ |
|
| 2463 | 2516 |
msr_pr = 1; |
| 2464 |
tlb_flush(env, 1); |
|
| 2465 | 2517 |
#else |
| 2466 | 2518 |
env->nip = 0xFFFFFFFC; |
| 2467 | 2519 |
ppc_tlb_invalidate_all(env); |
| 2468 | 2520 |
#endif |
| 2469 | 2521 |
do_compute_hflags(env); |
| 2470 | 2522 |
env->reserve = -1; |
| 2523 |
/* Be sure no exception or interrupt is pending */ |
|
| 2524 |
env->pending_interrupts = 0; |
|
| 2525 |
env->exception_index = EXCP_NONE; |
|
| 2526 |
/* Flush all TLBs */ |
|
| 2527 |
tlb_flush(env, 1); |
|
| 2471 | 2528 |
} |
| 2472 | 2529 |
|
| 2473 | 2530 |
CPUPPCState *cpu_ppc_init (void) |
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