root / target-ppc / cpu.h @ 5eb7995e
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/*
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* PowerPC emulation cpu definitions for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
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#include "config.h" |
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#include <inttypes.h> |
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#if defined (TARGET_PPC64)
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typedef uint64_t ppc_gpr_t;
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#define TARGET_GPR_BITS 64 |
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#define TARGET_LONG_BITS 64 |
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#define REGX "%016" PRIx64 |
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#define TARGET_PAGE_BITS 12 |
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#elif defined(TARGET_PPCEMB)
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/* BookE have 36 bits physical address space */
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#define TARGET_PHYS_ADDR_BITS 64 |
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/* GPR are 64 bits: used by vector extension */
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typedef uint64_t ppc_gpr_t;
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#define TARGET_GPR_BITS 64 |
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#define TARGET_LONG_BITS 32 |
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#define REGX "%016" PRIx64 |
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#if defined(CONFIG_USER_ONLY)
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/* It looks like a lot of Linux programs assume page size
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* is 4kB long. This is evil, but we have to deal with it...
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*/
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#define TARGET_PAGE_BITS 12 |
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#else
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/* Pages can be 1 kB small */
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#define TARGET_PAGE_BITS 10 |
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#endif
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#else
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#if (HOST_LONG_BITS >= 64) |
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/* When using 64 bits temporary registers,
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* we can use 64 bits GPR with no extra cost
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* It's even an optimization as it will prevent
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* the compiler to do unuseful masking in the micro-ops.
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*/
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typedef uint64_t ppc_gpr_t;
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#define TARGET_GPR_BITS 64 |
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#else
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typedef uint32_t ppc_gpr_t;
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#define TARGET_GPR_BITS 32 |
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#endif
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#define TARGET_LONG_BITS 32 |
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#define REGX "%08" PRIx32 |
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#define TARGET_PAGE_BITS 12 |
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#endif
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#include "cpu-defs.h" |
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#define ADDRX TARGET_FMT_lx
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#define PADDRX TARGET_FMT_plx
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#include <setjmp.h> |
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#include "softfloat.h" |
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#define TARGET_HAS_ICE 1 |
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#if defined (TARGET_PPC64)
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#define ELF_MACHINE EM_PPC64
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#else
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#define ELF_MACHINE EM_PPC
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#endif
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/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
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* have different cache line sizes
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*/
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#define ICACHE_LINE_SIZE 32 |
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#define DCACHE_LINE_SIZE 32 |
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/* XXX: put this in a common place */
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#define likely(x) __builtin_expect(!!(x), 1) |
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#define unlikely(x) __builtin_expect(!!(x), 0) |
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/*****************************************************************************/
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/* PVR definitions for most known PowerPC */
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enum {
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/* PowerPC 401 cores */
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CPU_PPC_401A1 = 0x00210000,
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CPU_PPC_401B2 = 0x00220000,
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CPU_PPC_401C2 = 0x00230000,
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CPU_PPC_401D2 = 0x00240000,
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CPU_PPC_401E2 = 0x00250000,
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CPU_PPC_401F2 = 0x00260000,
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CPU_PPC_401G2 = 0x00270000,
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#define CPU_PPC_401 CPU_PPC_401G2
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CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */ |
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CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */ |
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/* PowerPC 403 cores */
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CPU_PPC_403GA = 0x00200011,
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CPU_PPC_403GB = 0x00200100,
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CPU_PPC_403GC = 0x00200200,
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CPU_PPC_403GCX = 0x00201400,
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#define CPU_PPC_403 CPU_PPC_403GCX
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/* PowerPC 405 cores */
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CPU_PPC_405CR = 0x40110145,
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#define CPU_PPC_405GP CPU_PPC_405CR
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CPU_PPC_405EP = 0x51210950,
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CPU_PPC_405GPR = 0x50910951,
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CPU_PPC_405D2 = 0x20010000,
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CPU_PPC_405D4 = 0x41810000,
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#define CPU_PPC_405 CPU_PPC_405D4
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CPU_PPC_NPE405H = 0x414100C0,
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CPU_PPC_NPE405H2 = 0x41410140,
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CPU_PPC_NPE405L = 0x416100C0,
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/* XXX: missing 405LP, LC77700 */
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/* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
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#if 0
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CPU_PPC_STB01000 = xxx,
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#endif
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#if 0
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CPU_PPC_STB01010 = xxx,
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#endif
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#if 0
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CPU_PPC_STB0210 = xxx,
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#endif
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CPU_PPC_STB03 = 0x40310000,
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#if 0
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CPU_PPC_STB043 = xxx,
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#endif
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#if 0
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CPU_PPC_STB045 = xxx,
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#endif
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CPU_PPC_STB25 = 0x51510950,
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#if 0
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CPU_PPC_STB130 = xxx,
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#endif
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/* Xilinx cores */
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CPU_PPC_X2VP4 = 0x20010820,
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#define CPU_PPC_X2VP7 CPU_PPC_X2VP4
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CPU_PPC_X2VP20 = 0x20010860,
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#define CPU_PPC_X2VP50 CPU_PPC_X2VP20
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/* PowerPC 440 cores */
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CPU_PPC_440EP = 0x422218D3,
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#define CPU_PPC_440GR CPU_PPC_440EP
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CPU_PPC_440GP = 0x40120481,
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CPU_PPC_440GX = 0x51B21850,
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CPU_PPC_440GXc = 0x51B21892,
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CPU_PPC_440GXf = 0x51B21894,
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CPU_PPC_440SP = 0x53221850,
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CPU_PPC_440SP2 = 0x53221891,
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CPU_PPC_440SPE = 0x53421890,
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/* XXX: missing 440GRX */
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/* PowerPC 460 cores - TODO */
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/* PowerPC MPC 5xx cores */
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CPU_PPC_5xx = 0x00020020,
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/* PowerPC MPC 8xx cores (aka PowerQUICC) */
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CPU_PPC_8xx = 0x00500000,
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/* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
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CPU_PPC_82xx_HIP3 = 0x00810101,
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CPU_PPC_82xx_HIP4 = 0x80811014,
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CPU_PPC_827x = 0x80822013,
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/* eCores */
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CPU_PPC_e200 = 0x81120000,
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CPU_PPC_e500v110 = 0x80200010,
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CPU_PPC_e500v120 = 0x80200020,
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CPU_PPC_e500v210 = 0x80210010,
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CPU_PPC_e500v220 = 0x80210020,
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#define CPU_PPC_e500 CPU_PPC_e500v220
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CPU_PPC_e600 = 0x80040010,
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/* PowerPC 6xx cores */
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CPU_PPC_601 = 0x00010001,
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CPU_PPC_602 = 0x00050100,
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CPU_PPC_603 = 0x00030100,
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CPU_PPC_603E = 0x00060101,
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CPU_PPC_603P = 0x00070000,
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CPU_PPC_603E7v = 0x00070100,
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CPU_PPC_603E7v2 = 0x00070201,
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CPU_PPC_603E7 = 0x00070200,
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CPU_PPC_603R = 0x00071201,
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CPU_PPC_G2 = 0x00810011,
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CPU_PPC_G2H4 = 0x80811010,
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CPU_PPC_G2gp = 0x80821010,
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CPU_PPC_G2ls = 0x90810010,
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CPU_PPC_G2LE = 0x80820010,
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CPU_PPC_G2LEgp = 0x80822010,
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CPU_PPC_G2LEls = 0xA0822010,
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CPU_PPC_604 = 0x00040000,
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CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */ |
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CPU_PPC_604R = 0x000a0101,
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/* PowerPC 74x/75x cores (aka G3) */
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CPU_PPC_74x = 0x00080000,
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CPU_PPC_740E = 0x00080100,
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CPU_PPC_750E = 0x00080200,
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CPU_PPC_755_10 = 0x00083100,
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CPU_PPC_755_11 = 0x00083101,
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CPU_PPC_755_20 = 0x00083200,
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CPU_PPC_755D = 0x00083202,
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CPU_PPC_755E = 0x00083203,
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#define CPU_PPC_755 CPU_PPC_755E
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CPU_PPC_74xP = 0x10080000,
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CPU_PPC_750CXE21 = 0x00082201,
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CPU_PPC_750CXE22 = 0x00082212,
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CPU_PPC_750CXE23 = 0x00082203,
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CPU_PPC_750CXE24 = 0x00082214,
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CPU_PPC_750CXE24b = 0x00083214,
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CPU_PPC_750CXE31 = 0x00083211,
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CPU_PPC_750CXE31b = 0x00083311,
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#define CPU_PPC_750CXE CPU_PPC_750CXE31b
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CPU_PPC_750CXR = 0x00083410,
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CPU_PPC_750FX10 = 0x70000100,
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CPU_PPC_750FX20 = 0x70000200,
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CPU_PPC_750FX21 = 0x70000201,
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CPU_PPC_750FX22 = 0x70000202,
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CPU_PPC_750FX23 = 0x70000203,
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#define CPU_PPC_750FX CPU_PPC_750FX23
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CPU_PPC_750FL = 0x700A0203,
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CPU_PPC_750GX10 = 0x70020100,
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CPU_PPC_750GX11 = 0x70020101,
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CPU_PPC_750GX12 = 0x70020102,
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#define CPU_PPC_750GX CPU_PPC_750GX12
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CPU_PPC_750GL = 0x70020102,
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CPU_PPC_750L30 = 0x00088300,
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CPU_PPC_750L32 = 0x00088302,
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CPU_PPC_750CL = 0x00087200,
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/* PowerPC 74xx cores (aka G4) */
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CPU_PPC_7400 = 0x000C0100,
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CPU_PPC_7410C = 0x800C1102,
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CPU_PPC_7410D = 0x800C1103,
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CPU_PPC_7410E = 0x800C1104,
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CPU_PPC_7441 = 0x80000210,
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CPU_PPC_7445 = 0x80010100,
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CPU_PPC_7447 = 0x80020100,
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CPU_PPC_7447A = 0x80030101,
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CPU_PPC_7448 = 0x80040100,
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CPU_PPC_7450 = 0x80000200,
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CPU_PPC_7450b = 0x80000201,
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CPU_PPC_7451 = 0x80000203,
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CPU_PPC_7451G = 0x80000210,
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CPU_PPC_7455 = 0x80010201,
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CPU_PPC_7455F = 0x80010303,
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CPU_PPC_7455G = 0x80010304,
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CPU_PPC_7457 = 0x80020101,
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CPU_PPC_7457C = 0x80020102,
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CPU_PPC_7457A = 0x80030000,
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/* 64 bits PowerPC */
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CPU_PPC_620 = 0x00140000,
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CPU_PPC_630 = 0x00400000,
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CPU_PPC_631 = 0x00410000,
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CPU_PPC_POWER4 = 0x00350000,
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CPU_PPC_POWER4P = 0x00380000,
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CPU_PPC_POWER5 = 0x003A0000,
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CPU_PPC_POWER5P = 0x003B0000,
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CPU_PPC_970 = 0x00390000,
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CPU_PPC_970FX10 = 0x00391100,
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CPU_PPC_970FX20 = 0x003C0200,
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CPU_PPC_970FX21 = 0x003C0201,
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CPU_PPC_970FX30 = 0x003C0300,
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CPU_PPC_970FX31 = 0x003C0301,
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#define CPU_PPC_970FX CPU_PPC_970FX31
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CPU_PPC_970MP10 = 0x00440100,
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CPU_PPC_970MP11 = 0x00440101,
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#define CPU_PPC_970MP CPU_PPC_970MP11
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CPU_PPC_CELL10 = 0x00700100,
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CPU_PPC_CELL20 = 0x00700400,
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CPU_PPC_CELL30 = 0x00700500,
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CPU_PPC_CELL31 = 0x00700501,
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#define CPU_PPC_CELL32 CPU_PPC_CELL31
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#define CPU_PPC_CELL CPU_PPC_CELL32
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CPU_PPC_RS64 = 0x00330000,
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CPU_PPC_RS64II = 0x00340000,
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CPU_PPC_RS64III = 0x00360000,
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CPU_PPC_RS64IV = 0x00370000,
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/* Original POWER */
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/* XXX: should be POWER (RIOS), RSC3308, RSC4608,
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* POWER2 (RIOS2) & RSC2 (P2SC) here
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*/
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#if 0
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CPU_POWER = xxx,
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#endif
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#if 0
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CPU_POWER2 = xxx,
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#endif
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}; |
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/* System version register (used on MPC 8xxx) */
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enum {
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PPC_SVR_8540 = 0x80300000,
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PPC_SVR_8541E = 0x807A0010,
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PPC_SVR_8543v10 = 0x80320010,
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PPC_SVR_8543v11 = 0x80320011,
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PPC_SVR_8543v20 = 0x80320020,
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PPC_SVR_8543Ev10 = 0x803A0010,
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PPC_SVR_8543Ev11 = 0x803A0011,
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PPC_SVR_8543Ev20 = 0x803A0020,
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PPC_SVR_8545 = 0x80310220,
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PPC_SVR_8545E = 0x80390220,
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PPC_SVR_8547E = 0x80390120,
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PPC_SCR_8548v10 = 0x80310010,
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PPC_SCR_8548v11 = 0x80310011,
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PPC_SCR_8548v20 = 0x80310020,
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PPC_SVR_8548Ev10 = 0x80390010,
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PPC_SVR_8548Ev11 = 0x80390011,
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PPC_SVR_8548Ev20 = 0x80390020,
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PPC_SVR_8555E = 0x80790010,
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PPC_SVR_8560v10 = 0x80700010,
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PPC_SVR_8560v20 = 0x80700020,
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}; |
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/*****************************************************************************/
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/* Instruction types */
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enum {
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PPC_NONE = 0x00000000,
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/* integer operations instructions */
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/* flow control instructions */
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/* virtual memory instructions */
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/* ld/st with reservation instructions */
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/* cache control instructions */
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/* spr/msr access instructions */
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PPC_INSNS_BASE = 0x0000000000000001ULL,
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#define PPC_INTEGER PPC_INSNS_BASE
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#define PPC_FLOW PPC_INSNS_BASE
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#define PPC_MEM PPC_INSNS_BASE
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#define PPC_RES PPC_INSNS_BASE
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#define PPC_CACHE PPC_INSNS_BASE
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#define PPC_MISC PPC_INSNS_BASE
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/* floating point operations instructions */
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PPC_FLOAT = 0x0000000000000002ULL,
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/* more floating point operations instructions */
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PPC_FLOAT_EXT = 0x0000000000000004ULL,
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/* external control instructions */
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PPC_EXTERN = 0x0000000000000008ULL,
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/* segment register access instructions */
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PPC_SEGMENT = 0x0000000000000010ULL,
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/* Optional cache control instructions */
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PPC_CACHE_OPT = 0x0000000000000020ULL,
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/* Optional floating point op instructions */
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PPC_FLOAT_OPT = 0x0000000000000040ULL,
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/* Optional memory control instructions */
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PPC_MEM_TLBIA = 0x0000000000000080ULL,
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PPC_MEM_TLBIE = 0x0000000000000100ULL,
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PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
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/* eieio & sync */
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PPC_MEM_SYNC = 0x0000000000000400ULL,
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/* PowerPC 6xx TLB management instructions */
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PPC_6xx_TLB = 0x0000000000000800ULL,
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/* Altivec support */
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PPC_ALTIVEC = 0x0000000000001000ULL,
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/* Time base support */
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PPC_TB = 0x0000000000002000ULL,
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/* Embedded PowerPC dedicated instructions */
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PPC_EMB_COMMON = 0x0000000000004000ULL,
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/* PowerPC 40x exception model */
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PPC_40x_EXCP = 0x0000000000008000ULL,
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/* PowerPC 40x specific instructions */
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PPC_40x_SPEC = 0x0000000000010000ULL,
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/* PowerPC 405 Mac instructions */
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PPC_405_MAC = 0x0000000000020000ULL,
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/* PowerPC 440 specific instructions */
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PPC_440_SPEC = 0x0000000000040000ULL,
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/* Specific extensions */
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/* Power-to-PowerPC bridge (601) */
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PPC_POWER_BR = 0x0000000000080000ULL,
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/* PowerPC 602 specific */
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PPC_602_SPEC = 0x0000000000100000ULL,
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/* Deprecated instructions */
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/* Original POWER instruction set */
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PPC_POWER = 0x0000000000200000ULL,
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/* POWER2 instruction set extension */
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PPC_POWER2 = 0x0000000000400000ULL,
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/* Power RTC support */
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PPC_POWER_RTC = 0x0000000000800000ULL,
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/* 64 bits PowerPC instructions */
|
| 383 |
/* 64 bits PowerPC instruction set */
|
| 384 |
PPC_64B = 0x0000000001000000ULL,
|
| 385 |
/* 64 bits hypervisor extensions */
|
| 386 |
PPC_64H = 0x0000000002000000ULL,
|
| 387 |
/* 64 bits PowerPC "bridge" features */
|
| 388 |
PPC_64_BRIDGE = 0x0000000004000000ULL,
|
| 389 |
/* BookE (embedded) PowerPC specification */
|
| 390 |
PPC_BOOKE = 0x0000000008000000ULL,
|
| 391 |
/* eieio */
|
| 392 |
PPC_MEM_EIEIO = 0x0000000010000000ULL,
|
| 393 |
/* e500 vector instructions */
|
| 394 |
PPC_E500_VECTOR = 0x0000000020000000ULL,
|
| 395 |
/* PowerPC 4xx dedicated instructions */
|
| 396 |
PPC_4xx_COMMON = 0x0000000040000000ULL,
|
| 397 |
/* PowerPC 2.03 specification extensions */
|
| 398 |
PPC_203 = 0x0000000080000000ULL,
|
| 399 |
/* PowerPC 2.03 SPE extension */
|
| 400 |
PPC_SPE = 0x0000000100000000ULL,
|
| 401 |
/* PowerPC 2.03 SPE floating-point extension */
|
| 402 |
PPC_SPEFPU = 0x0000000200000000ULL,
|
| 403 |
/* SLB management */
|
| 404 |
PPC_SLBI = 0x0000000400000000ULL,
|
| 405 |
}; |
| 406 |
|
| 407 |
/* CPU run-time flags (MMU and exception model) */
|
| 408 |
enum {
|
| 409 |
/* MMU model */
|
| 410 |
PPC_FLAGS_MMU_MASK = 0x000000FF,
|
| 411 |
/* Standard 32 bits PowerPC MMU */
|
| 412 |
PPC_FLAGS_MMU_32B = 0x00000000,
|
| 413 |
/* Standard 64 bits PowerPC MMU */
|
| 414 |
PPC_FLAGS_MMU_64B = 0x00000001,
|
| 415 |
/* PowerPC 601 MMU */
|
| 416 |
PPC_FLAGS_MMU_601 = 0x00000002,
|
| 417 |
/* PowerPC 6xx MMU with software TLB */
|
| 418 |
PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
|
| 419 |
/* PowerPC 4xx MMU with software TLB */
|
| 420 |
PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
|
| 421 |
/* PowerPC 403 MMU */
|
| 422 |
PPC_FLAGS_MMU_403 = 0x00000005,
|
| 423 |
/* BookE FSL MMU model */
|
| 424 |
PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006,
|
| 425 |
/* BookE MMU model */
|
| 426 |
PPC_FLAGS_MMU_BOOKE = 0x00000007,
|
| 427 |
/* 64 bits "bridge" PowerPC MMU */
|
| 428 |
PPC_FLAGS_MMU_64BRIDGE = 0x00000008,
|
| 429 |
/* Exception model */
|
| 430 |
PPC_FLAGS_EXCP_MASK = 0x0000FF00,
|
| 431 |
/* Standard PowerPC exception model */
|
| 432 |
PPC_FLAGS_EXCP_STD = 0x00000000,
|
| 433 |
/* PowerPC 40x exception model */
|
| 434 |
PPC_FLAGS_EXCP_40x = 0x00000100,
|
| 435 |
/* PowerPC 601 exception model */
|
| 436 |
PPC_FLAGS_EXCP_601 = 0x00000200,
|
| 437 |
/* PowerPC 602 exception model */
|
| 438 |
PPC_FLAGS_EXCP_602 = 0x00000300,
|
| 439 |
/* PowerPC 603 exception model */
|
| 440 |
PPC_FLAGS_EXCP_603 = 0x00000400,
|
| 441 |
/* PowerPC 604 exception model */
|
| 442 |
PPC_FLAGS_EXCP_604 = 0x00000500,
|
| 443 |
/* PowerPC 7x0 exception model */
|
| 444 |
PPC_FLAGS_EXCP_7x0 = 0x00000600,
|
| 445 |
/* PowerPC 7x5 exception model */
|
| 446 |
PPC_FLAGS_EXCP_7x5 = 0x00000700,
|
| 447 |
/* PowerPC 74xx exception model */
|
| 448 |
PPC_FLAGS_EXCP_74xx = 0x00000800,
|
| 449 |
/* PowerPC 970 exception model */
|
| 450 |
PPC_FLAGS_EXCP_970 = 0x00000900,
|
| 451 |
/* BookE exception model */
|
| 452 |
PPC_FLAGS_EXCP_BOOKE = 0x00000A00,
|
| 453 |
/* Input pins model */
|
| 454 |
PPC_FLAGS_INPUT_MASK = 0x000F0000,
|
| 455 |
PPC_FLAGS_INPUT_6xx = 0x00000000,
|
| 456 |
PPC_FLAGS_INPUT_BookE = 0x00010000,
|
| 457 |
PPC_FLAGS_INPUT_40x = 0x00020000,
|
| 458 |
PPC_FLAGS_INPUT_970 = 0x00030000,
|
| 459 |
}; |
| 460 |
|
| 461 |
#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
|
| 462 |
#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
|
| 463 |
#define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK)
|
| 464 |
|
| 465 |
/*****************************************************************************/
|
| 466 |
/* Supported instruction set definitions */
|
| 467 |
/* This generates an empty opcode table... */
|
| 468 |
#define PPC_INSNS_TODO (PPC_NONE)
|
| 469 |
#define PPC_FLAGS_TODO (0x00000000) |
| 470 |
|
| 471 |
/* PowerPC 40x instruction set */
|
| 472 |
#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
|
| 473 |
/* PowerPC 401 */
|
| 474 |
#define PPC_INSNS_401 (PPC_INSNS_TODO)
|
| 475 |
#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
|
| 476 |
/* PowerPC 403 */
|
| 477 |
#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
|
| 478 |
PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \ |
| 479 |
PPC_40x_SPEC) |
| 480 |
#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \
|
| 481 |
PPC_FLAGS_INPUT_40x) |
| 482 |
/* PowerPC 405 */
|
| 483 |
#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
|
| 484 |
PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \ |
| 485 |
PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \ |
| 486 |
PPC_405_MAC) |
| 487 |
#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
|
| 488 |
PPC_FLAGS_INPUT_40x) |
| 489 |
/* PowerPC 440 */
|
| 490 |
#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
|
| 491 |
PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC) |
| 492 |
#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
|
| 493 |
PPC_FLAGS_INPUT_BookE) |
| 494 |
/* Generic BookE PowerPC */
|
| 495 |
#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
|
| 496 |
PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT) |
| 497 |
#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
|
| 498 |
PPC_FLAGS_INPUT_BookE) |
| 499 |
/* e500 core */
|
| 500 |
#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
|
| 501 |
PPC_CACHE_OPT | PPC_E500_VECTOR) |
| 502 |
#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
|
| 503 |
PPC_FLAGS_INPUT_BookE) |
| 504 |
/* Non-embedded PowerPC */
|
| 505 |
#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
|
| 506 |
PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE) |
| 507 |
/* PowerPC 601 */
|
| 508 |
#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
|
| 509 |
#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 | \
|
| 510 |
PPC_FLAGS_INPUT_6xx) |
| 511 |
/* PowerPC 602 */
|
| 512 |
#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
|
| 513 |
PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC) |
| 514 |
#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 | \
|
| 515 |
PPC_FLAGS_INPUT_6xx) |
| 516 |
/* PowerPC 603 */
|
| 517 |
#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
|
| 518 |
PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
| 519 |
#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
|
| 520 |
PPC_FLAGS_INPUT_6xx) |
| 521 |
/* PowerPC G2 */
|
| 522 |
#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
|
| 523 |
PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
| 524 |
#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
|
| 525 |
PPC_FLAGS_INPUT_6xx) |
| 526 |
/* PowerPC 604 */
|
| 527 |
#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
|
| 528 |
PPC_MEM_TLBSYNC | PPC_TB) |
| 529 |
#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 | \
|
| 530 |
PPC_FLAGS_INPUT_6xx) |
| 531 |
/* PowerPC 740/750 (aka G3) */
|
| 532 |
#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
|
| 533 |
PPC_MEM_TLBSYNC | PPC_TB) |
| 534 |
#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 | \
|
| 535 |
PPC_FLAGS_INPUT_6xx) |
| 536 |
/* PowerPC 745/755 */
|
| 537 |
#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
|
| 538 |
PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB) |
| 539 |
#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 | \
|
| 540 |
PPC_FLAGS_INPUT_6xx) |
| 541 |
/* PowerPC 74xx (aka G4) */
|
| 542 |
#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
|
| 543 |
PPC_MEM_TLBSYNC | PPC_TB) |
| 544 |
#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx | \
|
| 545 |
PPC_FLAGS_INPUT_6xx) |
| 546 |
/* PowerPC 970 (aka G5) */
|
| 547 |
#define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \
|
| 548 |
PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \ |
| 549 |
PPC_64B | PPC_64_BRIDGE | PPC_SLBI) |
| 550 |
#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 | \
|
| 551 |
PPC_FLAGS_INPUT_970) |
| 552 |
|
| 553 |
/* Default PowerPC will be 604/970 */
|
| 554 |
#define PPC_INSNS_PPC32 PPC_INSNS_604
|
| 555 |
#define PPC_FLAGS_PPC32 PPC_FLAGS_604
|
| 556 |
#define PPC_INSNS_PPC64 PPC_INSNS_970
|
| 557 |
#define PPC_FLAGS_PPC64 PPC_FLAGS_970
|
| 558 |
#define PPC_INSNS_DEFAULT PPC_INSNS_604
|
| 559 |
#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
|
| 560 |
typedef struct ppc_def_t ppc_def_t; |
| 561 |
|
| 562 |
/*****************************************************************************/
|
| 563 |
/* Types used to describe some PowerPC registers */
|
| 564 |
typedef struct CPUPPCState CPUPPCState; |
| 565 |
typedef struct opc_handler_t opc_handler_t; |
| 566 |
typedef struct ppc_tb_t ppc_tb_t; |
| 567 |
typedef struct ppc_spr_t ppc_spr_t; |
| 568 |
typedef struct ppc_dcr_t ppc_dcr_t; |
| 569 |
typedef struct ppc_avr_t ppc_avr_t; |
| 570 |
typedef union ppc_tlb_t ppc_tlb_t; |
| 571 |
|
| 572 |
/* SPR access micro-ops generations callbacks */
|
| 573 |
struct ppc_spr_t {
|
| 574 |
void (*uea_read)(void *opaque, int spr_num); |
| 575 |
void (*uea_write)(void *opaque, int spr_num); |
| 576 |
#if !defined(CONFIG_USER_ONLY)
|
| 577 |
void (*oea_read)(void *opaque, int spr_num); |
| 578 |
void (*oea_write)(void *opaque, int spr_num); |
| 579 |
#endif
|
| 580 |
const unsigned char *name; |
| 581 |
}; |
| 582 |
|
| 583 |
/* Altivec registers (128 bits) */
|
| 584 |
struct ppc_avr_t {
|
| 585 |
uint32_t u[4];
|
| 586 |
}; |
| 587 |
|
| 588 |
/* Software TLB cache */
|
| 589 |
typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
| 590 |
struct ppc6xx_tlb_t {
|
| 591 |
target_ulong pte0; |
| 592 |
target_ulong pte1; |
| 593 |
target_ulong EPN; |
| 594 |
}; |
| 595 |
|
| 596 |
typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
| 597 |
struct ppcemb_tlb_t {
|
| 598 |
target_phys_addr_t RPN; |
| 599 |
target_ulong EPN; |
| 600 |
target_ulong PID; |
| 601 |
target_ulong size; |
| 602 |
uint32_t prot; |
| 603 |
uint32_t attr; /* Storage attributes */
|
| 604 |
}; |
| 605 |
|
| 606 |
union ppc_tlb_t {
|
| 607 |
ppc6xx_tlb_t tlb6; |
| 608 |
ppcemb_tlb_t tlbe; |
| 609 |
}; |
| 610 |
|
| 611 |
/*****************************************************************************/
|
| 612 |
/* Machine state register bits definition */
|
| 613 |
#define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
| 614 |
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
| 615 |
#define MSR_HV 60 /* hypervisor state hflags */ |
| 616 |
#define MSR_CM 31 /* Computation mode for BookE hflags */ |
| 617 |
#define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
| 618 |
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
| 619 |
#define MSR_VR 25 /* altivec available hflags */ |
| 620 |
#define MSR_SPE 25 /* SPE enable for BookE hflags */ |
| 621 |
#define MSR_AP 23 /* Access privilege state on 602 hflags */ |
| 622 |
#define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
| 623 |
#define MSR_KEY 19 /* key bit on 603e */ |
| 624 |
#define MSR_POW 18 /* Power management */ |
| 625 |
#define MSR_WE 18 /* Wait state enable on embedded PowerPC */ |
| 626 |
#define MSR_TGPR 17 /* TGPR usage on 602/603 */ |
| 627 |
#define MSR_TLB 17 /* TLB update on ? */ |
| 628 |
#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */ |
| 629 |
#define MSR_ILE 16 /* Interrupt little-endian mode */ |
| 630 |
#define MSR_EE 15 /* External interrupt enable */ |
| 631 |
#define MSR_PR 14 /* Problem state hflags */ |
| 632 |
#define MSR_FP 13 /* Floating point available hflags */ |
| 633 |
#define MSR_ME 12 /* Machine check interrupt enable */ |
| 634 |
#define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
| 635 |
#define MSR_SE 10 /* Single-step trace enable hflags */ |
| 636 |
#define MSR_DWE 10 /* Debug wait enable on 405 */ |
| 637 |
#define MSR_UBLE 10 /* User BTB lock enable on e500 */ |
| 638 |
#define MSR_BE 9 /* Branch trace enable hflags */ |
| 639 |
#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */ |
| 640 |
#define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
| 641 |
#define MSR_AL 7 /* AL bit on POWER */ |
| 642 |
#define MSR_IP 6 /* Interrupt prefix */ |
| 643 |
#define MSR_IR 5 /* Instruction relocate */ |
| 644 |
#define MSR_IS 5 /* Instruction address space on embedded PowerPC */ |
| 645 |
#define MSR_DR 4 /* Data relocate */ |
| 646 |
#define MSR_DS 4 /* Data address space on embedded PowerPC */ |
| 647 |
#define MSR_PE 3 /* Protection enable on 403 */ |
| 648 |
#define MSR_EP 3 /* Exception prefix on 601 */ |
| 649 |
#define MSR_PX 2 /* Protection exclusive on 403 */ |
| 650 |
#define MSR_PMM 2 /* Performance monitor mark on POWER */ |
| 651 |
#define MSR_RI 1 /* Recoverable interrupt */ |
| 652 |
#define MSR_LE 0 /* Little-endian mode hflags */ |
| 653 |
#define msr_sf env->msr[MSR_SF]
|
| 654 |
#define msr_isf env->msr[MSR_ISF]
|
| 655 |
#define msr_hv env->msr[MSR_HV]
|
| 656 |
#define msr_cm env->msr[MSR_CM]
|
| 657 |
#define msr_icm env->msr[MSR_ICM]
|
| 658 |
#define msr_ucle env->msr[MSR_UCLE]
|
| 659 |
#define msr_vr env->msr[MSR_VR]
|
| 660 |
#define msr_spe env->msr[MSR_SPE]
|
| 661 |
#define msr_ap env->msr[MSR_AP]
|
| 662 |
#define msr_sa env->msr[MSR_SA]
|
| 663 |
#define msr_key env->msr[MSR_KEY]
|
| 664 |
#define msr_pow env->msr[MSR_POW]
|
| 665 |
#define msr_we env->msr[MSR_WE]
|
| 666 |
#define msr_tgpr env->msr[MSR_TGPR]
|
| 667 |
#define msr_tlb env->msr[MSR_TLB]
|
| 668 |
#define msr_ce env->msr[MSR_CE]
|
| 669 |
#define msr_ile env->msr[MSR_ILE]
|
| 670 |
#define msr_ee env->msr[MSR_EE]
|
| 671 |
#define msr_pr env->msr[MSR_PR]
|
| 672 |
#define msr_fp env->msr[MSR_FP]
|
| 673 |
#define msr_me env->msr[MSR_ME]
|
| 674 |
#define msr_fe0 env->msr[MSR_FE0]
|
| 675 |
#define msr_se env->msr[MSR_SE]
|
| 676 |
#define msr_dwe env->msr[MSR_DWE]
|
| 677 |
#define msr_uble env->msr[MSR_UBLE]
|
| 678 |
#define msr_be env->msr[MSR_BE]
|
| 679 |
#define msr_de env->msr[MSR_DE]
|
| 680 |
#define msr_fe1 env->msr[MSR_FE1]
|
| 681 |
#define msr_al env->msr[MSR_AL]
|
| 682 |
#define msr_ip env->msr[MSR_IP]
|
| 683 |
#define msr_ir env->msr[MSR_IR]
|
| 684 |
#define msr_is env->msr[MSR_IS]
|
| 685 |
#define msr_dr env->msr[MSR_DR]
|
| 686 |
#define msr_ds env->msr[MSR_DS]
|
| 687 |
#define msr_pe env->msr[MSR_PE]
|
| 688 |
#define msr_ep env->msr[MSR_EP]
|
| 689 |
#define msr_px env->msr[MSR_PX]
|
| 690 |
#define msr_pmm env->msr[MSR_PMM]
|
| 691 |
#define msr_ri env->msr[MSR_RI]
|
| 692 |
#define msr_le env->msr[MSR_LE]
|
| 693 |
|
| 694 |
/*****************************************************************************/
|
| 695 |
/* The whole PowerPC CPU context */
|
| 696 |
struct CPUPPCState {
|
| 697 |
/* First are the most commonly used resources
|
| 698 |
* during translated code execution
|
| 699 |
*/
|
| 700 |
#if TARGET_GPR_BITS > HOST_LONG_BITS
|
| 701 |
/* temporary fixed-point registers
|
| 702 |
* used to emulate 64 bits target on 32 bits hosts
|
| 703 |
*/
|
| 704 |
ppc_gpr_t t0, t1, t2; |
| 705 |
#endif
|
| 706 |
ppc_avr_t t0_avr, t1_avr, t2_avr; |
| 707 |
|
| 708 |
/* general purpose registers */
|
| 709 |
ppc_gpr_t gpr[32];
|
| 710 |
/* LR */
|
| 711 |
target_ulong lr; |
| 712 |
/* CTR */
|
| 713 |
target_ulong ctr; |
| 714 |
/* condition register */
|
| 715 |
uint8_t crf[8];
|
| 716 |
/* XER */
|
| 717 |
/* XXX: We use only 5 fields, but we want to keep the structure aligned */
|
| 718 |
uint8_t xer[8];
|
| 719 |
/* Reservation address */
|
| 720 |
target_ulong reserve; |
| 721 |
|
| 722 |
/* Those ones are used in supervisor mode only */
|
| 723 |
/* machine state register */
|
| 724 |
uint8_t msr[64];
|
| 725 |
/* temporary general purpose registers */
|
| 726 |
ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ |
| 727 |
|
| 728 |
/* Floating point execution context */
|
| 729 |
/* temporary float registers */
|
| 730 |
float64 ft0; |
| 731 |
float64 ft1; |
| 732 |
float64 ft2; |
| 733 |
float_status fp_status; |
| 734 |
/* floating point registers */
|
| 735 |
float64 fpr[32];
|
| 736 |
/* floating point status and control register */
|
| 737 |
uint8_t fpscr[8];
|
| 738 |
|
| 739 |
CPU_COMMON |
| 740 |
|
| 741 |
int halted; /* TRUE if the CPU is in suspend state */ |
| 742 |
|
| 743 |
int access_type; /* when a memory exception occurs, the access |
| 744 |
type is stored here */
|
| 745 |
|
| 746 |
/* MMU context */
|
| 747 |
/* Address space register */
|
| 748 |
target_ulong asr; |
| 749 |
/* segment registers */
|
| 750 |
target_ulong sdr1; |
| 751 |
target_ulong sr[16];
|
| 752 |
/* BATs */
|
| 753 |
int nb_BATs;
|
| 754 |
target_ulong DBAT[2][8]; |
| 755 |
target_ulong IBAT[2][8]; |
| 756 |
|
| 757 |
/* Other registers */
|
| 758 |
/* Special purpose registers */
|
| 759 |
target_ulong spr[1024];
|
| 760 |
/* Altivec registers */
|
| 761 |
ppc_avr_t avr[32];
|
| 762 |
uint32_t vscr; |
| 763 |
/* SPE registers */
|
| 764 |
ppc_gpr_t spe_acc; |
| 765 |
float_status spe_status; |
| 766 |
uint32_t spe_fscr; |
| 767 |
|
| 768 |
/* Internal devices resources */
|
| 769 |
/* Time base and decrementer */
|
| 770 |
ppc_tb_t *tb_env; |
| 771 |
/* Device control registers */
|
| 772 |
ppc_dcr_t *dcr_env; |
| 773 |
|
| 774 |
/* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
|
| 775 |
int nb_tlb; /* Total number of TLB */ |
| 776 |
int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ |
| 777 |
int nb_ways; /* Number of ways in the TLB set */ |
| 778 |
int last_way; /* Last used way used to allocate TLB in a LRU way */ |
| 779 |
int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
| 780 |
int nb_pids; /* Number of available PID registers */ |
| 781 |
ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
|
| 782 |
/* 403 dedicated access protection registers */
|
| 783 |
target_ulong pb[4];
|
| 784 |
|
| 785 |
/* Those resources are used during exception processing */
|
| 786 |
/* CPU model definition */
|
| 787 |
uint64_t msr_mask; |
| 788 |
uint32_t flags; |
| 789 |
|
| 790 |
int exception_index;
|
| 791 |
int error_code;
|
| 792 |
int interrupt_request;
|
| 793 |
uint32_t pending_interrupts; |
| 794 |
#if !defined(CONFIG_USER_ONLY)
|
| 795 |
/* This is the IRQ controller, which is implementation dependant
|
| 796 |
* and only relevant when emulating a complete machine.
|
| 797 |
*/
|
| 798 |
uint32_t irq_input_state; |
| 799 |
void **irq_inputs;
|
| 800 |
#endif
|
| 801 |
|
| 802 |
/* Those resources are used only during code translation */
|
| 803 |
/* Next instruction pointer */
|
| 804 |
target_ulong nip; |
| 805 |
/* SPR translation callbacks */
|
| 806 |
ppc_spr_t spr_cb[1024];
|
| 807 |
/* opcode handlers */
|
| 808 |
opc_handler_t *opcodes[0x40];
|
| 809 |
|
| 810 |
/* Those resources are used only in Qemu core */
|
| 811 |
jmp_buf jmp_env; |
| 812 |
int user_mode_only; /* user mode only simulation */ |
| 813 |
uint32_t hflags; |
| 814 |
|
| 815 |
/* Power management */
|
| 816 |
int power_mode;
|
| 817 |
|
| 818 |
/* temporary hack to handle OSI calls (only used if non NULL) */
|
| 819 |
int (*osi_call)(struct CPUPPCState *env); |
| 820 |
}; |
| 821 |
|
| 822 |
/* Context used internally during MMU translations */
|
| 823 |
typedef struct mmu_ctx_t mmu_ctx_t; |
| 824 |
struct mmu_ctx_t {
|
| 825 |
target_phys_addr_t raddr; /* Real address */
|
| 826 |
int prot; /* Protection bits */ |
| 827 |
target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */ |
| 828 |
target_ulong ptem; /* Virtual segment ID | API */
|
| 829 |
int key; /* Access key */ |
| 830 |
}; |
| 831 |
|
| 832 |
/*****************************************************************************/
|
| 833 |
CPUPPCState *cpu_ppc_init (void);
|
| 834 |
int cpu_ppc_exec (CPUPPCState *s);
|
| 835 |
void cpu_ppc_close (CPUPPCState *s);
|
| 836 |
/* you can call this signal handler from your SIGBUS and SIGSEGV
|
| 837 |
signal handlers to inform the virtual CPU of exceptions. non zero
|
| 838 |
is returned if the signal was handled by the virtual CPU. */
|
| 839 |
int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
| 840 |
void *puc);
|
| 841 |
|
| 842 |
void do_interrupt (CPUPPCState *env);
|
| 843 |
void ppc_hw_interrupt (CPUPPCState *env);
|
| 844 |
void cpu_loop_exit (void); |
| 845 |
|
| 846 |
void dump_stack (CPUPPCState *env);
|
| 847 |
|
| 848 |
#if !defined(CONFIG_USER_ONLY)
|
| 849 |
target_ulong do_load_ibatu (CPUPPCState *env, int nr);
|
| 850 |
target_ulong do_load_ibatl (CPUPPCState *env, int nr);
|
| 851 |
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
| 852 |
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
| 853 |
target_ulong do_load_dbatu (CPUPPCState *env, int nr);
|
| 854 |
target_ulong do_load_dbatl (CPUPPCState *env, int nr);
|
| 855 |
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
| 856 |
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
| 857 |
target_ulong do_load_sdr1 (CPUPPCState *env); |
| 858 |
void do_store_sdr1 (CPUPPCState *env, target_ulong value);
|
| 859 |
#if defined(TARGET_PPC64)
|
| 860 |
target_ulong ppc_load_asr (CPUPPCState *env); |
| 861 |
void ppc_store_asr (CPUPPCState *env, target_ulong value);
|
| 862 |
#endif
|
| 863 |
target_ulong do_load_sr (CPUPPCState *env, int srnum);
|
| 864 |
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
| 865 |
#endif
|
| 866 |
uint32_t ppc_load_xer (CPUPPCState *env); |
| 867 |
void ppc_store_xer (CPUPPCState *env, uint32_t value);
|
| 868 |
target_ulong do_load_msr (CPUPPCState *env); |
| 869 |
void do_store_msr (CPUPPCState *env, target_ulong value);
|
| 870 |
void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
|
| 871 |
|
| 872 |
void do_compute_hflags (CPUPPCState *env);
|
| 873 |
void cpu_ppc_reset (void *opaque); |
| 874 |
CPUPPCState *cpu_ppc_init (void);
|
| 875 |
void cpu_ppc_close(CPUPPCState *env);
|
| 876 |
|
| 877 |
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def); |
| 878 |
int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
|
| 879 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 880 |
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
|
| 881 |
|
| 882 |
/* Time-base and decrementer management */
|
| 883 |
#ifndef NO_CPU_IO_DEFS
|
| 884 |
uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
| 885 |
uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
| 886 |
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
|
| 887 |
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
|
| 888 |
uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
| 889 |
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
|
| 890 |
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
| 891 |
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); |
| 892 |
#if !defined(CONFIG_USER_ONLY)
|
| 893 |
void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
|
| 894 |
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
|
| 895 |
target_ulong load_40x_pit (CPUPPCState *env); |
| 896 |
void store_40x_pit (CPUPPCState *env, target_ulong val);
|
| 897 |
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
|
| 898 |
void store_40x_sler (CPUPPCState *env, uint32_t val);
|
| 899 |
void store_booke_tcr (CPUPPCState *env, target_ulong val);
|
| 900 |
void store_booke_tsr (CPUPPCState *env, target_ulong val);
|
| 901 |
void ppc_tlb_invalidate_all (CPUPPCState *env);
|
| 902 |
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
|
| 903 |
#endif
|
| 904 |
#endif
|
| 905 |
|
| 906 |
/* Device control registers */
|
| 907 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); |
| 908 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); |
| 909 |
|
| 910 |
#define CPUState CPUPPCState
|
| 911 |
#define cpu_init cpu_ppc_init
|
| 912 |
#define cpu_exec cpu_ppc_exec
|
| 913 |
#define cpu_gen_code cpu_ppc_gen_code
|
| 914 |
#define cpu_signal_handler cpu_ppc_signal_handler
|
| 915 |
|
| 916 |
#include "cpu-all.h" |
| 917 |
|
| 918 |
/*****************************************************************************/
|
| 919 |
/* Registers definitions */
|
| 920 |
#define XER_SO 31 |
| 921 |
#define XER_OV 30 |
| 922 |
#define XER_CA 29 |
| 923 |
#define XER_CMP 8 |
| 924 |
#define XER_BC 0 |
| 925 |
#define xer_so env->xer[4] |
| 926 |
#define xer_ov env->xer[6] |
| 927 |
#define xer_ca env->xer[2] |
| 928 |
#define xer_cmp env->xer[1] |
| 929 |
#define xer_bc env->xer[0] |
| 930 |
|
| 931 |
/* SPR definitions */
|
| 932 |
#define SPR_MQ (0x000) |
| 933 |
#define SPR_XER (0x001) |
| 934 |
#define SPR_601_VRTCU (0x004) |
| 935 |
#define SPR_601_VRTCL (0x005) |
| 936 |
#define SPR_601_UDECR (0x006) |
| 937 |
#define SPR_LR (0x008) |
| 938 |
#define SPR_CTR (0x009) |
| 939 |
#define SPR_DSISR (0x012) |
| 940 |
#define SPR_DAR (0x013) |
| 941 |
#define SPR_601_RTCU (0x014) |
| 942 |
#define SPR_601_RTCL (0x015) |
| 943 |
#define SPR_DECR (0x016) |
| 944 |
#define SPR_SDR1 (0x019) |
| 945 |
#define SPR_SRR0 (0x01A) |
| 946 |
#define SPR_SRR1 (0x01B) |
| 947 |
#define SPR_BOOKE_PID (0x030) |
| 948 |
#define SPR_BOOKE_DECAR (0x036) |
| 949 |
#define SPR_BOOKE_CSRR0 (0x03A) |
| 950 |
#define SPR_BOOKE_CSRR1 (0x03B) |
| 951 |
#define SPR_BOOKE_DEAR (0x03D) |
| 952 |
#define SPR_BOOKE_ESR (0x03E) |
| 953 |
#define SPR_BOOKE_IVPR (0x03F) |
| 954 |
#define SPR_8xx_EIE (0x050) |
| 955 |
#define SPR_8xx_EID (0x051) |
| 956 |
#define SPR_8xx_NRE (0x052) |
| 957 |
#define SPR_58x_CMPA (0x090) |
| 958 |
#define SPR_58x_CMPB (0x091) |
| 959 |
#define SPR_58x_CMPC (0x092) |
| 960 |
#define SPR_58x_CMPD (0x093) |
| 961 |
#define SPR_58x_ICR (0x094) |
| 962 |
#define SPR_58x_DER (0x094) |
| 963 |
#define SPR_58x_COUNTA (0x096) |
| 964 |
#define SPR_58x_COUNTB (0x097) |
| 965 |
#define SPR_58x_CMPE (0x098) |
| 966 |
#define SPR_58x_CMPF (0x099) |
| 967 |
#define SPR_58x_CMPG (0x09A) |
| 968 |
#define SPR_58x_CMPH (0x09B) |
| 969 |
#define SPR_58x_LCTRL1 (0x09C) |
| 970 |
#define SPR_58x_LCTRL2 (0x09D) |
| 971 |
#define SPR_58x_ICTRL (0x09E) |
| 972 |
#define SPR_58x_BAR (0x09F) |
| 973 |
#define SPR_VRSAVE (0x100) |
| 974 |
#define SPR_USPRG0 (0x100) |
| 975 |
#define SPR_USPRG1 (0x101) |
| 976 |
#define SPR_USPRG2 (0x102) |
| 977 |
#define SPR_USPRG3 (0x103) |
| 978 |
#define SPR_USPRG4 (0x104) |
| 979 |
#define SPR_USPRG5 (0x105) |
| 980 |
#define SPR_USPRG6 (0x106) |
| 981 |
#define SPR_USPRG7 (0x107) |
| 982 |
#define SPR_VTBL (0x10C) |
| 983 |
#define SPR_VTBU (0x10D) |
| 984 |
#define SPR_SPRG0 (0x110) |
| 985 |
#define SPR_SPRG1 (0x111) |
| 986 |
#define SPR_SPRG2 (0x112) |
| 987 |
#define SPR_SPRG3 (0x113) |
| 988 |
#define SPR_SPRG4 (0x114) |
| 989 |
#define SPR_SCOMC (0x114) |
| 990 |
#define SPR_SPRG5 (0x115) |
| 991 |
#define SPR_SCOMD (0x115) |
| 992 |
#define SPR_SPRG6 (0x116) |
| 993 |
#define SPR_SPRG7 (0x117) |
| 994 |
#define SPR_ASR (0x118) |
| 995 |
#define SPR_EAR (0x11A) |
| 996 |
#define SPR_TBL (0x11C) |
| 997 |
#define SPR_TBU (0x11D) |
| 998 |
#define SPR_SVR (0x11E) |
| 999 |
#define SPR_BOOKE_PIR (0x11E) |
| 1000 |
#define SPR_PVR (0x11F) |
| 1001 |
#define SPR_HSPRG0 (0x130) |
| 1002 |
#define SPR_BOOKE_DBSR (0x130) |
| 1003 |
#define SPR_HSPRG1 (0x131) |
| 1004 |
#define SPR_BOOKE_DBCR0 (0x134) |
| 1005 |
#define SPR_IBCR (0x135) |
| 1006 |
#define SPR_BOOKE_DBCR1 (0x135) |
| 1007 |
#define SPR_DBCR (0x136) |
| 1008 |
#define SPR_HDEC (0x136) |
| 1009 |
#define SPR_BOOKE_DBCR2 (0x136) |
| 1010 |
#define SPR_HIOR (0x137) |
| 1011 |
#define SPR_MBAR (0x137) |
| 1012 |
#define SPR_RMOR (0x138) |
| 1013 |
#define SPR_BOOKE_IAC1 (0x138) |
| 1014 |
#define SPR_HRMOR (0x139) |
| 1015 |
#define SPR_BOOKE_IAC2 (0x139) |
| 1016 |
#define SPR_HSSR0 (0x13A) |
| 1017 |
#define SPR_BOOKE_IAC3 (0x13A) |
| 1018 |
#define SPR_HSSR1 (0x13B) |
| 1019 |
#define SPR_BOOKE_IAC4 (0x13B) |
| 1020 |
#define SPR_LPCR (0x13C) |
| 1021 |
#define SPR_BOOKE_DAC1 (0x13C) |
| 1022 |
#define SPR_LPIDR (0x13D) |
| 1023 |
#define SPR_DABR2 (0x13D) |
| 1024 |
#define SPR_BOOKE_DAC2 (0x13D) |
| 1025 |
#define SPR_BOOKE_DVC1 (0x13E) |
| 1026 |
#define SPR_BOOKE_DVC2 (0x13F) |
| 1027 |
#define SPR_BOOKE_TSR (0x150) |
| 1028 |
#define SPR_BOOKE_TCR (0x154) |
| 1029 |
#define SPR_BOOKE_IVOR0 (0x190) |
| 1030 |
#define SPR_BOOKE_IVOR1 (0x191) |
| 1031 |
#define SPR_BOOKE_IVOR2 (0x192) |
| 1032 |
#define SPR_BOOKE_IVOR3 (0x193) |
| 1033 |
#define SPR_BOOKE_IVOR4 (0x194) |
| 1034 |
#define SPR_BOOKE_IVOR5 (0x195) |
| 1035 |
#define SPR_BOOKE_IVOR6 (0x196) |
| 1036 |
#define SPR_BOOKE_IVOR7 (0x197) |
| 1037 |
#define SPR_BOOKE_IVOR8 (0x198) |
| 1038 |
#define SPR_BOOKE_IVOR9 (0x199) |
| 1039 |
#define SPR_BOOKE_IVOR10 (0x19A) |
| 1040 |
#define SPR_BOOKE_IVOR11 (0x19B) |
| 1041 |
#define SPR_BOOKE_IVOR12 (0x19C) |
| 1042 |
#define SPR_BOOKE_IVOR13 (0x19D) |
| 1043 |
#define SPR_BOOKE_IVOR14 (0x19E) |
| 1044 |
#define SPR_BOOKE_IVOR15 (0x19F) |
| 1045 |
#define SPR_E500_SPEFSCR (0x200) |
| 1046 |
#define SPR_E500_BBEAR (0x201) |
| 1047 |
#define SPR_E500_BBTAR (0x202) |
| 1048 |
#define SPR_BOOKE_ATBL (0x20E) |
| 1049 |
#define SPR_BOOKE_ATBU (0x20F) |
| 1050 |
#define SPR_IBAT0U (0x210) |
| 1051 |
#define SPR_BOOKE_IVOR32 (0x210) |
| 1052 |
#define SPR_IBAT0L (0x211) |
| 1053 |
#define SPR_BOOKE_IVOR33 (0x211) |
| 1054 |
#define SPR_IBAT1U (0x212) |
| 1055 |
#define SPR_BOOKE_IVOR34 (0x212) |
| 1056 |
#define SPR_IBAT1L (0x213) |
| 1057 |
#define SPR_BOOKE_IVOR35 (0x213) |
| 1058 |
#define SPR_IBAT2U (0x214) |
| 1059 |
#define SPR_BOOKE_IVOR36 (0x214) |
| 1060 |
#define SPR_IBAT2L (0x215) |
| 1061 |
#define SPR_E500_L1CFG0 (0x215) |
| 1062 |
#define SPR_BOOKE_IVOR37 (0x215) |
| 1063 |
#define SPR_IBAT3U (0x216) |
| 1064 |
#define SPR_E500_L1CFG1 (0x216) |
| 1065 |
#define SPR_IBAT3L (0x217) |
| 1066 |
#define SPR_DBAT0U (0x218) |
| 1067 |
#define SPR_DBAT0L (0x219) |
| 1068 |
#define SPR_DBAT1U (0x21A) |
| 1069 |
#define SPR_DBAT1L (0x21B) |
| 1070 |
#define SPR_DBAT2U (0x21C) |
| 1071 |
#define SPR_DBAT2L (0x21D) |
| 1072 |
#define SPR_DBAT3U (0x21E) |
| 1073 |
#define SPR_DBAT3L (0x21F) |
| 1074 |
#define SPR_IBAT4U (0x230) |
| 1075 |
#define SPR_IBAT4L (0x231) |
| 1076 |
#define SPR_IBAT5U (0x232) |
| 1077 |
#define SPR_IBAT5L (0x233) |
| 1078 |
#define SPR_IBAT6U (0x234) |
| 1079 |
#define SPR_IBAT6L (0x235) |
| 1080 |
#define SPR_IBAT7U (0x236) |
| 1081 |
#define SPR_IBAT7L (0x237) |
| 1082 |
#define SPR_DBAT4U (0x238) |
| 1083 |
#define SPR_DBAT4L (0x239) |
| 1084 |
#define SPR_DBAT5U (0x23A) |
| 1085 |
#define SPR_BOOKE_MCSRR0 (0x23A) |
| 1086 |
#define SPR_DBAT5L (0x23B) |
| 1087 |
#define SPR_BOOKE_MCSRR1 (0x23B) |
| 1088 |
#define SPR_DBAT6U (0x23C) |
| 1089 |
#define SPR_BOOKE_MCSR (0x23C) |
| 1090 |
#define SPR_DBAT6L (0x23D) |
| 1091 |
#define SPR_E500_MCAR (0x23D) |
| 1092 |
#define SPR_DBAT7U (0x23E) |
| 1093 |
#define SPR_BOOKE_DSRR0 (0x23E) |
| 1094 |
#define SPR_DBAT7L (0x23F) |
| 1095 |
#define SPR_BOOKE_DSRR1 (0x23F) |
| 1096 |
#define SPR_BOOKE_SPRG8 (0x25C) |
| 1097 |
#define SPR_BOOKE_SPRG9 (0x25D) |
| 1098 |
#define SPR_BOOKE_MAS0 (0x270) |
| 1099 |
#define SPR_BOOKE_MAS1 (0x271) |
| 1100 |
#define SPR_BOOKE_MAS2 (0x272) |
| 1101 |
#define SPR_BOOKE_MAS3 (0x273) |
| 1102 |
#define SPR_BOOKE_MAS4 (0x274) |
| 1103 |
#define SPR_BOOKE_MAS6 (0x276) |
| 1104 |
#define SPR_BOOKE_PID1 (0x279) |
| 1105 |
#define SPR_BOOKE_PID2 (0x27A) |
| 1106 |
#define SPR_BOOKE_TLB0CFG (0x2B0) |
| 1107 |
#define SPR_BOOKE_TLB1CFG (0x2B1) |
| 1108 |
#define SPR_BOOKE_TLB2CFG (0x2B2) |
| 1109 |
#define SPR_BOOKE_TLB3CFG (0x2B3) |
| 1110 |
#define SPR_BOOKE_EPR (0x2BE) |
| 1111 |
#define SPR_440_INV0 (0x370) |
| 1112 |
#define SPR_440_INV1 (0x371) |
| 1113 |
#define SPR_440_INV2 (0x372) |
| 1114 |
#define SPR_440_INV3 (0x373) |
| 1115 |
#define SPR_440_IVT0 (0x374) |
| 1116 |
#define SPR_440_IVT1 (0x375) |
| 1117 |
#define SPR_440_IVT2 (0x376) |
| 1118 |
#define SPR_440_IVT3 (0x377) |
| 1119 |
#define SPR_440_DNV0 (0x390) |
| 1120 |
#define SPR_440_DNV1 (0x391) |
| 1121 |
#define SPR_440_DNV2 (0x392) |
| 1122 |
#define SPR_440_DNV3 (0x393) |
| 1123 |
#define SPR_440_DVT0 (0x394) |
| 1124 |
#define SPR_440_DVT1 (0x395) |
| 1125 |
#define SPR_440_DVT2 (0x396) |
| 1126 |
#define SPR_440_DVT3 (0x397) |
| 1127 |
#define SPR_440_DVLIM (0x398) |
| 1128 |
#define SPR_440_IVLIM (0x399) |
| 1129 |
#define SPR_440_RSTCFG (0x39B) |
| 1130 |
#define SPR_BOOKE_DCBTRL (0x39C) |
| 1131 |
#define SPR_BOOKE_DCBTRH (0x39D) |
| 1132 |
#define SPR_BOOKE_ICBTRL (0x39E) |
| 1133 |
#define SPR_BOOKE_ICBTRH (0x39F) |
| 1134 |
#define SPR_UMMCR0 (0x3A8) |
| 1135 |
#define SPR_UPMC1 (0x3A9) |
| 1136 |
#define SPR_UPMC2 (0x3AA) |
| 1137 |
#define SPR_USIA (0x3AB) |
| 1138 |
#define SPR_UMMCR1 (0x3AC) |
| 1139 |
#define SPR_UPMC3 (0x3AD) |
| 1140 |
#define SPR_UPMC4 (0x3AE) |
| 1141 |
#define SPR_USDA (0x3AF) |
| 1142 |
#define SPR_40x_ZPR (0x3B0) |
| 1143 |
#define SPR_BOOKE_MAS7 (0x3B0) |
| 1144 |
#define SPR_40x_PID (0x3B1) |
| 1145 |
#define SPR_440_MMUCR (0x3B2) |
| 1146 |
#define SPR_4xx_CCR0 (0x3B3) |
| 1147 |
#define SPR_BOOKE_EPLC (0x3B3) |
| 1148 |
#define SPR_405_IAC3 (0x3B4) |
| 1149 |
#define SPR_BOOKE_EPSC (0x3B4) |
| 1150 |
#define SPR_405_IAC4 (0x3B5) |
| 1151 |
#define SPR_405_DVC1 (0x3B6) |
| 1152 |
#define SPR_405_DVC2 (0x3B7) |
| 1153 |
#define SPR_MMCR0 (0x3B8) |
| 1154 |
#define SPR_PMC1 (0x3B9) |
| 1155 |
#define SPR_40x_SGR (0x3B9) |
| 1156 |
#define SPR_PMC2 (0x3BA) |
| 1157 |
#define SPR_40x_DCWR (0x3BA) |
| 1158 |
#define SPR_SIA (0x3BB) |
| 1159 |
#define SPR_405_SLER (0x3BB) |
| 1160 |
#define SPR_MMCR1 (0x3BC) |
| 1161 |
#define SPR_405_SU0R (0x3BC) |
| 1162 |
#define SPR_PMC3 (0x3BD) |
| 1163 |
#define SPR_405_DBCR1 (0x3BD) |
| 1164 |
#define SPR_PMC4 (0x3BE) |
| 1165 |
#define SPR_SDA (0x3BF) |
| 1166 |
#define SPR_403_VTBL (0x3CC) |
| 1167 |
#define SPR_403_VTBU (0x3CD) |
| 1168 |
#define SPR_DMISS (0x3D0) |
| 1169 |
#define SPR_DCMP (0x3D1) |
| 1170 |
#define SPR_HASH1 (0x3D2) |
| 1171 |
#define SPR_HASH2 (0x3D3) |
| 1172 |
#define SPR_BOOKE_ICBDR (0x3D3) |
| 1173 |
#define SPR_IMISS (0x3D4) |
| 1174 |
#define SPR_40x_ESR (0x3D4) |
| 1175 |
#define SPR_ICMP (0x3D5) |
| 1176 |
#define SPR_40x_DEAR (0x3D5) |
| 1177 |
#define SPR_RPA (0x3D6) |
| 1178 |
#define SPR_40x_EVPR (0x3D6) |
| 1179 |
#define SPR_403_CDBCR (0x3D7) |
| 1180 |
#define SPR_TCR (0x3D8) |
| 1181 |
#define SPR_40x_TSR (0x3D8) |
| 1182 |
#define SPR_IBR (0x3DA) |
| 1183 |
#define SPR_40x_TCR (0x3DA) |
| 1184 |
#define SPR_ESASR (0x3DB) |
| 1185 |
#define SPR_40x_PIT (0x3DB) |
| 1186 |
#define SPR_403_TBL (0x3DC) |
| 1187 |
#define SPR_403_TBU (0x3DD) |
| 1188 |
#define SPR_SEBR (0x3DE) |
| 1189 |
#define SPR_40x_SRR2 (0x3DE) |
| 1190 |
#define SPR_SER (0x3DF) |
| 1191 |
#define SPR_40x_SRR3 (0x3DF) |
| 1192 |
#define SPR_HID0 (0x3F0) |
| 1193 |
#define SPR_40x_DBSR (0x3F0) |
| 1194 |
#define SPR_HID1 (0x3F1) |
| 1195 |
#define SPR_IABR (0x3F2) |
| 1196 |
#define SPR_40x_DBCR0 (0x3F2) |
| 1197 |
#define SPR_601_HID2 (0x3F2) |
| 1198 |
#define SPR_E500_L1CSR0 (0x3F2) |
| 1199 |
#define SPR_HID2 (0x3F3) |
| 1200 |
#define SPR_E500_L1CSR1 (0x3F3) |
| 1201 |
#define SPR_440_DBDR (0x3F3) |
| 1202 |
#define SPR_40x_IAC1 (0x3F4) |
| 1203 |
#define SPR_BOOKE_MMUCSR0 (0x3F4) |
| 1204 |
#define SPR_DABR (0x3F5) |
| 1205 |
#define DABR_MASK (~(target_ulong)0x7) |
| 1206 |
#define SPR_E500_BUCSR (0x3F5) |
| 1207 |
#define SPR_40x_IAC2 (0x3F5) |
| 1208 |
#define SPR_601_HID5 (0x3F5) |
| 1209 |
#define SPR_40x_DAC1 (0x3F6) |
| 1210 |
#define SPR_40x_DAC2 (0x3F7) |
| 1211 |
#define SPR_BOOKE_MMUCFG (0x3F7) |
| 1212 |
#define SPR_L2PM (0x3F8) |
| 1213 |
#define SPR_750_HID2 (0x3F8) |
| 1214 |
#define SPR_L2CR (0x3F9) |
| 1215 |
#define SPR_IABR2 (0x3FA) |
| 1216 |
#define SPR_40x_DCCR (0x3FA) |
| 1217 |
#define SPR_ICTC (0x3FB) |
| 1218 |
#define SPR_40x_ICCR (0x3FB) |
| 1219 |
#define SPR_THRM1 (0x3FC) |
| 1220 |
#define SPR_403_PBL1 (0x3FC) |
| 1221 |
#define SPR_SP (0x3FD) |
| 1222 |
#define SPR_THRM2 (0x3FD) |
| 1223 |
#define SPR_403_PBU1 (0x3FD) |
| 1224 |
#define SPR_LT (0x3FE) |
| 1225 |
#define SPR_THRM3 (0x3FE) |
| 1226 |
#define SPR_FPECR (0x3FE) |
| 1227 |
#define SPR_403_PBL2 (0x3FE) |
| 1228 |
#define SPR_PIR (0x3FF) |
| 1229 |
#define SPR_403_PBU2 (0x3FF) |
| 1230 |
#define SPR_601_HID15 (0x3FF) |
| 1231 |
#define SPR_E500_SVR (0x3FF) |
| 1232 |
|
| 1233 |
/*****************************************************************************/
|
| 1234 |
/* Memory access type :
|
| 1235 |
* may be needed for precise access rights control and precise exceptions.
|
| 1236 |
*/
|
| 1237 |
enum {
|
| 1238 |
/* 1 bit to define user level / supervisor access */
|
| 1239 |
ACCESS_USER = 0x00,
|
| 1240 |
ACCESS_SUPER = 0x01,
|
| 1241 |
/* Type of instruction that generated the access */
|
| 1242 |
ACCESS_CODE = 0x10, /* Code fetch access */ |
| 1243 |
ACCESS_INT = 0x20, /* Integer load/store access */ |
| 1244 |
ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
| 1245 |
ACCESS_RES = 0x40, /* load/store with reservation */ |
| 1246 |
ACCESS_EXT = 0x50, /* external access */ |
| 1247 |
ACCESS_CACHE = 0x60, /* Cache manipulation */ |
| 1248 |
}; |
| 1249 |
|
| 1250 |
/*****************************************************************************/
|
| 1251 |
/* Exceptions */
|
| 1252 |
#define EXCP_NONE -1 |
| 1253 |
/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
|
| 1254 |
#define EXCP_RESET 0x0100 /* System reset */ |
| 1255 |
#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */ |
| 1256 |
#define EXCP_DSI 0x0300 /* Data storage exception */ |
| 1257 |
#define EXCP_DSEG 0x0380 /* Data segment exception */ |
| 1258 |
#define EXCP_ISI 0x0400 /* Instruction storage exception */ |
| 1259 |
#define EXCP_ISEG 0x0480 /* Instruction segment exception */ |
| 1260 |
#define EXCP_EXTERNAL 0x0500 /* External interruption */ |
| 1261 |
#define EXCP_ALIGN 0x0600 /* Alignment exception */ |
| 1262 |
#define EXCP_PROGRAM 0x0700 /* Program exception */ |
| 1263 |
#define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */ |
| 1264 |
#define EXCP_DECR 0x0900 /* Decrementer exception */ |
| 1265 |
#define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */ |
| 1266 |
#define EXCP_SYSCALL 0x0C00 /* System call */ |
| 1267 |
#define EXCP_TRACE 0x0D00 /* Trace exception */ |
| 1268 |
#define EXCP_PERF 0x0F00 /* Performance monitor exception */ |
| 1269 |
/* Exceptions defined in PowerPC 32 bits programming environment manual */
|
| 1270 |
#define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */ |
| 1271 |
/* Implementation specific exceptions */
|
| 1272 |
/* 40x exceptions */
|
| 1273 |
#define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */ |
| 1274 |
#define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */ |
| 1275 |
#define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */ |
| 1276 |
#define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */ |
| 1277 |
#define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */ |
| 1278 |
#define EXCP_40x_DEBUG 0x2000 /* Debug exception */ |
| 1279 |
/* 405 specific exceptions */
|
| 1280 |
#define EXCP_405_APU 0x0F20 /* APU unavailable exception */ |
| 1281 |
/* TLB assist exceptions (602/603) */
|
| 1282 |
#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */ |
| 1283 |
#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */ |
| 1284 |
#define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */ |
| 1285 |
/* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
|
| 1286 |
#define EXCP_IABR 0x1300 /* Instruction address breakpoint */ |
| 1287 |
#define EXCP_SMI 0x1400 /* System management interrupt */ |
| 1288 |
/* Altivec related exceptions */
|
| 1289 |
#define EXCP_VPU 0x0F20 /* VPU unavailable exception */ |
| 1290 |
/* 601 specific exceptions */
|
| 1291 |
#define EXCP_601_IO 0x0600 /* IO error exception */ |
| 1292 |
#define EXCP_601_RUNM 0x2000 /* Run mode exception */ |
| 1293 |
/* 602 specific exceptions */
|
| 1294 |
#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */ |
| 1295 |
#define EXCP_602_EMUL 0x1600 /* Emulation trap exception */ |
| 1296 |
/* G2 specific exceptions */
|
| 1297 |
#define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */ |
| 1298 |
/* MPC740/745/750 & IBM 750 specific exceptions */
|
| 1299 |
#define EXCP_THRM 0x1700 /* Thermal management interrupt */ |
| 1300 |
/* 74xx specific exceptions */
|
| 1301 |
#define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */ |
| 1302 |
/* 970FX specific exceptions */
|
| 1303 |
#define EXCP_970_SOFTP 0x1500 /* Soft patch exception */ |
| 1304 |
#define EXCP_970_MAINT 0x1600 /* Maintenance exception */ |
| 1305 |
#define EXCP_970_THRM 0x1800 /* Thermal exception */ |
| 1306 |
#define EXCP_970_VPUA 0x1700 /* VPU assist exception */ |
| 1307 |
/* SPE related exceptions */
|
| 1308 |
#define EXCP_NO_SPE 0x0F20 /* SPE unavailable exception */ |
| 1309 |
/* End of exception vectors area */
|
| 1310 |
#define EXCP_PPC_MAX 0x4000 |
| 1311 |
/* Qemu exceptions: special cases we want to stop translation */
|
| 1312 |
#define EXCP_MTMSR 0x11000 /* mtmsr instruction: */ |
| 1313 |
/* may change privilege level */
|
| 1314 |
#define EXCP_BRANCH 0x11001 /* branch instruction */ |
| 1315 |
#define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */ |
| 1316 |
|
| 1317 |
/* Error codes */
|
| 1318 |
enum {
|
| 1319 |
/* Exception subtypes for EXCP_ALIGN */
|
| 1320 |
EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
| 1321 |
EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
| 1322 |
EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
| 1323 |
EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
| 1324 |
EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
| 1325 |
EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
| 1326 |
/* Exception subtypes for EXCP_PROGRAM */
|
| 1327 |
/* FP exceptions */
|
| 1328 |
EXCP_FP = 0x10,
|
| 1329 |
EXCP_FP_OX = 0x01, /* FP overflow */ |
| 1330 |
EXCP_FP_UX = 0x02, /* FP underflow */ |
| 1331 |
EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
| 1332 |
EXCP_FP_XX = 0x04, /* FP inexact */ |
| 1333 |
EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
| 1334 |
EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
| 1335 |
EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
| 1336 |
EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
| 1337 |
EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
| 1338 |
EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
| 1339 |
EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
| 1340 |
EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
| 1341 |
EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
| 1342 |
/* Invalid instruction */
|
| 1343 |
EXCP_INVAL = 0x20,
|
| 1344 |
EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
| 1345 |
EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
| 1346 |
EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
| 1347 |
EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
| 1348 |
/* Privileged instruction */
|
| 1349 |
EXCP_PRIV = 0x30,
|
| 1350 |
EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
| 1351 |
EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
| 1352 |
/* Trap */
|
| 1353 |
EXCP_TRAP = 0x40,
|
| 1354 |
}; |
| 1355 |
|
| 1356 |
/* Hardware interruption sources:
|
| 1357 |
* all those exception can be raised simulteaneously
|
| 1358 |
*/
|
| 1359 |
/* Input pins definitions */
|
| 1360 |
enum {
|
| 1361 |
/* 6xx bus input pins */
|
| 1362 |
PPC6xx_INPUT_HRESET = 0,
|
| 1363 |
PPC6xx_INPUT_SRESET = 1,
|
| 1364 |
PPC6xx_INPUT_CKSTP_IN = 2,
|
| 1365 |
PPC6xx_INPUT_MCP = 3,
|
| 1366 |
PPC6xx_INPUT_SMI = 4,
|
| 1367 |
PPC6xx_INPUT_INT = 5,
|
| 1368 |
}; |
| 1369 |
|
| 1370 |
enum {
|
| 1371 |
/* Embedded PowerPC input pins */
|
| 1372 |
PPCBookE_INPUT_HRESET = 0,
|
| 1373 |
PPCBookE_INPUT_SRESET = 1,
|
| 1374 |
PPCBookE_INPUT_CKSTP_IN = 2,
|
| 1375 |
PPCBookE_INPUT_MCP = 3,
|
| 1376 |
PPCBookE_INPUT_SMI = 4,
|
| 1377 |
PPCBookE_INPUT_INT = 5,
|
| 1378 |
PPCBookE_INPUT_CINT = 6,
|
| 1379 |
}; |
| 1380 |
|
| 1381 |
enum {
|
| 1382 |
/* PowerPC 405 input pins */
|
| 1383 |
PPC405_INPUT_RESET_CORE = 0,
|
| 1384 |
PPC405_INPUT_RESET_CHIP = 1,
|
| 1385 |
PPC405_INPUT_RESET_SYS = 2,
|
| 1386 |
PPC405_INPUT_CINT = 3,
|
| 1387 |
PPC405_INPUT_INT = 4,
|
| 1388 |
PPC405_INPUT_HALT = 5,
|
| 1389 |
PPC405_INPUT_DEBUG = 6,
|
| 1390 |
}; |
| 1391 |
|
| 1392 |
enum {
|
| 1393 |
/* PowerPC 970 input pins */
|
| 1394 |
PPC970_INPUT_HRESET = 0,
|
| 1395 |
PPC970_INPUT_SRESET = 1,
|
| 1396 |
PPC970_INPUT_CKSTP = 2,
|
| 1397 |
PPC970_INPUT_TBEN = 3,
|
| 1398 |
PPC970_INPUT_MCP = 4,
|
| 1399 |
PPC970_INPUT_INT = 5,
|
| 1400 |
PPC970_INPUT_THINT = 6,
|
| 1401 |
}; |
| 1402 |
|
| 1403 |
/* Hardware exceptions definitions */
|
| 1404 |
enum {
|
| 1405 |
/* External hardware exception sources */
|
| 1406 |
PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
| 1407 |
PPC_INTERRUPT_MCK = 1, /* Machine check exception */ |
| 1408 |
PPC_INTERRUPT_EXT = 2, /* External interrupt */ |
| 1409 |
PPC_INTERRUPT_SMI = 3, /* System management interrupt */ |
| 1410 |
PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */ |
| 1411 |
PPC_INTERRUPT_DEBUG = 5, /* External debug exception */ |
| 1412 |
PPC_INTERRUPT_THERM = 6, /* Thermal exception */ |
| 1413 |
/* Internal hardware exception sources */
|
| 1414 |
PPC_INTERRUPT_DECR = 7, /* Decrementer exception */ |
| 1415 |
PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */ |
| 1416 |
PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */ |
| 1417 |
PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */ |
| 1418 |
PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */ |
| 1419 |
}; |
| 1420 |
|
| 1421 |
/*****************************************************************************/
|
| 1422 |
|
| 1423 |
#endif /* !defined (__CPU_PPC_H__) */ |