root / hw / smc91c111.c @ 5ef98b47
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1 | 5fafdf24 | ths | /*
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2 | 80337b66 | bellard | * SMSC 91C111 Ethernet interface emulation
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3 | 80337b66 | bellard | *
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4 | 80337b66 | bellard | * Copyright (c) 2005 CodeSourcery, LLC.
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5 | 80337b66 | bellard | * Written by Paul Brook
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6 | 80337b66 | bellard | *
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7 | 80337b66 | bellard | * This code is licenced under the GPL
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8 | 80337b66 | bellard | */
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9 | 80337b66 | bellard | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "net.h" |
12 | 87ecb68b | pbrook | #include "devices.h" |
13 | 80337b66 | bellard | /* For crc32 */
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14 | 80337b66 | bellard | #include <zlib.h> |
15 | 80337b66 | bellard | |
16 | 80337b66 | bellard | /* Number of 2k memory pages available. */
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17 | 80337b66 | bellard | #define NUM_PACKETS 4 |
18 | 80337b66 | bellard | |
19 | 80337b66 | bellard | typedef struct { |
20 | 80337b66 | bellard | uint32_t base; |
21 | 80337b66 | bellard | VLANClientState *vc; |
22 | 80337b66 | bellard | uint16_t tcr; |
23 | 80337b66 | bellard | uint16_t rcr; |
24 | 80337b66 | bellard | uint16_t cr; |
25 | 80337b66 | bellard | uint16_t ctr; |
26 | 80337b66 | bellard | uint16_t gpr; |
27 | 80337b66 | bellard | uint16_t ptr; |
28 | 80337b66 | bellard | uint16_t ercv; |
29 | d537cf6c | pbrook | qemu_irq irq; |
30 | 80337b66 | bellard | int bank;
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31 | 80337b66 | bellard | int packet_num;
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32 | 80337b66 | bellard | int tx_alloc;
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33 | 80337b66 | bellard | /* Bitmask of allocated packets. */
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34 | 80337b66 | bellard | int allocated;
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35 | 80337b66 | bellard | int tx_fifo_len;
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36 | 80337b66 | bellard | int tx_fifo[NUM_PACKETS];
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37 | 80337b66 | bellard | int rx_fifo_len;
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38 | 80337b66 | bellard | int rx_fifo[NUM_PACKETS];
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39 | 5198cfd9 | bellard | int tx_fifo_done_len;
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40 | 5198cfd9 | bellard | int tx_fifo_done[NUM_PACKETS];
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41 | 80337b66 | bellard | /* Packet buffer memory. */
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42 | 5198cfd9 | bellard | uint8_t data[NUM_PACKETS][2048];
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43 | 80337b66 | bellard | uint8_t int_level; |
44 | 80337b66 | bellard | uint8_t int_mask; |
45 | 80337b66 | bellard | uint8_t macaddr[6];
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46 | 80337b66 | bellard | } smc91c111_state; |
47 | 80337b66 | bellard | |
48 | 80337b66 | bellard | #define RCR_SOFT_RST 0x8000 |
49 | 80337b66 | bellard | #define RCR_STRIP_CRC 0x0200 |
50 | 80337b66 | bellard | #define RCR_RXEN 0x0100 |
51 | 80337b66 | bellard | |
52 | 80337b66 | bellard | #define TCR_EPH_LOOP 0x2000 |
53 | 80337b66 | bellard | #define TCR_NOCRC 0x0100 |
54 | 80337b66 | bellard | #define TCR_PAD_EN 0x0080 |
55 | 80337b66 | bellard | #define TCR_FORCOL 0x0004 |
56 | 80337b66 | bellard | #define TCR_LOOP 0x0002 |
57 | 80337b66 | bellard | #define TCR_TXEN 0x0001 |
58 | 80337b66 | bellard | |
59 | 80337b66 | bellard | #define INT_MD 0x80 |
60 | 80337b66 | bellard | #define INT_ERCV 0x40 |
61 | 80337b66 | bellard | #define INT_EPH 0x20 |
62 | 80337b66 | bellard | #define INT_RX_OVRN 0x10 |
63 | 80337b66 | bellard | #define INT_ALLOC 0x08 |
64 | 80337b66 | bellard | #define INT_TX_EMPTY 0x04 |
65 | 80337b66 | bellard | #define INT_TX 0x02 |
66 | 80337b66 | bellard | #define INT_RCV 0x01 |
67 | 80337b66 | bellard | |
68 | 80337b66 | bellard | #define CTR_AUTO_RELEASE 0x0800 |
69 | 80337b66 | bellard | #define CTR_RELOAD 0x0002 |
70 | 80337b66 | bellard | #define CTR_STORE 0x0001 |
71 | 80337b66 | bellard | |
72 | 80337b66 | bellard | #define RS_ALGNERR 0x8000 |
73 | 80337b66 | bellard | #define RS_BRODCAST 0x4000 |
74 | 80337b66 | bellard | #define RS_BADCRC 0x2000 |
75 | 80337b66 | bellard | #define RS_ODDFRAME 0x1000 |
76 | 80337b66 | bellard | #define RS_TOOLONG 0x0800 |
77 | 80337b66 | bellard | #define RS_TOOSHORT 0x0400 |
78 | 80337b66 | bellard | #define RS_MULTICAST 0x0001 |
79 | 80337b66 | bellard | |
80 | 80337b66 | bellard | /* Update interrupt status. */
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81 | 80337b66 | bellard | static void smc91c111_update(smc91c111_state *s) |
82 | 80337b66 | bellard | { |
83 | 80337b66 | bellard | int level;
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84 | 80337b66 | bellard | |
85 | 80337b66 | bellard | if (s->tx_fifo_len == 0) |
86 | 80337b66 | bellard | s->int_level |= INT_TX_EMPTY; |
87 | 5198cfd9 | bellard | if (s->tx_fifo_done_len != 0) |
88 | 5198cfd9 | bellard | s->int_level |= INT_TX; |
89 | 80337b66 | bellard | level = (s->int_level & s->int_mask) != 0;
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90 | d537cf6c | pbrook | qemu_set_irq(s->irq, level); |
91 | 80337b66 | bellard | } |
92 | 80337b66 | bellard | |
93 | 80337b66 | bellard | /* Try to allocate a packet. Returns 0x80 on failure. */
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94 | 80337b66 | bellard | static int smc91c111_allocate_packet(smc91c111_state *s) |
95 | 80337b66 | bellard | { |
96 | 80337b66 | bellard | int i;
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97 | 80337b66 | bellard | if (s->allocated == (1 << NUM_PACKETS) - 1) { |
98 | 80337b66 | bellard | return 0x80; |
99 | 80337b66 | bellard | } |
100 | 80337b66 | bellard | |
101 | 80337b66 | bellard | for (i = 0; i < NUM_PACKETS; i++) { |
102 | 80337b66 | bellard | if ((s->allocated & (1 << i)) == 0) |
103 | 80337b66 | bellard | break;
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104 | 80337b66 | bellard | } |
105 | 80337b66 | bellard | s->allocated |= 1 << i;
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106 | 80337b66 | bellard | return i;
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107 | 80337b66 | bellard | } |
108 | 80337b66 | bellard | |
109 | 80337b66 | bellard | |
110 | 80337b66 | bellard | /* Process a pending TX allocate. */
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111 | 80337b66 | bellard | static void smc91c111_tx_alloc(smc91c111_state *s) |
112 | 80337b66 | bellard | { |
113 | 80337b66 | bellard | s->tx_alloc = smc91c111_allocate_packet(s); |
114 | 80337b66 | bellard | if (s->tx_alloc == 0x80) |
115 | 80337b66 | bellard | return;
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116 | 80337b66 | bellard | s->int_level |= INT_ALLOC; |
117 | 80337b66 | bellard | smc91c111_update(s); |
118 | 80337b66 | bellard | } |
119 | 80337b66 | bellard | |
120 | 80337b66 | bellard | /* Remove and item from the RX FIFO. */
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121 | 80337b66 | bellard | static void smc91c111_pop_rx_fifo(smc91c111_state *s) |
122 | 80337b66 | bellard | { |
123 | 80337b66 | bellard | int i;
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124 | 80337b66 | bellard | |
125 | 80337b66 | bellard | s->rx_fifo_len--; |
126 | 80337b66 | bellard | if (s->rx_fifo_len) {
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127 | 80337b66 | bellard | for (i = 0; i < s->rx_fifo_len; i++) |
128 | 80337b66 | bellard | s->rx_fifo[i] = s->rx_fifo[i + 1];
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129 | 80337b66 | bellard | s->int_level |= INT_RCV; |
130 | 80337b66 | bellard | } else {
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131 | 80337b66 | bellard | s->int_level &= ~INT_RCV; |
132 | 80337b66 | bellard | } |
133 | 80337b66 | bellard | smc91c111_update(s); |
134 | 80337b66 | bellard | } |
135 | 80337b66 | bellard | |
136 | 5198cfd9 | bellard | /* Remove an item from the TX completion FIFO. */
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137 | 5198cfd9 | bellard | static void smc91c111_pop_tx_fifo_done(smc91c111_state *s) |
138 | 5198cfd9 | bellard | { |
139 | 5198cfd9 | bellard | int i;
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140 | 5198cfd9 | bellard | |
141 | 5198cfd9 | bellard | if (s->tx_fifo_done_len == 0) |
142 | 5198cfd9 | bellard | return;
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143 | 5198cfd9 | bellard | s->tx_fifo_done_len--; |
144 | 5198cfd9 | bellard | for (i = 0; i < s->tx_fifo_done_len; i++) |
145 | 5198cfd9 | bellard | s->tx_fifo_done[i] = s->tx_fifo_done[i + 1];
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146 | 5198cfd9 | bellard | } |
147 | 5198cfd9 | bellard | |
148 | 80337b66 | bellard | /* Release the memory allocated to a packet. */
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149 | 80337b66 | bellard | static void smc91c111_release_packet(smc91c111_state *s, int packet) |
150 | 80337b66 | bellard | { |
151 | 80337b66 | bellard | s->allocated &= ~(1 << packet);
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152 | 80337b66 | bellard | if (s->tx_alloc == 0x80) |
153 | 80337b66 | bellard | smc91c111_tx_alloc(s); |
154 | 80337b66 | bellard | } |
155 | 80337b66 | bellard | |
156 | 80337b66 | bellard | /* Flush the TX FIFO. */
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157 | 80337b66 | bellard | static void smc91c111_do_tx(smc91c111_state *s) |
158 | 80337b66 | bellard | { |
159 | 80337b66 | bellard | int i;
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160 | 80337b66 | bellard | int len;
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161 | 80337b66 | bellard | int control;
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162 | 80337b66 | bellard | int add_crc;
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163 | 80337b66 | bellard | int packetnum;
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164 | 80337b66 | bellard | uint8_t *p; |
165 | 80337b66 | bellard | |
166 | 80337b66 | bellard | if ((s->tcr & TCR_TXEN) == 0) |
167 | 80337b66 | bellard | return;
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168 | 80337b66 | bellard | if (s->tx_fifo_len == 0) |
169 | 80337b66 | bellard | return;
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170 | 80337b66 | bellard | for (i = 0; i < s->tx_fifo_len; i++) { |
171 | 80337b66 | bellard | packetnum = s->tx_fifo[i]; |
172 | 80337b66 | bellard | p = &s->data[packetnum][0];
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173 | 80337b66 | bellard | /* Set status word. */
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174 | 80337b66 | bellard | *(p++) = 0x01;
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175 | 80337b66 | bellard | *(p++) = 0x40;
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176 | 80337b66 | bellard | len = *(p++); |
177 | 80337b66 | bellard | len |= ((int)*(p++)) << 8; |
178 | 80337b66 | bellard | len -= 6;
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179 | 80337b66 | bellard | control = p[len + 1];
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180 | 80337b66 | bellard | if (control & 0x20) |
181 | 80337b66 | bellard | len++; |
182 | 80337b66 | bellard | /* ??? This overwrites the data following the buffer.
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183 | 80337b66 | bellard | Don't know what real hardware does. */
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184 | 80337b66 | bellard | if (len < 64 && (s->tcr & TCR_PAD_EN)) { |
185 | 80337b66 | bellard | memset(p + len, 0, 64 - len); |
186 | 80337b66 | bellard | len = 64;
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187 | 80337b66 | bellard | } |
188 | 80337b66 | bellard | #if 0
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189 | 80337b66 | bellard | /* The card is supposed to append the CRC to the frame. However
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190 | 80337b66 | bellard | none of the other network traffic has the CRC appended.
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191 | 80337b66 | bellard | Suspect this is low level ethernet detail we don't need to worry
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192 | 80337b66 | bellard | about. */
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193 | 80337b66 | bellard | add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0;
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194 | 80337b66 | bellard | if (add_crc) {
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195 | 416b5d36 | ths | uint32_t crc;
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196 | 416b5d36 | ths | |
197 | 80337b66 | bellard | crc = crc32(~0, p, len);
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198 | 80337b66 | bellard | memcpy(p + len, &crc, 4);
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199 | 80337b66 | bellard | len += 4;
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200 | 80337b66 | bellard | }
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201 | 80337b66 | bellard | #else
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202 | 80337b66 | bellard | add_crc = 0;
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203 | 80337b66 | bellard | #endif
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204 | 80337b66 | bellard | if (s->ctr & CTR_AUTO_RELEASE)
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205 | 5198cfd9 | bellard | /* Race? */
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206 | 80337b66 | bellard | smc91c111_release_packet(s, packetnum); |
207 | 5198cfd9 | bellard | else if (s->tx_fifo_done_len < NUM_PACKETS) |
208 | 5198cfd9 | bellard | s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum; |
209 | 80337b66 | bellard | qemu_send_packet(s->vc, p, len); |
210 | 80337b66 | bellard | } |
211 | 80337b66 | bellard | s->tx_fifo_len = 0;
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212 | 80337b66 | bellard | smc91c111_update(s); |
213 | 80337b66 | bellard | } |
214 | 80337b66 | bellard | |
215 | 80337b66 | bellard | /* Add a packet to the TX FIFO. */
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216 | 80337b66 | bellard | static void smc91c111_queue_tx(smc91c111_state *s, int packet) |
217 | 80337b66 | bellard | { |
218 | 80337b66 | bellard | if (s->tx_fifo_len == NUM_PACKETS)
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219 | 80337b66 | bellard | return;
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220 | 80337b66 | bellard | s->tx_fifo[s->tx_fifo_len++] = packet; |
221 | 80337b66 | bellard | smc91c111_do_tx(s); |
222 | 80337b66 | bellard | } |
223 | 80337b66 | bellard | |
224 | 80337b66 | bellard | static void smc91c111_reset(smc91c111_state *s) |
225 | 80337b66 | bellard | { |
226 | 80337b66 | bellard | s->bank = 0;
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227 | 80337b66 | bellard | s->tx_fifo_len = 0;
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228 | 5198cfd9 | bellard | s->tx_fifo_done_len = 0;
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229 | 80337b66 | bellard | s->rx_fifo_len = 0;
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230 | 80337b66 | bellard | s->allocated = 0;
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231 | 80337b66 | bellard | s->packet_num = 0;
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232 | 80337b66 | bellard | s->tx_alloc = 0;
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233 | 80337b66 | bellard | s->tcr = 0;
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234 | 80337b66 | bellard | s->rcr = 0;
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235 | 80337b66 | bellard | s->cr = 0xa0b1;
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236 | 80337b66 | bellard | s->ctr = 0x1210;
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237 | 80337b66 | bellard | s->ptr = 0;
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238 | 80337b66 | bellard | s->ercv = 0x1f;
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239 | 80337b66 | bellard | s->int_level = INT_TX_EMPTY; |
240 | 80337b66 | bellard | s->int_mask = 0;
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241 | 80337b66 | bellard | smc91c111_update(s); |
242 | 80337b66 | bellard | } |
243 | 80337b66 | bellard | |
244 | 80337b66 | bellard | #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val |
245 | 80337b66 | bellard | #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8) |
246 | 80337b66 | bellard | |
247 | 80337b66 | bellard | static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, |
248 | 80337b66 | bellard | uint32_t value) |
249 | 80337b66 | bellard | { |
250 | 80337b66 | bellard | smc91c111_state *s = (smc91c111_state *)opaque; |
251 | 80337b66 | bellard | |
252 | 80337b66 | bellard | offset -= s->base; |
253 | 80337b66 | bellard | if (offset == 14) { |
254 | 80337b66 | bellard | s->bank = value; |
255 | 80337b66 | bellard | return;
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256 | 80337b66 | bellard | } |
257 | 80337b66 | bellard | if (offset == 15) |
258 | 80337b66 | bellard | return;
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259 | 80337b66 | bellard | switch (s->bank) {
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260 | 80337b66 | bellard | case 0: |
261 | 80337b66 | bellard | switch (offset) {
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262 | 80337b66 | bellard | case 0: /* TCR */ |
263 | 80337b66 | bellard | SET_LOW(tcr, value); |
264 | 80337b66 | bellard | return;
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265 | 80337b66 | bellard | case 1: |
266 | 80337b66 | bellard | SET_HIGH(tcr, value); |
267 | 80337b66 | bellard | return;
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268 | 80337b66 | bellard | case 4: /* RCR */ |
269 | 80337b66 | bellard | SET_LOW(rcr, value); |
270 | 80337b66 | bellard | return;
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271 | 80337b66 | bellard | case 5: |
272 | 80337b66 | bellard | SET_HIGH(rcr, value); |
273 | 80337b66 | bellard | if (s->rcr & RCR_SOFT_RST)
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274 | 80337b66 | bellard | smc91c111_reset(s); |
275 | 80337b66 | bellard | return;
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276 | 80337b66 | bellard | case 10: case 11: /* RPCR */ |
277 | 80337b66 | bellard | /* Ignored */
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278 | 80337b66 | bellard | return;
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279 | 80337b66 | bellard | } |
280 | 80337b66 | bellard | break;
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281 | 80337b66 | bellard | |
282 | 80337b66 | bellard | case 1: |
283 | 80337b66 | bellard | switch (offset) {
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284 | 80337b66 | bellard | case 0: /* CONFIG */ |
285 | 80337b66 | bellard | SET_LOW(cr, value); |
286 | 80337b66 | bellard | return;
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287 | 80337b66 | bellard | case 1: |
288 | 80337b66 | bellard | SET_HIGH(cr,value); |
289 | 80337b66 | bellard | return;
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290 | 80337b66 | bellard | case 2: case 3: /* BASE */ |
291 | 80337b66 | bellard | case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ |
292 | 80337b66 | bellard | /* Not implemented. */
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293 | 80337b66 | bellard | return;
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294 | 80337b66 | bellard | case 10: /* Genral Purpose */ |
295 | 80337b66 | bellard | SET_LOW(gpr, value); |
296 | 80337b66 | bellard | return;
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297 | 80337b66 | bellard | case 11: |
298 | 80337b66 | bellard | SET_HIGH(gpr, value); |
299 | 80337b66 | bellard | return;
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300 | 80337b66 | bellard | case 12: /* Control */ |
301 | 80337b66 | bellard | if (value & 1) |
302 | 80337b66 | bellard | fprintf(stderr, "smc91c111:EEPROM store not implemented\n");
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303 | 80337b66 | bellard | if (value & 2) |
304 | 80337b66 | bellard | fprintf(stderr, "smc91c111:EEPROM reload not implemented\n");
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305 | 80337b66 | bellard | value &= ~3;
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306 | 80337b66 | bellard | SET_LOW(ctr, value); |
307 | 80337b66 | bellard | return;
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308 | 80337b66 | bellard | case 13: |
309 | 80337b66 | bellard | SET_HIGH(ctr, value); |
310 | 80337b66 | bellard | return;
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311 | 80337b66 | bellard | } |
312 | 80337b66 | bellard | break;
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313 | 80337b66 | bellard | |
314 | 80337b66 | bellard | case 2: |
315 | 80337b66 | bellard | switch (offset) {
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316 | 80337b66 | bellard | case 0: /* MMU Command */ |
317 | 80337b66 | bellard | switch (value >> 5) { |
318 | 80337b66 | bellard | case 0: /* no-op */ |
319 | 80337b66 | bellard | break;
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320 | 80337b66 | bellard | case 1: /* Allocate for TX. */ |
321 | 80337b66 | bellard | s->tx_alloc = 0x80;
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322 | 80337b66 | bellard | s->int_level &= ~INT_ALLOC; |
323 | 80337b66 | bellard | smc91c111_update(s); |
324 | 80337b66 | bellard | smc91c111_tx_alloc(s); |
325 | 80337b66 | bellard | break;
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326 | 80337b66 | bellard | case 2: /* Reset MMU. */ |
327 | 80337b66 | bellard | s->allocated = 0;
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328 | 80337b66 | bellard | s->tx_fifo_len = 0;
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329 | 5198cfd9 | bellard | s->tx_fifo_done_len = 0;
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330 | 80337b66 | bellard | s->rx_fifo_len = 0;
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331 | 80337b66 | bellard | s->tx_alloc = 0;
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332 | 80337b66 | bellard | break;
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333 | 80337b66 | bellard | case 3: /* Remove from RX FIFO. */ |
334 | 80337b66 | bellard | smc91c111_pop_rx_fifo(s); |
335 | 80337b66 | bellard | break;
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336 | 80337b66 | bellard | case 4: /* Remove from RX FIFO and release. */ |
337 | 80337b66 | bellard | if (s->rx_fifo_len > 0) { |
338 | 80337b66 | bellard | smc91c111_release_packet(s, s->rx_fifo[0]);
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339 | 80337b66 | bellard | } |
340 | 80337b66 | bellard | smc91c111_pop_rx_fifo(s); |
341 | 80337b66 | bellard | break;
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342 | 80337b66 | bellard | case 5: /* Release. */ |
343 | 80337b66 | bellard | smc91c111_release_packet(s, s->packet_num); |
344 | 80337b66 | bellard | break;
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345 | 80337b66 | bellard | case 6: /* Add to TX FIFO. */ |
346 | 80337b66 | bellard | smc91c111_queue_tx(s, s->packet_num); |
347 | 80337b66 | bellard | break;
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348 | 80337b66 | bellard | case 7: /* Reset TX FIFO. */ |
349 | 80337b66 | bellard | s->tx_fifo_len = 0;
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350 | 5198cfd9 | bellard | s->tx_fifo_done_len = 0;
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351 | 80337b66 | bellard | break;
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352 | 80337b66 | bellard | } |
353 | 80337b66 | bellard | return;
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354 | 80337b66 | bellard | case 1: |
355 | 80337b66 | bellard | /* Ignore. */
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356 | 80337b66 | bellard | return;
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357 | 80337b66 | bellard | case 2: /* Packet Number Register */ |
358 | 80337b66 | bellard | s->packet_num = value; |
359 | 80337b66 | bellard | return;
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360 | 80337b66 | bellard | case 3: case 4: case 5: |
361 | 80337b66 | bellard | /* Should be readonly, but linux writes to them anyway. Ignore. */
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362 | 80337b66 | bellard | return;
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363 | 80337b66 | bellard | case 6: /* Pointer */ |
364 | 80337b66 | bellard | SET_LOW(ptr, value); |
365 | 80337b66 | bellard | return;
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366 | 80337b66 | bellard | case 7: |
367 | 80337b66 | bellard | SET_HIGH(ptr, value); |
368 | 80337b66 | bellard | return;
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369 | 80337b66 | bellard | case 8: case 9: case 10: case 11: /* Data */ |
370 | 80337b66 | bellard | { |
371 | 80337b66 | bellard | int p;
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372 | 80337b66 | bellard | int n;
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373 | 80337b66 | bellard | |
374 | 80337b66 | bellard | if (s->ptr & 0x8000) |
375 | 80337b66 | bellard | n = s->rx_fifo[0];
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376 | 80337b66 | bellard | else
|
377 | 80337b66 | bellard | n = s->packet_num; |
378 | 80337b66 | bellard | p = s->ptr & 0x07ff;
|
379 | 80337b66 | bellard | if (s->ptr & 0x4000) { |
380 | 80337b66 | bellard | s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x7ff); |
381 | 80337b66 | bellard | } else {
|
382 | 80337b66 | bellard | p += (offset & 3);
|
383 | 80337b66 | bellard | } |
384 | 80337b66 | bellard | s->data[n][p] = value; |
385 | 80337b66 | bellard | } |
386 | 80337b66 | bellard | return;
|
387 | 80337b66 | bellard | case 12: /* Interrupt ACK. */ |
388 | 80337b66 | bellard | s->int_level &= ~(value & 0xd6);
|
389 | 5198cfd9 | bellard | if (value & INT_TX)
|
390 | 5198cfd9 | bellard | smc91c111_pop_tx_fifo_done(s); |
391 | 80337b66 | bellard | smc91c111_update(s); |
392 | 80337b66 | bellard | return;
|
393 | 80337b66 | bellard | case 13: /* Interrupt mask. */ |
394 | 80337b66 | bellard | s->int_mask = value; |
395 | 80337b66 | bellard | smc91c111_update(s); |
396 | 80337b66 | bellard | return;
|
397 | 80337b66 | bellard | } |
398 | 80337b66 | bellard | break;;
|
399 | 80337b66 | bellard | |
400 | 80337b66 | bellard | case 3: |
401 | 80337b66 | bellard | switch (offset) {
|
402 | 80337b66 | bellard | case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: |
403 | 80337b66 | bellard | /* Multicast table. */
|
404 | 80337b66 | bellard | /* Not implemented. */
|
405 | 80337b66 | bellard | return;
|
406 | 80337b66 | bellard | case 8: case 9: /* Management Interface. */ |
407 | 80337b66 | bellard | /* Not implemented. */
|
408 | 80337b66 | bellard | return;
|
409 | 80337b66 | bellard | case 12: /* Early receive. */ |
410 | 80337b66 | bellard | s->ercv = value & 0x1f;
|
411 | 80337b66 | bellard | case 13: |
412 | 80337b66 | bellard | /* Ignore. */
|
413 | 80337b66 | bellard | return;
|
414 | 80337b66 | bellard | } |
415 | 80337b66 | bellard | break;
|
416 | 80337b66 | bellard | } |
417 | 80337b66 | bellard | cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n",
|
418 | 4d1165fa | pbrook | s->bank, (int)offset);
|
419 | 80337b66 | bellard | } |
420 | 80337b66 | bellard | |
421 | 80337b66 | bellard | static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) |
422 | 80337b66 | bellard | { |
423 | 80337b66 | bellard | smc91c111_state *s = (smc91c111_state *)opaque; |
424 | 80337b66 | bellard | |
425 | 80337b66 | bellard | offset -= s->base; |
426 | 80337b66 | bellard | if (offset == 14) { |
427 | 80337b66 | bellard | return s->bank;
|
428 | 80337b66 | bellard | } |
429 | 80337b66 | bellard | if (offset == 15) |
430 | 80337b66 | bellard | return 0x33; |
431 | 80337b66 | bellard | switch (s->bank) {
|
432 | 80337b66 | bellard | case 0: |
433 | 80337b66 | bellard | switch (offset) {
|
434 | 80337b66 | bellard | case 0: /* TCR */ |
435 | 80337b66 | bellard | return s->tcr & 0xff; |
436 | 80337b66 | bellard | case 1: |
437 | 80337b66 | bellard | return s->tcr >> 8; |
438 | 80337b66 | bellard | case 2: /* EPH Status */ |
439 | 80337b66 | bellard | return 0; |
440 | 80337b66 | bellard | case 3: |
441 | 80337b66 | bellard | return 0x40; |
442 | 80337b66 | bellard | case 4: /* RCR */ |
443 | 80337b66 | bellard | return s->rcr & 0xff; |
444 | 80337b66 | bellard | case 5: |
445 | 80337b66 | bellard | return s->rcr >> 8; |
446 | 80337b66 | bellard | case 6: /* Counter */ |
447 | 80337b66 | bellard | case 7: |
448 | 80337b66 | bellard | /* Not implemented. */
|
449 | 80337b66 | bellard | return 0; |
450 | 687fa640 | ths | case 8: /* Memory size. */ |
451 | 687fa640 | ths | return NUM_PACKETS;
|
452 | 687fa640 | ths | case 9: /* Free memory available. */ |
453 | 80337b66 | bellard | { |
454 | 80337b66 | bellard | int i;
|
455 | 80337b66 | bellard | int n;
|
456 | 80337b66 | bellard | n = 0;
|
457 | 80337b66 | bellard | for (i = 0; i < NUM_PACKETS; i++) { |
458 | 80337b66 | bellard | if (s->allocated & (1 << i)) |
459 | 80337b66 | bellard | n++; |
460 | 80337b66 | bellard | } |
461 | 80337b66 | bellard | return n;
|
462 | 80337b66 | bellard | } |
463 | 80337b66 | bellard | case 10: case 11: /* RPCR */ |
464 | 80337b66 | bellard | /* Not implemented. */
|
465 | 80337b66 | bellard | return 0; |
466 | 80337b66 | bellard | } |
467 | 80337b66 | bellard | break;
|
468 | 80337b66 | bellard | |
469 | 80337b66 | bellard | case 1: |
470 | 80337b66 | bellard | switch (offset) {
|
471 | 80337b66 | bellard | case 0: /* CONFIG */ |
472 | 80337b66 | bellard | return s->cr & 0xff; |
473 | 80337b66 | bellard | case 1: |
474 | 80337b66 | bellard | return s->cr >> 8; |
475 | 80337b66 | bellard | case 2: case 3: /* BASE */ |
476 | 80337b66 | bellard | /* Not implemented. */
|
477 | 80337b66 | bellard | return 0; |
478 | 80337b66 | bellard | case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ |
479 | 80337b66 | bellard | return s->macaddr[offset - 4]; |
480 | 80337b66 | bellard | case 10: /* General Purpose */ |
481 | 80337b66 | bellard | return s->gpr & 0xff; |
482 | 80337b66 | bellard | case 11: |
483 | 80337b66 | bellard | return s->gpr >> 8; |
484 | 80337b66 | bellard | case 12: /* Control */ |
485 | 80337b66 | bellard | return s->ctr & 0xff; |
486 | 80337b66 | bellard | case 13: |
487 | 80337b66 | bellard | return s->ctr >> 8; |
488 | 80337b66 | bellard | } |
489 | 80337b66 | bellard | break;
|
490 | 80337b66 | bellard | |
491 | 80337b66 | bellard | case 2: |
492 | 80337b66 | bellard | switch (offset) {
|
493 | 80337b66 | bellard | case 0: case 1: /* MMUCR Busy bit. */ |
494 | 80337b66 | bellard | return 0; |
495 | 80337b66 | bellard | case 2: /* Packet Number. */ |
496 | 80337b66 | bellard | return s->packet_num;
|
497 | 80337b66 | bellard | case 3: /* Allocation Result. */ |
498 | 80337b66 | bellard | return s->tx_alloc;
|
499 | 80337b66 | bellard | case 4: /* TX FIFO */ |
500 | 5198cfd9 | bellard | if (s->tx_fifo_done_len == 0) |
501 | 80337b66 | bellard | return 0x80; |
502 | 80337b66 | bellard | else
|
503 | 5198cfd9 | bellard | return s->tx_fifo_done[0]; |
504 | 80337b66 | bellard | case 5: /* RX FIFO */ |
505 | 80337b66 | bellard | if (s->rx_fifo_len == 0) |
506 | 80337b66 | bellard | return 0x80; |
507 | 80337b66 | bellard | else
|
508 | 80337b66 | bellard | return s->rx_fifo[0]; |
509 | 80337b66 | bellard | case 6: /* Pointer */ |
510 | 80337b66 | bellard | return s->ptr & 0xff; |
511 | 80337b66 | bellard | case 7: |
512 | 80337b66 | bellard | return (s->ptr >> 8) & 0xf7; |
513 | 80337b66 | bellard | case 8: case 9: case 10: case 11: /* Data */ |
514 | 80337b66 | bellard | { |
515 | 80337b66 | bellard | int p;
|
516 | 80337b66 | bellard | int n;
|
517 | 80337b66 | bellard | |
518 | 80337b66 | bellard | if (s->ptr & 0x8000) |
519 | 80337b66 | bellard | n = s->rx_fifo[0];
|
520 | 80337b66 | bellard | else
|
521 | 80337b66 | bellard | n = s->packet_num; |
522 | 80337b66 | bellard | p = s->ptr & 0x07ff;
|
523 | 80337b66 | bellard | if (s->ptr & 0x4000) { |
524 | 80337b66 | bellard | s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x07ff); |
525 | 80337b66 | bellard | } else {
|
526 | 80337b66 | bellard | p += (offset & 3);
|
527 | 80337b66 | bellard | } |
528 | 80337b66 | bellard | return s->data[n][p];
|
529 | 80337b66 | bellard | } |
530 | 80337b66 | bellard | case 12: /* Interrupt status. */ |
531 | 80337b66 | bellard | return s->int_level;
|
532 | 80337b66 | bellard | case 13: /* Interrupt mask. */ |
533 | 80337b66 | bellard | return s->int_mask;
|
534 | 80337b66 | bellard | } |
535 | 80337b66 | bellard | break;
|
536 | 80337b66 | bellard | |
537 | 80337b66 | bellard | case 3: |
538 | 80337b66 | bellard | switch (offset) {
|
539 | 80337b66 | bellard | case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: |
540 | 80337b66 | bellard | /* Multicast table. */
|
541 | 80337b66 | bellard | /* Not implemented. */
|
542 | 80337b66 | bellard | return 0; |
543 | 80337b66 | bellard | case 8: /* Management Interface. */ |
544 | 80337b66 | bellard | /* Not implemented. */
|
545 | 80337b66 | bellard | return 0x30; |
546 | 80337b66 | bellard | case 9: |
547 | 80337b66 | bellard | return 0x33; |
548 | 80337b66 | bellard | case 10: /* Revision. */ |
549 | 80337b66 | bellard | return 0x91; |
550 | 80337b66 | bellard | case 11: |
551 | 80337b66 | bellard | return 0x33; |
552 | 80337b66 | bellard | case 12: |
553 | 80337b66 | bellard | return s->ercv;
|
554 | 80337b66 | bellard | case 13: |
555 | 80337b66 | bellard | return 0; |
556 | 80337b66 | bellard | } |
557 | 80337b66 | bellard | break;
|
558 | 80337b66 | bellard | } |
559 | 80337b66 | bellard | cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n",
|
560 | 4d1165fa | pbrook | s->bank, (int)offset);
|
561 | 80337b66 | bellard | return 0; |
562 | 80337b66 | bellard | } |
563 | 80337b66 | bellard | |
564 | 80337b66 | bellard | static void smc91c111_writew(void *opaque, target_phys_addr_t offset, |
565 | 80337b66 | bellard | uint32_t value) |
566 | 80337b66 | bellard | { |
567 | 80337b66 | bellard | smc91c111_writeb(opaque, offset, value & 0xff);
|
568 | 80337b66 | bellard | smc91c111_writeb(opaque, offset + 1, value >> 8); |
569 | 80337b66 | bellard | } |
570 | 80337b66 | bellard | |
571 | 80337b66 | bellard | static void smc91c111_writel(void *opaque, target_phys_addr_t offset, |
572 | 80337b66 | bellard | uint32_t value) |
573 | 80337b66 | bellard | { |
574 | 80337b66 | bellard | smc91c111_state *s = (smc91c111_state *)opaque; |
575 | 80337b66 | bellard | /* 32-bit writes to offset 0xc only actually write to the bank select
|
576 | 80337b66 | bellard | register (offset 0xe) */
|
577 | 80337b66 | bellard | if (offset != s->base + 0xc) |
578 | 80337b66 | bellard | smc91c111_writew(opaque, offset, value & 0xffff);
|
579 | 80337b66 | bellard | smc91c111_writew(opaque, offset + 2, value >> 16); |
580 | 80337b66 | bellard | } |
581 | 80337b66 | bellard | |
582 | 80337b66 | bellard | static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset) |
583 | 80337b66 | bellard | { |
584 | 80337b66 | bellard | uint32_t val; |
585 | 80337b66 | bellard | val = smc91c111_readb(opaque, offset); |
586 | 80337b66 | bellard | val |= smc91c111_readb(opaque, offset + 1) << 8; |
587 | 80337b66 | bellard | return val;
|
588 | 80337b66 | bellard | } |
589 | 80337b66 | bellard | |
590 | 80337b66 | bellard | static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset) |
591 | 80337b66 | bellard | { |
592 | 80337b66 | bellard | uint32_t val; |
593 | 80337b66 | bellard | val = smc91c111_readw(opaque, offset); |
594 | 80337b66 | bellard | val |= smc91c111_readw(opaque, offset + 2) << 16; |
595 | 80337b66 | bellard | return val;
|
596 | 80337b66 | bellard | } |
597 | 80337b66 | bellard | |
598 | d861b05e | pbrook | static int smc91c111_can_receive(void *opaque) |
599 | d861b05e | pbrook | { |
600 | d861b05e | pbrook | smc91c111_state *s = (smc91c111_state *)opaque; |
601 | d861b05e | pbrook | |
602 | d861b05e | pbrook | if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) |
603 | d861b05e | pbrook | return 1; |
604 | d861b05e | pbrook | if (s->allocated == (1 << NUM_PACKETS) - 1) |
605 | d861b05e | pbrook | return 0; |
606 | d861b05e | pbrook | return 1; |
607 | d861b05e | pbrook | } |
608 | d861b05e | pbrook | |
609 | 80337b66 | bellard | static void smc91c111_receive(void *opaque, const uint8_t *buf, int size) |
610 | 80337b66 | bellard | { |
611 | 80337b66 | bellard | smc91c111_state *s = (smc91c111_state *)opaque; |
612 | 80337b66 | bellard | int status;
|
613 | 80337b66 | bellard | int packetsize;
|
614 | 80337b66 | bellard | uint32_t crc; |
615 | 80337b66 | bellard | int packetnum;
|
616 | 80337b66 | bellard | uint8_t *p; |
617 | 80337b66 | bellard | |
618 | 80337b66 | bellard | if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) |
619 | 80337b66 | bellard | return;
|
620 | 9f083493 | ths | /* Short packets are padded with zeros. Receiving a packet
|
621 | 80337b66 | bellard | < 64 bytes long is considered an error condition. */
|
622 | 80337b66 | bellard | if (size < 64) |
623 | 80337b66 | bellard | packetsize = 64;
|
624 | 80337b66 | bellard | else
|
625 | 80337b66 | bellard | packetsize = (size & ~1);
|
626 | 80337b66 | bellard | packetsize += 6;
|
627 | 80337b66 | bellard | crc = (s->rcr & RCR_STRIP_CRC) == 0;
|
628 | 80337b66 | bellard | if (crc)
|
629 | 80337b66 | bellard | packetsize += 4;
|
630 | 80337b66 | bellard | /* TODO: Flag overrun and receive errors. */
|
631 | 80337b66 | bellard | if (packetsize > 2048) |
632 | 80337b66 | bellard | return;
|
633 | 80337b66 | bellard | packetnum = smc91c111_allocate_packet(s); |
634 | 80337b66 | bellard | if (packetnum == 0x80) |
635 | 80337b66 | bellard | return;
|
636 | 80337b66 | bellard | s->rx_fifo[s->rx_fifo_len++] = packetnum; |
637 | 80337b66 | bellard | |
638 | 80337b66 | bellard | p = &s->data[packetnum][0];
|
639 | 80337b66 | bellard | /* ??? Multicast packets? */
|
640 | 80337b66 | bellard | status = 0;
|
641 | 80337b66 | bellard | if (size > 1518) |
642 | 80337b66 | bellard | status |= RS_TOOLONG; |
643 | 80337b66 | bellard | if (size & 1) |
644 | 80337b66 | bellard | status |= RS_ODDFRAME; |
645 | 80337b66 | bellard | *(p++) = status & 0xff;
|
646 | 80337b66 | bellard | *(p++) = status >> 8;
|
647 | 80337b66 | bellard | *(p++) = packetsize & 0xff;
|
648 | 80337b66 | bellard | *(p++) = packetsize >> 8;
|
649 | 80337b66 | bellard | memcpy(p, buf, size & ~1);
|
650 | 80337b66 | bellard | p += (size & ~1);
|
651 | 80337b66 | bellard | /* Pad short packets. */
|
652 | 80337b66 | bellard | if (size < 64) { |
653 | 80337b66 | bellard | int pad;
|
654 | 3b46e624 | ths | |
655 | 80337b66 | bellard | if (size & 1) |
656 | 80337b66 | bellard | *(p++) = buf[size - 1];
|
657 | 80337b66 | bellard | pad = 64 - size;
|
658 | 80337b66 | bellard | memset(p, 0, pad);
|
659 | 80337b66 | bellard | p += pad; |
660 | 80337b66 | bellard | size = 64;
|
661 | 80337b66 | bellard | } |
662 | 80337b66 | bellard | /* It's not clear if the CRC should go before or after the last byte in
|
663 | 80337b66 | bellard | odd sized packets. Linux disables the CRC, so that's no help.
|
664 | 80337b66 | bellard | The pictures in the documentation show the CRC aligned on a 16-bit
|
665 | 80337b66 | bellard | boundary before the last odd byte, so that's what we do. */
|
666 | 80337b66 | bellard | if (crc) {
|
667 | 80337b66 | bellard | crc = crc32(~0, buf, size);
|
668 | 80337b66 | bellard | *(p++) = crc & 0xff; crc >>= 8; |
669 | 80337b66 | bellard | *(p++) = crc & 0xff; crc >>= 8; |
670 | 80337b66 | bellard | *(p++) = crc & 0xff; crc >>= 8; |
671 | 80337b66 | bellard | *(p++) = crc & 0xff; crc >>= 8; |
672 | 80337b66 | bellard | } |
673 | 80337b66 | bellard | if (size & 1) { |
674 | 80337b66 | bellard | *(p++) = buf[size - 1];
|
675 | 80337b66 | bellard | *(p++) = 0x60;
|
676 | 80337b66 | bellard | } else {
|
677 | 80337b66 | bellard | *(p++) = 0;
|
678 | 80337b66 | bellard | *(p++) = 0x40;
|
679 | 80337b66 | bellard | } |
680 | 80337b66 | bellard | /* TODO: Raise early RX interrupt? */
|
681 | 80337b66 | bellard | s->int_level |= INT_RCV; |
682 | 80337b66 | bellard | smc91c111_update(s); |
683 | 80337b66 | bellard | } |
684 | 80337b66 | bellard | |
685 | 80337b66 | bellard | static CPUReadMemoryFunc *smc91c111_readfn[] = {
|
686 | 80337b66 | bellard | smc91c111_readb, |
687 | 80337b66 | bellard | smc91c111_readw, |
688 | 80337b66 | bellard | smc91c111_readl |
689 | 80337b66 | bellard | }; |
690 | 80337b66 | bellard | |
691 | 80337b66 | bellard | static CPUWriteMemoryFunc *smc91c111_writefn[] = {
|
692 | 80337b66 | bellard | smc91c111_writeb, |
693 | 80337b66 | bellard | smc91c111_writew, |
694 | 80337b66 | bellard | smc91c111_writel |
695 | 80337b66 | bellard | }; |
696 | 80337b66 | bellard | |
697 | d537cf6c | pbrook | void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
|
698 | 80337b66 | bellard | { |
699 | 80337b66 | bellard | smc91c111_state *s; |
700 | 80337b66 | bellard | int iomemtype;
|
701 | 80337b66 | bellard | |
702 | 80337b66 | bellard | s = (smc91c111_state *)qemu_mallocz(sizeof(smc91c111_state));
|
703 | 80337b66 | bellard | iomemtype = cpu_register_io_memory(0, smc91c111_readfn,
|
704 | 80337b66 | bellard | smc91c111_writefn, s); |
705 | 80337b66 | bellard | cpu_register_physical_memory(base, 16, iomemtype);
|
706 | 80337b66 | bellard | s->base = base; |
707 | 80337b66 | bellard | s->irq = irq; |
708 | 80337b66 | bellard | memcpy(s->macaddr, nd->macaddr, 6);
|
709 | 80337b66 | bellard | |
710 | 80337b66 | bellard | smc91c111_reset(s); |
711 | 80337b66 | bellard | |
712 | d861b05e | pbrook | s->vc = qemu_new_vlan_client(nd->vlan, smc91c111_receive, |
713 | d861b05e | pbrook | smc91c111_can_receive, s); |
714 | 80337b66 | bellard | /* ??? Save/restore. */
|
715 | 80337b66 | bellard | } |