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/*
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* Nokia N-series internet tablets.
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*
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* Copyright (C) 2007 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "qemu-common.h" |
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#include "sysemu.h" |
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#include "omap.h" |
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#include "arm-misc.h" |
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#include "irq.h" |
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#include "console.h" |
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#include "boards.h" |
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#include "i2c.h" |
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#include "devices.h" |
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#include "flash.h" |
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#include "hw.h" |
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/* Nokia N8x0 support */
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struct n800_s {
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struct omap_mpu_state_s *cpu;
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|
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struct rfbi_chip_s blizzard;
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struct {
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void *opaque;
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uint32_t (*txrx)(void *opaque, uint32_t value, int len); |
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struct uwire_slave_s *chip;
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} ts; |
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i2c_bus *i2c; |
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|
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int keymap[0x80]; |
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i2c_slave *kbd; |
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|
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struct tusb_s *usb;
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void *retu;
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void *tahvo;
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}; |
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|
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/* GPIO pins */
|
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#define N8X0_TUSB_ENABLE_GPIO 0 |
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#define N800_MMC2_WP_GPIO 8 |
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#define N800_UNKNOWN_GPIO0 9 /* out */ |
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#define N810_MMC2_VIOSD_GPIO 9 |
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#define N800_UNKNOWN_GPIO1 10 /* out */ |
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#define N800_CAM_TURN_GPIO 12 |
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#define N810_GPS_RESET_GPIO 12 |
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#define N800_BLIZZARD_POWERDOWN_GPIO 15 |
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#define N800_MMC1_WP_GPIO 23 |
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#define N810_MMC2_VSD_GPIO 23 |
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#define N8X0_ONENAND_GPIO 26 |
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#define N810_BLIZZARD_RESET_GPIO 30 |
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#define N800_UNKNOWN_GPIO2 53 /* out */ |
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#define N8X0_TUSB_INT_GPIO 58 |
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#define N8X0_BT_WKUP_GPIO 61 |
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#define N8X0_STI_GPIO 62 |
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#define N8X0_CBUS_SEL_GPIO 64 |
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#define N8X0_CBUS_DAT_GPIO 65 |
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#define N8X0_CBUS_CLK_GPIO 66 |
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#define N8X0_WLAN_IRQ_GPIO 87 |
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#define N8X0_BT_RESET_GPIO 92 |
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#define N8X0_TEA5761_CS_GPIO 93 |
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#define N800_UNKNOWN_GPIO 94 |
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#define N810_TSC_RESET_GPIO 94 |
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#define N800_CAM_ACT_GPIO 95 |
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#define N810_GPS_WAKEUP_GPIO 95 |
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#define N8X0_MMC_CS_GPIO 96 |
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#define N8X0_WLAN_PWR_GPIO 97 |
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#define N8X0_BT_HOST_WKUP_GPIO 98 |
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#define N800_UNKNOWN_GPIO3 101 /* out */ |
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#define N810_KB_LOCK_GPIO 102 |
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#define N800_TSC_TS_GPIO 103 |
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#define N810_TSC_TS_GPIO 106 |
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#define N8X0_HEADPHONE_GPIO 107 |
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#define N8X0_RETU_GPIO 108 |
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#define N800_TSC_KP_IRQ_GPIO 109 |
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#define N810_KEYBOARD_GPIO 109 |
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#define N800_BAT_COVER_GPIO 110 |
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#define N810_SLIDE_GPIO 110 |
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#define N8X0_TAHVO_GPIO 111 |
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#define N800_UNKNOWN_GPIO4 112 /* out */ |
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#define N810_SLEEPX_LED_GPIO 112 |
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#define N800_TSC_RESET_GPIO 118 /* ? */ |
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#define N800_TSC_UNKNOWN_GPIO 119 /* out */ |
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#define N8X0_TMP105_GPIO 125 |
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|
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/* Config */
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#define XLDR_LL_UART 1 |
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|
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/* Addresses on the I2C bus 0 */
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#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */ |
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#define N8X0_TCM825x_ADDR 0x29 /* Camera */ |
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#define N810_LP5521_ADDR 0x32 /* LEDs */ |
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#define N810_TSL2563_ADDR 0x3d /* Light sensor */ |
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#define N810_LM8323_ADDR 0x45 /* Keyboard */ |
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/* Addresses on the I2C bus 1 */
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#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */ |
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#define N8X0_MENELAUS_ADDR 0x72 /* Power management */ |
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|
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/* Chipselects on GPMC NOR interface */
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#define N8X0_ONENAND_CS 0 |
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#define N8X0_USB_ASYNC_CS 1 |
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#define N8X0_USB_SYNC_CS 4 |
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|
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static void n800_mmc_cs_cb(void *opaque, int line, int level) |
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{
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/* TODO: this seems to actually be connected to the menelaus, to
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* which also both MMC slots connect. */
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omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
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printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1); |
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} |
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static void n8x0_gpio_setup(struct n800_s *s) |
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{
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qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
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omap2_gpio_out_set(s->cpu->gpif, N8X0_MMC_CS_GPIO, mmc_cs[0]);
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qemu_irq_lower(omap2_gpio_in_get(s->cpu->gpif, N800_BAT_COVER_GPIO)[0]);
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} |
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static void n8x0_nand_setup(struct n800_s *s) |
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{
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/* Either ec40xx or ec48xx are OK for the ID */
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omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
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onenand_base_unmap, |
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onenand_init(0xec4800, 1, |
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omap2_gpio_in_get(s->cpu->gpif, |
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N8X0_ONENAND_GPIO)[0]));
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} |
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|
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static void n8x0_i2c_setup(struct n800_s *s) |
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{
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qemu_irq tmp_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TMP105_GPIO)[0];
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/* Attach the CPU on one end of our I2C bus. */
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s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
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/* Attach a menelaus PM chip */
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i2c_set_slave_address( |
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twl92230_init(s->i2c, |
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s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]),
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N8X0_MENELAUS_ADDR); |
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/* Attach a TMP105 PM chip (A0 wired to ground) */
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i2c_set_slave_address(tmp105_init(s->i2c, tmp_irq), N8X0_TMP105_ADDR); |
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} |
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|
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/* Touchscreen and keypad controller */
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static struct mouse_transform_info_s n800_pointercal = { |
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.x = 800,
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.y = 480,
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.a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
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}; |
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static struct mouse_transform_info_s n810_pointercal = { |
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.x = 800,
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.y = 480,
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.a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
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}; |
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|
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#define RETU_KEYCODE 61 /* F3 */ |
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|
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static void n800_key_event(void *opaque, int keycode) |
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{
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struct n800_s *s = (struct n800_s *) opaque; |
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int code = s->keymap[keycode & 0x7f]; |
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|
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if (code == -1) { |
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if ((keycode & 0x7f) == RETU_KEYCODE) |
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retu_key_event(s->retu, !(keycode & 0x80));
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return;
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} |
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tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
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} |
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|
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static const int n800_keys[16] = { |
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-1,
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72, /* Up */ |
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63, /* Home (F5) */ |
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-1,
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75, /* Left */ |
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28, /* Enter */ |
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77, /* Right */ |
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-1,
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1, /* Cycle (ESC) */ |
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80, /* Down */ |
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62, /* Menu (F4) */ |
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-1,
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66, /* Zoom- (F8) */ |
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64, /* FullScreen (F6) */ |
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65, /* Zoom+ (F7) */ |
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-1,
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}; |
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|
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static void n800_tsc_kbd_setup(struct n800_s *s) |
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{
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int i;
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|
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/* XXX: are the three pins inverted inside the chip between the
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* tsc and the cpu (N4111)? */
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qemu_irq penirq = 0; /* NC */ |
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qemu_irq kbirq = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_KP_IRQ_GPIO)[0];
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qemu_irq dav = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_TS_GPIO)[0];
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s->ts.chip = tsc2301_init(penirq, kbirq, dav, 0);
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s->ts.opaque = s->ts.chip->opaque; |
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s->ts.txrx = tsc210x_txrx; |
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|
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for (i = 0; i < 0x80; i ++) |
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s->keymap[i] = -1;
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for (i = 0; i < 0x10; i ++) |
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if (n800_keys[i] >= 0) |
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s->keymap[n800_keys[i]] = i; |
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|
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qemu_add_kbd_event_handler(n800_key_event, s); |
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|
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tsc210x_set_transform(s->ts.chip, &n800_pointercal); |
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} |
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|
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static void n810_tsc_setup(struct n800_s *s) |
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{
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qemu_irq pintdav = omap2_gpio_in_get(s->cpu->gpif, N810_TSC_TS_GPIO)[0];
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|
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s->ts.opaque = tsc2005_init(pintdav); |
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s->ts.txrx = tsc2005_txrx; |
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|
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tsc2005_set_transform(s->ts.opaque, &n810_pointercal); |
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} |
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|
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/* N810 Keyboard controller */
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static void n810_key_event(void *opaque, int keycode) |
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{
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struct n800_s *s = (struct n800_s *) opaque; |
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int code = s->keymap[keycode & 0x7f]; |
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|
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if (code == -1) { |
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if ((keycode & 0x7f) == RETU_KEYCODE) |
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retu_key_event(s->retu, !(keycode & 0x80));
|
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return;
|
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} |
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|
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lm832x_key_event(s->kbd, code, !(keycode & 0x80));
|
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} |
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|
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#define M 0 |
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|
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static int n810_keys[0x80] = { |
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[0x01] = 16, /* Q */ |
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[0x02] = 37, /* K */ |
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[0x03] = 24, /* O */ |
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[0x04] = 25, /* P */ |
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[0x05] = 14, /* Backspace */ |
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[0x06] = 30, /* A */ |
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[0x07] = 31, /* S */ |
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[0x08] = 32, /* D */ |
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[0x09] = 33, /* F */ |
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[0x0a] = 34, /* G */ |
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[0x0b] = 35, /* H */ |
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[0x0c] = 36, /* J */ |
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|
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[0x11] = 17, /* W */ |
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[0x12] = 62, /* Menu (F4) */ |
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[0x13] = 38, /* L */ |
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[0x14] = 40, /* ' (Apostrophe) */ |
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[0x16] = 44, /* Z */ |
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[0x17] = 45, /* X */ |
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[0x18] = 46, /* C */ |
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[0x19] = 47, /* V */ |
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[0x1a] = 48, /* B */ |
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[0x1b] = 49, /* N */ |
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[0x1c] = 42, /* Shift (Left shift) */ |
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[0x1f] = 65, /* Zoom+ (F7) */ |
| 290 |
|
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[0x21] = 18, /* E */ |
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[0x22] = 39, /* ; (Semicolon) */ |
| 293 |
[0x23] = 12, /* - (Minus) */ |
| 294 |
[0x24] = 13, /* = (Equal) */ |
| 295 |
[0x2b] = 56, /* Fn (Left Alt) */ |
| 296 |
[0x2c] = 50, /* M */ |
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[0x2f] = 66, /* Zoom- (F8) */ |
| 298 |
|
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[0x31] = 19, /* R */ |
| 300 |
[0x32] = 29 | M, /* Right Ctrl */ |
| 301 |
[0x34] = 57, /* Space */ |
| 302 |
[0x35] = 51, /* , (Comma) */ |
| 303 |
[0x37] = 72 | M, /* Up */ |
| 304 |
[0x3c] = 82 | M, /* Compose (Insert) */ |
| 305 |
[0x3f] = 64, /* FullScreen (F6) */ |
| 306 |
|
| 307 |
[0x41] = 20, /* T */ |
| 308 |
[0x44] = 52, /* . (Dot) */ |
| 309 |
[0x46] = 77 | M, /* Right */ |
| 310 |
[0x4f] = 63, /* Home (F5) */ |
| 311 |
[0x51] = 21, /* Y */ |
| 312 |
[0x53] = 80 | M, /* Down */ |
| 313 |
[0x55] = 28, /* Enter */ |
| 314 |
[0x5f] = 1, /* Cycle (ESC) */ |
| 315 |
|
| 316 |
[0x61] = 22, /* U */ |
| 317 |
[0x64] = 75 | M, /* Left */ |
| 318 |
|
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[0x71] = 23, /* I */ |
| 320 |
#if 0
|
| 321 |
[0x75] = 28 | M, /* KP Enter (KP Enter) */
|
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#else
|
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[0x75] = 15, /* KP Enter (Tab) */ |
| 324 |
#endif
|
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}; |
| 326 |
|
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#undef M
|
| 328 |
|
| 329 |
static void n810_kbd_setup(struct n800_s *s) |
| 330 |
{
|
| 331 |
qemu_irq kbd_irq = omap2_gpio_in_get(s->cpu->gpif, N810_KEYBOARD_GPIO)[0];
|
| 332 |
int i;
|
| 333 |
|
| 334 |
for (i = 0; i < 0x80; i ++) |
| 335 |
s->keymap[i] = -1;
|
| 336 |
for (i = 0; i < 0x80; i ++) |
| 337 |
if (n810_keys[i] > 0) |
| 338 |
s->keymap[n810_keys[i]] = i; |
| 339 |
|
| 340 |
qemu_add_kbd_event_handler(n810_key_event, s); |
| 341 |
|
| 342 |
/* Attach the LM8322 keyboard to the I2C bus,
|
| 343 |
* should happen in n8x0_i2c_setup and s->kbd be initialised here. */
|
| 344 |
s->kbd = lm8323_init(s->i2c, kbd_irq); |
| 345 |
i2c_set_slave_address(s->kbd, N810_LM8323_ADDR); |
| 346 |
} |
| 347 |
|
| 348 |
/* LCD MIPI DBI-C controller (URAL) */
|
| 349 |
struct mipid_s {
|
| 350 |
int resp[4]; |
| 351 |
int param[4]; |
| 352 |
int p;
|
| 353 |
int pm;
|
| 354 |
int cmd;
|
| 355 |
|
| 356 |
int sleep;
|
| 357 |
int booster;
|
| 358 |
int te;
|
| 359 |
int selfcheck;
|
| 360 |
int partial;
|
| 361 |
int normal;
|
| 362 |
int vscr;
|
| 363 |
int invert;
|
| 364 |
int onoff;
|
| 365 |
int gamma;
|
| 366 |
uint32_t id; |
| 367 |
}; |
| 368 |
|
| 369 |
static void mipid_reset(struct mipid_s *s) |
| 370 |
{
|
| 371 |
if (!s->sleep)
|
| 372 |
fprintf(stderr, "%s: Display off\n", __FUNCTION__);
|
| 373 |
|
| 374 |
s->pm = 0;
|
| 375 |
s->cmd = 0;
|
| 376 |
|
| 377 |
s->sleep = 1;
|
| 378 |
s->booster = 0;
|
| 379 |
s->selfcheck = |
| 380 |
(1 << 7) | /* Register loading OK. */ |
| 381 |
(1 << 5) | /* The chip is attached. */ |
| 382 |
(1 << 4); /* Display glass still in one piece. */ |
| 383 |
s->te = 0;
|
| 384 |
s->partial = 0;
|
| 385 |
s->normal = 1;
|
| 386 |
s->vscr = 0;
|
| 387 |
s->invert = 0;
|
| 388 |
s->onoff = 1;
|
| 389 |
s->gamma = 0;
|
| 390 |
} |
| 391 |
|
| 392 |
static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) |
| 393 |
{
|
| 394 |
struct mipid_s *s = (struct mipid_s *) opaque; |
| 395 |
uint8_t ret; |
| 396 |
|
| 397 |
if (len > 9) |
| 398 |
cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
|
| 399 |
__FUNCTION__, len); |
| 400 |
|
| 401 |
if (s->p >= sizeof(s->resp) / sizeof(*s->resp)) |
| 402 |
ret = 0;
|
| 403 |
else
|
| 404 |
ret = s->resp[s->p ++]; |
| 405 |
if (s->pm --> 0) |
| 406 |
s->param[s->pm] = cmd; |
| 407 |
else
|
| 408 |
s->cmd = cmd; |
| 409 |
|
| 410 |
switch (s->cmd) {
|
| 411 |
case 0x00: /* NOP */ |
| 412 |
break;
|
| 413 |
|
| 414 |
case 0x01: /* SWRESET */ |
| 415 |
mipid_reset(s); |
| 416 |
break;
|
| 417 |
|
| 418 |
case 0x02: /* BSTROFF */ |
| 419 |
s->booster = 0;
|
| 420 |
break;
|
| 421 |
case 0x03: /* BSTRON */ |
| 422 |
s->booster = 1;
|
| 423 |
break;
|
| 424 |
|
| 425 |
case 0x04: /* RDDID */ |
| 426 |
s->p = 0;
|
| 427 |
s->resp[0] = (s->id >> 16) & 0xff; |
| 428 |
s->resp[1] = (s->id >> 8) & 0xff; |
| 429 |
s->resp[2] = (s->id >> 0) & 0xff; |
| 430 |
break;
|
| 431 |
|
| 432 |
case 0x06: /* RD_RED */ |
| 433 |
case 0x07: /* RD_GREEN */ |
| 434 |
/* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
|
| 435 |
* for the bootloader one needs to change this. */
|
| 436 |
case 0x08: /* RD_BLUE */ |
| 437 |
s->p = 0;
|
| 438 |
/* TODO: return first pixel components */
|
| 439 |
s->resp[0] = 0x01; |
| 440 |
break;
|
| 441 |
|
| 442 |
case 0x09: /* RDDST */ |
| 443 |
s->p = 0;
|
| 444 |
s->resp[0] = s->booster << 7; |
| 445 |
s->resp[1] = (5 << 4) | (s->partial << 2) | |
| 446 |
(s->sleep << 1) | s->normal;
|
| 447 |
s->resp[2] = (s->vscr << 7) | (s->invert << 5) | |
| 448 |
(s->onoff << 2) | (s->te << 1) | (s->gamma >> 2); |
| 449 |
s->resp[3] = s->gamma << 6; |
| 450 |
break;
|
| 451 |
|
| 452 |
case 0x0a: /* RDDPM */ |
| 453 |
s->p = 0;
|
| 454 |
s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) | |
| 455 |
(s->partial << 5) | (s->sleep << 6) | (s->booster << 7); |
| 456 |
break;
|
| 457 |
case 0x0b: /* RDDMADCTR */ |
| 458 |
s->p = 0;
|
| 459 |
s->resp[0] = 0; |
| 460 |
break;
|
| 461 |
case 0x0c: /* RDDCOLMOD */ |
| 462 |
s->p = 0;
|
| 463 |
s->resp[0] = 5; /* 65K colours */ |
| 464 |
break;
|
| 465 |
case 0x0d: /* RDDIM */ |
| 466 |
s->p = 0;
|
| 467 |
s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma; |
| 468 |
break;
|
| 469 |
case 0x0e: /* RDDSM */ |
| 470 |
s->p = 0;
|
| 471 |
s->resp[0] = s->te << 7; |
| 472 |
break;
|
| 473 |
case 0x0f: /* RDDSDR */ |
| 474 |
s->p = 0;
|
| 475 |
s->resp[0] = s->selfcheck;
|
| 476 |
break;
|
| 477 |
|
| 478 |
case 0x10: /* SLPIN */ |
| 479 |
s->sleep = 1;
|
| 480 |
break;
|
| 481 |
case 0x11: /* SLPOUT */ |
| 482 |
s->sleep = 0;
|
| 483 |
s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */ |
| 484 |
break;
|
| 485 |
|
| 486 |
case 0x12: /* PTLON */ |
| 487 |
s->partial = 1;
|
| 488 |
s->normal = 0;
|
| 489 |
s->vscr = 0;
|
| 490 |
break;
|
| 491 |
case 0x13: /* NORON */ |
| 492 |
s->partial = 0;
|
| 493 |
s->normal = 1;
|
| 494 |
s->vscr = 0;
|
| 495 |
break;
|
| 496 |
|
| 497 |
case 0x20: /* INVOFF */ |
| 498 |
s->invert = 0;
|
| 499 |
break;
|
| 500 |
case 0x21: /* INVON */ |
| 501 |
s->invert = 1;
|
| 502 |
break;
|
| 503 |
|
| 504 |
case 0x22: /* APOFF */ |
| 505 |
case 0x23: /* APON */ |
| 506 |
goto bad_cmd;
|
| 507 |
|
| 508 |
case 0x25: /* WRCNTR */ |
| 509 |
if (s->pm < 0) |
| 510 |
s->pm = 1;
|
| 511 |
goto bad_cmd;
|
| 512 |
|
| 513 |
case 0x26: /* GAMSET */ |
| 514 |
if (!s->pm)
|
| 515 |
s->gamma = ffs(s->param[0] & 0xf) - 1; |
| 516 |
else if (s->pm < 0) |
| 517 |
s->pm = 1;
|
| 518 |
break;
|
| 519 |
|
| 520 |
case 0x28: /* DISPOFF */ |
| 521 |
s->onoff = 0;
|
| 522 |
fprintf(stderr, "%s: Display off\n", __FUNCTION__);
|
| 523 |
break;
|
| 524 |
case 0x29: /* DISPON */ |
| 525 |
s->onoff = 1;
|
| 526 |
fprintf(stderr, "%s: Display on\n", __FUNCTION__);
|
| 527 |
break;
|
| 528 |
|
| 529 |
case 0x2a: /* CASET */ |
| 530 |
case 0x2b: /* RASET */ |
| 531 |
case 0x2c: /* RAMWR */ |
| 532 |
case 0x2d: /* RGBSET */ |
| 533 |
case 0x2e: /* RAMRD */ |
| 534 |
case 0x30: /* PTLAR */ |
| 535 |
case 0x33: /* SCRLAR */ |
| 536 |
goto bad_cmd;
|
| 537 |
|
| 538 |
case 0x34: /* TEOFF */ |
| 539 |
s->te = 0;
|
| 540 |
break;
|
| 541 |
case 0x35: /* TEON */ |
| 542 |
if (!s->pm)
|
| 543 |
s->te = 1;
|
| 544 |
else if (s->pm < 0) |
| 545 |
s->pm = 1;
|
| 546 |
break;
|
| 547 |
|
| 548 |
case 0x36: /* MADCTR */ |
| 549 |
goto bad_cmd;
|
| 550 |
|
| 551 |
case 0x37: /* VSCSAD */ |
| 552 |
s->partial = 0;
|
| 553 |
s->normal = 0;
|
| 554 |
s->vscr = 1;
|
| 555 |
break;
|
| 556 |
|
| 557 |
case 0x38: /* IDMOFF */ |
| 558 |
case 0x39: /* IDMON */ |
| 559 |
case 0x3a: /* COLMOD */ |
| 560 |
goto bad_cmd;
|
| 561 |
|
| 562 |
case 0xb0: /* CLKINT / DISCTL */ |
| 563 |
case 0xb1: /* CLKEXT */ |
| 564 |
if (s->pm < 0) |
| 565 |
s->pm = 2;
|
| 566 |
break;
|
| 567 |
|
| 568 |
case 0xb4: /* FRMSEL */ |
| 569 |
break;
|
| 570 |
|
| 571 |
case 0xb5: /* FRM8SEL */ |
| 572 |
case 0xb6: /* TMPRNG / INIESC */ |
| 573 |
case 0xb7: /* TMPHIS / NOP2 */ |
| 574 |
case 0xb8: /* TMPREAD / MADCTL */ |
| 575 |
case 0xba: /* DISTCTR */ |
| 576 |
case 0xbb: /* EPVOL */ |
| 577 |
goto bad_cmd;
|
| 578 |
|
| 579 |
case 0xbd: /* Unknown */ |
| 580 |
s->p = 0;
|
| 581 |
s->resp[0] = 0; |
| 582 |
s->resp[1] = 1; |
| 583 |
break;
|
| 584 |
|
| 585 |
case 0xc2: /* IFMOD */ |
| 586 |
if (s->pm < 0) |
| 587 |
s->pm = 2;
|
| 588 |
break;
|
| 589 |
|
| 590 |
case 0xc6: /* PWRCTL */ |
| 591 |
case 0xc7: /* PPWRCTL */ |
| 592 |
case 0xd0: /* EPWROUT */ |
| 593 |
case 0xd1: /* EPWRIN */ |
| 594 |
case 0xd4: /* RDEV */ |
| 595 |
case 0xd5: /* RDRR */ |
| 596 |
goto bad_cmd;
|
| 597 |
|
| 598 |
case 0xda: /* RDID1 */ |
| 599 |
s->p = 0;
|
| 600 |
s->resp[0] = (s->id >> 16) & 0xff; |
| 601 |
break;
|
| 602 |
case 0xdb: /* RDID2 */ |
| 603 |
s->p = 0;
|
| 604 |
s->resp[0] = (s->id >> 8) & 0xff; |
| 605 |
break;
|
| 606 |
case 0xdc: /* RDID3 */ |
| 607 |
s->p = 0;
|
| 608 |
s->resp[0] = (s->id >> 0) & 0xff; |
| 609 |
break;
|
| 610 |
|
| 611 |
default:
|
| 612 |
bad_cmd:
|
| 613 |
fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
|
| 614 |
break;
|
| 615 |
} |
| 616 |
|
| 617 |
return ret;
|
| 618 |
} |
| 619 |
|
| 620 |
static void *mipid_init(void) |
| 621 |
{
|
| 622 |
struct mipid_s *s = (struct mipid_s *) qemu_mallocz(sizeof(*s)); |
| 623 |
|
| 624 |
s->id = 0x838f03;
|
| 625 |
mipid_reset(s); |
| 626 |
|
| 627 |
return s;
|
| 628 |
} |
| 629 |
|
| 630 |
static void n8x0_spi_setup(struct n800_s *s) |
| 631 |
{
|
| 632 |
void *tsc = s->ts.opaque;
|
| 633 |
void *mipid = mipid_init();
|
| 634 |
|
| 635 |
omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0); |
| 636 |
omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1); |
| 637 |
} |
| 638 |
|
| 639 |
/* This task is normally performed by the bootloader. If we're loading
|
| 640 |
* a kernel directly, we need to enable the Blizzard ourselves. */
|
| 641 |
static void n800_dss_init(struct rfbi_chip_s *chip) |
| 642 |
{
|
| 643 |
uint8_t *fb_blank; |
| 644 |
|
| 645 |
chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */ |
| 646 |
chip->write(chip->opaque, 1, 0x64); |
| 647 |
chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */ |
| 648 |
chip->write(chip->opaque, 1, 0x1e); |
| 649 |
chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */ |
| 650 |
chip->write(chip->opaque, 1, 0xe0); |
| 651 |
chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */ |
| 652 |
chip->write(chip->opaque, 1, 0x01); |
| 653 |
chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */ |
| 654 |
chip->write(chip->opaque, 1, 0x06); |
| 655 |
chip->write(chip->opaque, 0, 0x68); /* Display Mode register */ |
| 656 |
chip->write(chip->opaque, 1, 1); /* Enable bit */ |
| 657 |
|
| 658 |
chip->write(chip->opaque, 0, 0x6c); |
| 659 |
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ |
| 660 |
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ |
| 661 |
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ |
| 662 |
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ |
| 663 |
chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */ |
| 664 |
chip->write(chip->opaque, 1, 0x03); /* Input X End Position */ |
| 665 |
chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */ |
| 666 |
chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */ |
| 667 |
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ |
| 668 |
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ |
| 669 |
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ |
| 670 |
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ |
| 671 |
chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */ |
| 672 |
chip->write(chip->opaque, 1, 0x03); /* Output X End Position */ |
| 673 |
chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */ |
| 674 |
chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */ |
| 675 |
chip->write(chip->opaque, 1, 0x01); /* Input Data Format */ |
| 676 |
chip->write(chip->opaque, 1, 0x01); /* Data Source Select */ |
| 677 |
|
| 678 |
fb_blank = memset(qemu_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2); |
| 679 |
/* Display Memory Data Port */
|
| 680 |
chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800); |
| 681 |
free(fb_blank); |
| 682 |
} |
| 683 |
|
| 684 |
static void n8x0_dss_setup(struct n800_s *s, DisplayState *ds) |
| 685 |
{
|
| 686 |
s->blizzard.opaque = s1d13745_init(0, ds);
|
| 687 |
s->blizzard.block = s1d13745_write_block; |
| 688 |
s->blizzard.write = s1d13745_write; |
| 689 |
s->blizzard.read = s1d13745_read; |
| 690 |
|
| 691 |
omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
|
| 692 |
} |
| 693 |
|
| 694 |
static void n8x0_cbus_setup(struct n800_s *s) |
| 695 |
{
|
| 696 |
qemu_irq dat_out = omap2_gpio_in_get(s->cpu->gpif, N8X0_CBUS_DAT_GPIO)[0];
|
| 697 |
qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];
|
| 698 |
qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0];
|
| 699 |
|
| 700 |
struct cbus_s *cbus = cbus_init(dat_out);
|
| 701 |
|
| 702 |
omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk); |
| 703 |
omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat); |
| 704 |
omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_SEL_GPIO, cbus->sel); |
| 705 |
|
| 706 |
cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
|
| 707 |
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
|
| 708 |
} |
| 709 |
|
| 710 |
static void n8x0_usb_power_cb(void *opaque, int line, int level) |
| 711 |
{
|
| 712 |
struct n800_s *s = opaque;
|
| 713 |
|
| 714 |
tusb6010_power(s->usb, level); |
| 715 |
} |
| 716 |
|
| 717 |
static void n8x0_usb_setup(struct n800_s *s) |
| 718 |
{
|
| 719 |
qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];
|
| 720 |
qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0]; |
| 721 |
struct tusb_s *tusb = tusb6010_init(tusb_irq);
|
| 722 |
|
| 723 |
/* Using the NOR interface */
|
| 724 |
omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS, |
| 725 |
tusb6010_async_io(tusb), 0, 0, tusb); |
| 726 |
omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS, |
| 727 |
tusb6010_sync_io(tusb), 0, 0, tusb); |
| 728 |
|
| 729 |
s->usb = tusb; |
| 730 |
omap2_gpio_out_set(s->cpu->gpif, N8X0_TUSB_ENABLE_GPIO, tusb_pwr); |
| 731 |
} |
| 732 |
|
| 733 |
/* Setup done before the main bootloader starts by some early setup code
|
| 734 |
* - used when we want to run the main bootloader in emulation. This
|
| 735 |
* isn't documented. */
|
| 736 |
static uint32_t n800_pinout[104] = { |
| 737 |
0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0, |
| 738 |
0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808, |
| 739 |
0x08080808, 0x180800c4, 0x00b80000, 0x08080808, |
| 740 |
0x080800bc, 0x00cc0808, 0x08081818, 0x18180128, |
| 741 |
0x01241800, 0x18181818, 0x000000f0, 0x01300000, |
| 742 |
0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b, |
| 743 |
0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080, |
| 744 |
0x007c0000, 0x00000000, 0x00000088, 0x00840000, |
| 745 |
0x00000000, 0x00000094, 0x00980300, 0x0f180003, |
| 746 |
0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c, |
| 747 |
0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008, |
| 748 |
0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f, |
| 749 |
0x181800f4, 0x00f81818, 0x00000018, 0x000000fc, |
| 750 |
0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008, |
| 751 |
0x00000000, 0x00000038, 0x00340000, 0x00000000, |
| 752 |
0x1a080070, 0x00641a1a, 0x08080808, 0x08080060, |
| 753 |
0x005c0808, 0x08080808, 0x08080058, 0x00540808, |
| 754 |
0x08080808, 0x0808006c, 0x00680808, 0x08080808, |
| 755 |
0x000000a8, 0x00b00000, 0x08080808, 0x000000a0, |
| 756 |
0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808, |
| 757 |
0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff, |
| 758 |
0x000000ac, 0x01040800, 0x08080b0f, 0x18180100, |
| 759 |
0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a, |
| 760 |
0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00, |
| 761 |
0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118, |
| 762 |
0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b, |
| 763 |
}; |
| 764 |
|
| 765 |
static void n800_setup_nolo_tags(void *sram_base) |
| 766 |
{
|
| 767 |
int i;
|
| 768 |
uint32_t *p = sram_base + 0x8000;
|
| 769 |
uint32_t *v = sram_base + 0xa000;
|
| 770 |
|
| 771 |
memset(p, 0, 0x3000); |
| 772 |
|
| 773 |
strcpy((void *) (p + 0), "QEMU N800"); |
| 774 |
|
| 775 |
strcpy((void *) (p + 8), "F5"); |
| 776 |
|
| 777 |
stl_raw(p + 10, 0x04f70000); |
| 778 |
strcpy((void *) (p + 9), "RX-34"); |
| 779 |
|
| 780 |
/* RAM size in MB? */
|
| 781 |
stl_raw(p + 12, 0x80); |
| 782 |
|
| 783 |
/* Pointer to the list of tags */
|
| 784 |
stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000); |
| 785 |
|
| 786 |
/* The NOLO tags start here */
|
| 787 |
p = sram_base + 0x9000;
|
| 788 |
#define ADD_TAG(tag, len) \
|
| 789 |
stw_raw((uint16_t *) p + 0, tag); \
|
| 790 |
stw_raw((uint16_t *) p + 1, len); p ++; \
|
| 791 |
stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff)); |
| 792 |
|
| 793 |
/* OMAP STI console? Pin out settings? */
|
| 794 |
ADD_TAG(0x6e01, 414); |
| 795 |
for (i = 0; i < sizeof(n800_pinout) / 4; i ++) |
| 796 |
stl_raw(v ++, n800_pinout[i]); |
| 797 |
|
| 798 |
/* Kernel memsize? */
|
| 799 |
ADD_TAG(0x6e05, 1); |
| 800 |
stl_raw(v ++, 2);
|
| 801 |
|
| 802 |
/* NOLO serial console */
|
| 803 |
ADD_TAG(0x6e02, 4); |
| 804 |
stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
|
| 805 |
|
| 806 |
#if 0
|
| 807 |
/* CBUS settings (Retu/AVilma) */
|
| 808 |
ADD_TAG(0x6e03, 6);
|
| 809 |
stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
|
| 810 |
stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
|
| 811 |
stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
|
| 812 |
v += 2;
|
| 813 |
#endif
|
| 814 |
|
| 815 |
/* Nokia ASIC BB5 (Retu/Tahvo) */
|
| 816 |
ADD_TAG(0x6e0a, 4); |
| 817 |
stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */ |
| 818 |
stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */ |
| 819 |
v ++; |
| 820 |
|
| 821 |
/* LCD console? */
|
| 822 |
ADD_TAG(0x6e04, 4); |
| 823 |
stw_raw((uint16_t *) v + 0, 30); /* ??? */ |
| 824 |
stw_raw((uint16_t *) v + 1, 24); /* ??? */ |
| 825 |
v ++; |
| 826 |
|
| 827 |
#if 0
|
| 828 |
/* LCD settings */
|
| 829 |
ADD_TAG(0x6e06, 2);
|
| 830 |
stw_raw((uint16_t *) (v ++), 15); /* ??? */
|
| 831 |
#endif
|
| 832 |
|
| 833 |
/* I^2C (Menelaus) */
|
| 834 |
ADD_TAG(0x6e07, 4); |
| 835 |
stl_raw(v ++, 0x00720000); /* ??? */ |
| 836 |
|
| 837 |
/* Unknown */
|
| 838 |
ADD_TAG(0x6e0b, 6); |
| 839 |
stw_raw((uint16_t *) v + 0, 94); /* ??? */ |
| 840 |
stw_raw((uint16_t *) v + 1, 23); /* ??? */ |
| 841 |
stw_raw((uint16_t *) v + 2, 0); /* ??? */ |
| 842 |
v += 2;
|
| 843 |
|
| 844 |
/* OMAP gpio switch info */
|
| 845 |
ADD_TAG(0x6e0c, 80); |
| 846 |
strcpy((void *) v, "bat_cover"); v += 3; |
| 847 |
stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */ |
| 848 |
stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */ |
| 849 |
v += 2;
|
| 850 |
strcpy((void *) v, "cam_act"); v += 3; |
| 851 |
stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */ |
| 852 |
stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */ |
| 853 |
v += 2;
|
| 854 |
strcpy((void *) v, "cam_turn"); v += 3; |
| 855 |
stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */ |
| 856 |
stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */ |
| 857 |
v += 2;
|
| 858 |
strcpy((void *) v, "headphone"); v += 3; |
| 859 |
stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */ |
| 860 |
stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */ |
| 861 |
v += 2;
|
| 862 |
|
| 863 |
/* Bluetooth */
|
| 864 |
ADD_TAG(0x6e0e, 12); |
| 865 |
stl_raw(v ++, 0x5c623d01); /* ??? */ |
| 866 |
stl_raw(v ++, 0x00000201); /* ??? */ |
| 867 |
stl_raw(v ++, 0x00000000); /* ??? */ |
| 868 |
|
| 869 |
/* CX3110x WLAN settings */
|
| 870 |
ADD_TAG(0x6e0f, 8); |
| 871 |
stl_raw(v ++, 0x00610025); /* ??? */ |
| 872 |
stl_raw(v ++, 0xffff0057); /* ??? */ |
| 873 |
|
| 874 |
/* MMC host settings */
|
| 875 |
ADD_TAG(0x6e10, 12); |
| 876 |
stl_raw(v ++, 0xffff000f); /* ??? */ |
| 877 |
stl_raw(v ++, 0xffffffff); /* ??? */ |
| 878 |
stl_raw(v ++, 0x00000060); /* ??? */ |
| 879 |
|
| 880 |
/* OneNAND chip select */
|
| 881 |
ADD_TAG(0x6e11, 10); |
| 882 |
stl_raw(v ++, 0x00000401); /* ??? */ |
| 883 |
stl_raw(v ++, 0x0002003a); /* ??? */ |
| 884 |
stl_raw(v ++, 0x00000002); /* ??? */ |
| 885 |
|
| 886 |
/* TEA5761 sensor settings */
|
| 887 |
ADD_TAG(0x6e12, 2); |
| 888 |
stl_raw(v ++, 93); /* GPIO num ??? */ |
| 889 |
|
| 890 |
#if 0
|
| 891 |
/* Unknown tag */
|
| 892 |
ADD_TAG(6e09, 0);
|
| 893 |
|
| 894 |
/* Kernel UART / console */
|
| 895 |
ADD_TAG(6e12, 0);
|
| 896 |
#endif
|
| 897 |
|
| 898 |
/* End of the list */
|
| 899 |
stl_raw(p ++, 0x00000000);
|
| 900 |
stl_raw(p ++, 0x00000000);
|
| 901 |
} |
| 902 |
|
| 903 |
/* This task is normally performed by the bootloader. If we're loading
|
| 904 |
* a kernel directly, we need to set up GPMC mappings ourselves. */
|
| 905 |
static void n800_gpmc_init(struct n800_s *s) |
| 906 |
{
|
| 907 |
uint32_t config7 = |
| 908 |
(0xf << 8) | /* MASKADDRESS */ |
| 909 |
(1 << 6) | /* CSVALID */ |
| 910 |
(4 << 0); /* BASEADDRESS */ |
| 911 |
|
| 912 |
cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */ |
| 913 |
(void *) &config7, sizeof(config7)); |
| 914 |
} |
| 915 |
|
| 916 |
/* Setup sequence done by the bootloader */
|
| 917 |
static void n8x0_boot_init(void *opaque) |
| 918 |
{
|
| 919 |
struct n800_s *s = (struct n800_s *) opaque; |
| 920 |
uint32_t buf; |
| 921 |
|
| 922 |
/* PRCM setup */
|
| 923 |
#define omap_writel(addr, val) \
|
| 924 |
buf = (val); \ |
| 925 |
cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf)) |
| 926 |
|
| 927 |
omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */ |
| 928 |
omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */ |
| 929 |
omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */ |
| 930 |
omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */ |
| 931 |
omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */ |
| 932 |
omap_writel(0x48008098, 0); /* PRCM_POLCTRL */ |
| 933 |
omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */ |
| 934 |
omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */ |
| 935 |
omap_writel(0x48008158, 1); /* RM_RSTST_MPU */ |
| 936 |
omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */ |
| 937 |
omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */ |
| 938 |
omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */ |
| 939 |
omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */ |
| 940 |
omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */ |
| 941 |
omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */ |
| 942 |
omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */ |
| 943 |
omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */ |
| 944 |
omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */ |
| 945 |
omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */ |
| 946 |
omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */ |
| 947 |
omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */ |
| 948 |
omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */ |
| 949 |
omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */ |
| 950 |
omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */ |
| 951 |
omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */ |
| 952 |
omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */ |
| 953 |
omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */ |
| 954 |
omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */ |
| 955 |
omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */ |
| 956 |
omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */ |
| 957 |
omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */ |
| 958 |
omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */ |
| 959 |
omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */ |
| 960 |
omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */ |
| 961 |
omap_writel(0x48008540, /* CM_CLKSEL1_PLL */ |
| 962 |
(0x78 << 12) | (6 << 8)); |
| 963 |
omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */ |
| 964 |
|
| 965 |
/* GPMC setup */
|
| 966 |
n800_gpmc_init(s); |
| 967 |
|
| 968 |
/* Video setup */
|
| 969 |
n800_dss_init(&s->blizzard); |
| 970 |
|
| 971 |
/* CPU setup */
|
| 972 |
s->cpu->env->regs[15] = s->cpu->env->boot_info->loader_start;
|
| 973 |
s->cpu->env->GE = 0x5;
|
| 974 |
|
| 975 |
/* If the machine has a slided keyboard, open it */
|
| 976 |
if (s->kbd)
|
| 977 |
qemu_irq_raise(omap2_gpio_in_get(s->cpu->gpif, N810_SLIDE_GPIO)[0]);
|
| 978 |
} |
| 979 |
|
| 980 |
#define OMAP_TAG_NOKIA_BT 0x4e01 |
| 981 |
#define OMAP_TAG_WLAN_CX3110X 0x4e02 |
| 982 |
#define OMAP_TAG_CBUS 0x4e03 |
| 983 |
#define OMAP_TAG_EM_ASIC_BB5 0x4e04 |
| 984 |
|
| 985 |
static struct omap_gpiosw_info_s { |
| 986 |
const char *name; |
| 987 |
int line;
|
| 988 |
int type;
|
| 989 |
} n800_gpiosw_info[] = {
|
| 990 |
{
|
| 991 |
"bat_cover", N800_BAT_COVER_GPIO,
|
| 992 |
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
| 993 |
}, {
|
| 994 |
"cam_act", N800_CAM_ACT_GPIO,
|
| 995 |
OMAP_GPIOSW_TYPE_ACTIVITY, |
| 996 |
}, {
|
| 997 |
"cam_turn", N800_CAM_TURN_GPIO,
|
| 998 |
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED, |
| 999 |
}, {
|
| 1000 |
"headphone", N8X0_HEADPHONE_GPIO,
|
| 1001 |
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, |
| 1002 |
}, |
| 1003 |
{ 0 }
|
| 1004 |
}, n810_gpiosw_info[] = {
|
| 1005 |
{
|
| 1006 |
"gps_reset", N810_GPS_RESET_GPIO,
|
| 1007 |
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, |
| 1008 |
}, {
|
| 1009 |
"gps_wakeup", N810_GPS_WAKEUP_GPIO,
|
| 1010 |
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, |
| 1011 |
}, {
|
| 1012 |
"headphone", N8X0_HEADPHONE_GPIO,
|
| 1013 |
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, |
| 1014 |
}, {
|
| 1015 |
"kb_lock", N810_KB_LOCK_GPIO,
|
| 1016 |
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
| 1017 |
}, {
|
| 1018 |
"sleepx_led", N810_SLEEPX_LED_GPIO,
|
| 1019 |
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT, |
| 1020 |
}, {
|
| 1021 |
"slide", N810_SLIDE_GPIO,
|
| 1022 |
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
| 1023 |
}, |
| 1024 |
{ 0 }
|
| 1025 |
}; |
| 1026 |
|
| 1027 |
static struct omap_partition_info_s { |
| 1028 |
uint32_t offset; |
| 1029 |
uint32_t size; |
| 1030 |
int mask;
|
| 1031 |
const char *name; |
| 1032 |
} n800_part_info[] = {
|
| 1033 |
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
|
| 1034 |
{ 0x00020000, 0x00060000, 0x0, "config" },
|
| 1035 |
{ 0x00080000, 0x00200000, 0x0, "kernel" },
|
| 1036 |
{ 0x00280000, 0x00200000, 0x3, "initfs" },
|
| 1037 |
{ 0x00480000, 0x0fb80000, 0x3, "rootfs" },
|
| 1038 |
|
| 1039 |
{ 0, 0, 0, 0 }
|
| 1040 |
}, n810_part_info[] = {
|
| 1041 |
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
|
| 1042 |
{ 0x00020000, 0x00060000, 0x0, "config" },
|
| 1043 |
{ 0x00080000, 0x00220000, 0x0, "kernel" },
|
| 1044 |
{ 0x002a0000, 0x00400000, 0x0, "initfs" },
|
| 1045 |
{ 0x006a0000, 0x0f960000, 0x0, "rootfs" },
|
| 1046 |
|
| 1047 |
{ 0, 0, 0, 0 }
|
| 1048 |
}; |
| 1049 |
|
| 1050 |
static int n8x0_atag_setup(void *p, int model) |
| 1051 |
{
|
| 1052 |
uint8_t *b; |
| 1053 |
uint16_t *w; |
| 1054 |
uint32_t *l; |
| 1055 |
struct omap_gpiosw_info_s *gpiosw;
|
| 1056 |
struct omap_partition_info_s *partition;
|
| 1057 |
const char *tag; |
| 1058 |
|
| 1059 |
w = p; |
| 1060 |
|
| 1061 |
stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
|
| 1062 |
stw_raw(w ++, 4); /* u16 len */ |
| 1063 |
stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */ |
| 1064 |
w ++; |
| 1065 |
|
| 1066 |
#if 0
|
| 1067 |
stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
|
| 1068 |
stw_raw(w ++, 4); /* u16 len */
|
| 1069 |
stw_raw(w ++, XLDR_LL_UART); /* u8 console_uart */
|
| 1070 |
stw_raw(w ++, 115200); /* u32 console_speed */
|
| 1071 |
#endif
|
| 1072 |
|
| 1073 |
stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
|
| 1074 |
stw_raw(w ++, 36); /* u16 len */ |
| 1075 |
strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */ |
| 1076 |
w += 8;
|
| 1077 |
strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */ |
| 1078 |
w += 8;
|
| 1079 |
stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
|
| 1080 |
stw_raw(w ++, 24); /* u8 data_lines */ |
| 1081 |
|
| 1082 |
stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
|
| 1083 |
stw_raw(w ++, 8); /* u16 len */ |
| 1084 |
stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
|
| 1085 |
stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
|
| 1086 |
stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
|
| 1087 |
w ++; |
| 1088 |
|
| 1089 |
stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
|
| 1090 |
stw_raw(w ++, 4); /* u16 len */ |
| 1091 |
stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
|
| 1092 |
stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
|
| 1093 |
|
| 1094 |
gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
|
| 1095 |
for (; gpiosw->name; gpiosw ++) {
|
| 1096 |
stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
|
| 1097 |
stw_raw(w ++, 20); /* u16 len */ |
| 1098 |
strcpy((void *) w, gpiosw->name); /* char name[12] */ |
| 1099 |
w += 6;
|
| 1100 |
stw_raw(w ++, gpiosw->line); /* u16 gpio */
|
| 1101 |
stw_raw(w ++, gpiosw->type); |
| 1102 |
stw_raw(w ++, 0);
|
| 1103 |
stw_raw(w ++, 0);
|
| 1104 |
} |
| 1105 |
|
| 1106 |
stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
|
| 1107 |
stw_raw(w ++, 12); /* u16 len */ |
| 1108 |
b = (void *) w;
|
| 1109 |
stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */ |
| 1110 |
stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
|
| 1111 |
stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
|
| 1112 |
stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
|
| 1113 |
stb_raw(b ++, 1); /* u8 bt_uart */ |
| 1114 |
memset(b, 0, 6); /* u8 bd_addr[6] */ |
| 1115 |
b += 6;
|
| 1116 |
stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */ |
| 1117 |
w = (void *) b;
|
| 1118 |
|
| 1119 |
stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
|
| 1120 |
stw_raw(w ++, 8); /* u16 len */ |
| 1121 |
stw_raw(w ++, 0x25); /* u8 chip_type */ |
| 1122 |
stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
|
| 1123 |
stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
|
| 1124 |
stw_raw(w ++, -1); /* s16 spi_cs_gpio */ |
| 1125 |
|
| 1126 |
stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
|
| 1127 |
stw_raw(w ++, 16); /* u16 len */ |
| 1128 |
if (model == 810) { |
| 1129 |
stw_raw(w ++, 0x23f); /* unsigned flags */ |
| 1130 |
stw_raw(w ++, -1); /* s16 power_pin */ |
| 1131 |
stw_raw(w ++, -1); /* s16 switch_pin */ |
| 1132 |
stw_raw(w ++, -1); /* s16 wp_pin */ |
| 1133 |
stw_raw(w ++, 0x240); /* unsigned flags */ |
| 1134 |
stw_raw(w ++, 0xc000); /* s16 power_pin */ |
| 1135 |
stw_raw(w ++, 0x0248); /* s16 switch_pin */ |
| 1136 |
stw_raw(w ++, 0xc000); /* s16 wp_pin */ |
| 1137 |
} else {
|
| 1138 |
stw_raw(w ++, 0xf); /* unsigned flags */ |
| 1139 |
stw_raw(w ++, -1); /* s16 power_pin */ |
| 1140 |
stw_raw(w ++, -1); /* s16 switch_pin */ |
| 1141 |
stw_raw(w ++, -1); /* s16 wp_pin */ |
| 1142 |
stw_raw(w ++, 0); /* unsigned flags */ |
| 1143 |
stw_raw(w ++, 0); /* s16 power_pin */ |
| 1144 |
stw_raw(w ++, 0); /* s16 switch_pin */ |
| 1145 |
stw_raw(w ++, 0); /* s16 wp_pin */ |
| 1146 |
} |
| 1147 |
|
| 1148 |
stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
|
| 1149 |
stw_raw(w ++, 4); /* u16 len */ |
| 1150 |
stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
|
| 1151 |
w ++; |
| 1152 |
|
| 1153 |
partition = (model == 810) ? n810_part_info : n800_part_info;
|
| 1154 |
for (; partition->name; partition ++) {
|
| 1155 |
stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
|
| 1156 |
stw_raw(w ++, 28); /* u16 len */ |
| 1157 |
strcpy((void *) w, partition->name); /* char name[16] */ |
| 1158 |
l = (void *) (w + 8); |
| 1159 |
stl_raw(l ++, partition->size); /* unsigned int size */
|
| 1160 |
stl_raw(l ++, partition->offset); /* unsigned int offset */
|
| 1161 |
stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
|
| 1162 |
w = (void *) l;
|
| 1163 |
} |
| 1164 |
|
| 1165 |
stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
|
| 1166 |
stw_raw(w ++, 12); /* u16 len */ |
| 1167 |
#if 0
|
| 1168 |
strcpy((void *) w, "por"); /* char reason_str[12] */
|
| 1169 |
strcpy((void *) w, "charger"); /* char reason_str[12] */
|
| 1170 |
strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
|
| 1171 |
strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
|
| 1172 |
strcpy((void *) w, "mbus"); /* char reason_str[12] */
|
| 1173 |
strcpy((void *) w, "unknown"); /* char reason_str[12] */
|
| 1174 |
strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
|
| 1175 |
strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
|
| 1176 |
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
|
| 1177 |
strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
|
| 1178 |
#else
|
| 1179 |
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ |
| 1180 |
#endif
|
| 1181 |
w += 6;
|
| 1182 |
|
| 1183 |
tag = (model == 810) ? "RX-44" : "RX-34"; |
| 1184 |
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
|
| 1185 |
stw_raw(w ++, 24); /* u16 len */ |
| 1186 |
strcpy((void *) w, "product"); /* char component[12] */ |
| 1187 |
w += 6;
|
| 1188 |
strcpy((void *) w, tag); /* char version[12] */ |
| 1189 |
w += 6;
|
| 1190 |
|
| 1191 |
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
|
| 1192 |
stw_raw(w ++, 24); /* u16 len */ |
| 1193 |
strcpy((void *) w, "hw-build"); /* char component[12] */ |
| 1194 |
w += 6;
|
| 1195 |
strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */ |
| 1196 |
w += 6;
|
| 1197 |
|
| 1198 |
tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu"; |
| 1199 |
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
|
| 1200 |
stw_raw(w ++, 24); /* u16 len */ |
| 1201 |
strcpy((void *) w, "nolo"); /* char component[12] */ |
| 1202 |
w += 6;
|
| 1203 |
strcpy((void *) w, tag); /* char version[12] */ |
| 1204 |
w += 6;
|
| 1205 |
|
| 1206 |
return (void *) w - p; |
| 1207 |
} |
| 1208 |
|
| 1209 |
static int n800_atag_setup(struct arm_boot_info *info, void *p) |
| 1210 |
{
|
| 1211 |
return n8x0_atag_setup(p, 800); |
| 1212 |
} |
| 1213 |
|
| 1214 |
static int n810_atag_setup(struct arm_boot_info *info, void *p) |
| 1215 |
{
|
| 1216 |
return n8x0_atag_setup(p, 810); |
| 1217 |
} |
| 1218 |
|
| 1219 |
static void n8x0_init(ram_addr_t ram_size, const char *boot_device, |
| 1220 |
DisplayState *ds, const char *kernel_filename, |
| 1221 |
const char *kernel_cmdline, const char *initrd_filename, |
| 1222 |
const char *cpu_model, struct arm_boot_info *binfo, int model) |
| 1223 |
{
|
| 1224 |
struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s)); |
| 1225 |
int sdram_size = binfo->ram_size;
|
| 1226 |
int onenandram_size = 0x00010000; |
| 1227 |
|
| 1228 |
if (ram_size < sdram_size + onenandram_size + OMAP242X_SRAM_SIZE) {
|
| 1229 |
fprintf(stderr, "This architecture uses %i bytes of memory\n",
|
| 1230 |
sdram_size + onenandram_size + OMAP242X_SRAM_SIZE); |
| 1231 |
exit(1);
|
| 1232 |
} |
| 1233 |
|
| 1234 |
s->cpu = omap2420_mpu_init(sdram_size, NULL, cpu_model);
|
| 1235 |
|
| 1236 |
/* Setup peripherals
|
| 1237 |
*
|
| 1238 |
* Believed external peripherals layout in the N810:
|
| 1239 |
* (spi bus 1)
|
| 1240 |
* tsc2005
|
| 1241 |
* lcd_mipid
|
| 1242 |
* (spi bus 2)
|
| 1243 |
* Conexant cx3110x (WLAN)
|
| 1244 |
* optional: pc2400m (WiMAX)
|
| 1245 |
* (i2c bus 0)
|
| 1246 |
* TLV320AIC33 (audio codec)
|
| 1247 |
* TCM825x (camera by Toshiba)
|
| 1248 |
* lp5521 (clever LEDs)
|
| 1249 |
* tsl2563 (light sensor, hwmon, model 7, rev. 0)
|
| 1250 |
* lm8323 (keypad, manf 00, rev 04)
|
| 1251 |
* (i2c bus 1)
|
| 1252 |
* tmp105 (temperature sensor, hwmon)
|
| 1253 |
* menelaus (pm)
|
| 1254 |
* (somewhere on i2c - maybe N800-only)
|
| 1255 |
* tea5761 (FM tuner)
|
| 1256 |
* (serial 0)
|
| 1257 |
* GPS
|
| 1258 |
* (some serial port)
|
| 1259 |
* csr41814 (Bluetooth)
|
| 1260 |
*/
|
| 1261 |
n8x0_gpio_setup(s); |
| 1262 |
n8x0_nand_setup(s); |
| 1263 |
n8x0_i2c_setup(s); |
| 1264 |
if (model == 800) |
| 1265 |
n800_tsc_kbd_setup(s); |
| 1266 |
else if (model == 810) { |
| 1267 |
n810_tsc_setup(s); |
| 1268 |
n810_kbd_setup(s); |
| 1269 |
} |
| 1270 |
n8x0_spi_setup(s); |
| 1271 |
n8x0_dss_setup(s, ds); |
| 1272 |
n8x0_cbus_setup(s); |
| 1273 |
if (usb_enabled)
|
| 1274 |
n8x0_usb_setup(s); |
| 1275 |
|
| 1276 |
/* Setup initial (reset) machine state */
|
| 1277 |
|
| 1278 |
/* Start at the OneNAND bootloader. */
|
| 1279 |
s->cpu->env->regs[15] = 0; |
| 1280 |
|
| 1281 |
if (kernel_filename) {
|
| 1282 |
/* Or at the linux loader. */
|
| 1283 |
binfo->kernel_filename = kernel_filename; |
| 1284 |
binfo->kernel_cmdline = kernel_cmdline; |
| 1285 |
binfo->initrd_filename = initrd_filename; |
| 1286 |
arm_load_kernel(s->cpu->env, binfo); |
| 1287 |
|
| 1288 |
qemu_register_reset(n8x0_boot_init, s); |
| 1289 |
n8x0_boot_init(s); |
| 1290 |
} |
| 1291 |
|
| 1292 |
if (option_rom[0] && (boot_device[0] == 'n' || !kernel_filename)) { |
| 1293 |
/* No, wait, better start at the ROM. */
|
| 1294 |
s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000; |
| 1295 |
|
| 1296 |
/* This is intended for loading the `secondary.bin' program from
|
| 1297 |
* Nokia images (the NOLO bootloader). The entry point seems
|
| 1298 |
* to be at OMAP2_Q2_BASE + 0x400000.
|
| 1299 |
*
|
| 1300 |
* The `2nd.bin' files contain some kind of earlier boot code and
|
| 1301 |
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
|
| 1302 |
*
|
| 1303 |
* The code above is for loading the `zImage' file from Nokia
|
| 1304 |
* images. */
|
| 1305 |
printf("%i bytes of image loaded\n", load_image(option_rom[0], |
| 1306 |
phys_ram_base + 0x400000));
|
| 1307 |
|
| 1308 |
n800_setup_nolo_tags(phys_ram_base + sdram_size); |
| 1309 |
} |
| 1310 |
|
| 1311 |
dpy_resize(ds, 800, 480); |
| 1312 |
} |
| 1313 |
|
| 1314 |
static struct arm_boot_info n800_binfo = { |
| 1315 |
.loader_start = OMAP2_Q2_BASE, |
| 1316 |
/* Actually two chips of 0x4000000 bytes each */
|
| 1317 |
.ram_size = 0x08000000,
|
| 1318 |
.board_id = 0x4f7,
|
| 1319 |
.atag_board = n800_atag_setup, |
| 1320 |
}; |
| 1321 |
|
| 1322 |
static struct arm_boot_info n810_binfo = { |
| 1323 |
.loader_start = OMAP2_Q2_BASE, |
| 1324 |
/* Actually two chips of 0x4000000 bytes each */
|
| 1325 |
.ram_size = 0x08000000,
|
| 1326 |
/* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
|
| 1327 |
* used by some older versions of the bootloader and 5555 is used
|
| 1328 |
* instead (including versions that shipped with many devices). */
|
| 1329 |
.board_id = 0x60c,
|
| 1330 |
.atag_board = n810_atag_setup, |
| 1331 |
}; |
| 1332 |
|
| 1333 |
static void n800_init(ram_addr_t ram_size, int vga_ram_size, |
| 1334 |
const char *boot_device, DisplayState *ds, |
| 1335 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1336 |
const char *initrd_filename, const char *cpu_model) |
| 1337 |
{
|
| 1338 |
return n8x0_init(ram_size, boot_device, ds,
|
| 1339 |
kernel_filename, kernel_cmdline, initrd_filename, |
| 1340 |
cpu_model, &n800_binfo, 800);
|
| 1341 |
} |
| 1342 |
|
| 1343 |
static void n810_init(ram_addr_t ram_size, int vga_ram_size, |
| 1344 |
const char *boot_device, DisplayState *ds, |
| 1345 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1346 |
const char *initrd_filename, const char *cpu_model) |
| 1347 |
{
|
| 1348 |
return n8x0_init(ram_size, boot_device, ds,
|
| 1349 |
kernel_filename, kernel_cmdline, initrd_filename, |
| 1350 |
cpu_model, &n810_binfo, 810);
|
| 1351 |
} |
| 1352 |
|
| 1353 |
QEMUMachine n800_machine = {
|
| 1354 |
"n800",
|
| 1355 |
"Nokia N800 tablet aka. RX-34 (OMAP2420)",
|
| 1356 |
n800_init, |
| 1357 |
(0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED, |
| 1358 |
}; |
| 1359 |
|
| 1360 |
QEMUMachine n810_machine = {
|
| 1361 |
"n810",
|
| 1362 |
"Nokia N810 tablet aka. RX-44 (OMAP2420)",
|
| 1363 |
n810_init, |
| 1364 |
(0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED, |
| 1365 |
}; |