root / target-mips / translate_init.c @ 5efbfedd
History | View | Annotate | Download (5.8 kB)
1 | 33d68b5f | ths | /*
|
---|---|---|---|
2 | 33d68b5f | ths | * MIPS emulation for qemu: CPU initialisation routines.
|
3 | 33d68b5f | ths | *
|
4 | 33d68b5f | ths | * Copyright (c) 2004-2005 Jocelyn Mayer
|
5 | 33d68b5f | ths | * Copyright (c) 2007 Herve Poussineau
|
6 | 33d68b5f | ths | *
|
7 | 33d68b5f | ths | * This library is free software; you can redistribute it and/or
|
8 | 33d68b5f | ths | * modify it under the terms of the GNU Lesser General Public
|
9 | 33d68b5f | ths | * License as published by the Free Software Foundation; either
|
10 | 33d68b5f | ths | * version 2 of the License, or (at your option) any later version.
|
11 | 33d68b5f | ths | *
|
12 | 33d68b5f | ths | * This library is distributed in the hope that it will be useful,
|
13 | 33d68b5f | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 | 33d68b5f | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
15 | 33d68b5f | ths | * Lesser General Public License for more details.
|
16 | 33d68b5f | ths | *
|
17 | 33d68b5f | ths | * You should have received a copy of the GNU Lesser General Public
|
18 | 33d68b5f | ths | * License along with this library; if not, write to the Free Software
|
19 | 33d68b5f | ths | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
20 | 33d68b5f | ths | */
|
21 | 33d68b5f | ths | |
22 | 3953d786 | ths | /* CPU / CPU family specific config register values. */
|
23 | 3953d786 | ths | |
24 | 3953d786 | ths | /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
|
25 | 3953d786 | ths | uncached coherency */
|
26 | 3953d786 | ths | #define MIPS_CONFIG0 \
|
27 | 3953d786 | ths | ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \ |
28 | 3953d786 | ths | (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \ |
29 | 3953d786 | ths | (0x2 << CP0C0_K0))
|
30 | 3953d786 | ths | |
31 | 3953d786 | ths | /* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
|
32 | 3953d786 | ths | 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
|
33 | 3953d786 | ths | no coprocessor2 attached, no MDMX support attached,
|
34 | 3953d786 | ths | no performance counters, watch registers present,
|
35 | 3953d786 | ths | no code compression, EJTAG present, no FPU */
|
36 | 3953d786 | ths | #define MIPS_CONFIG1 \
|
37 | 3953d786 | ths | ((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \ |
38 | 3953d786 | ths | (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \ |
39 | 3953d786 | ths | (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \ |
40 | 3953d786 | ths | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
41 | 3953d786 | ths | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
42 | 3953d786 | ths | (0 << CP0C1_FP))
|
43 | 3953d786 | ths | |
44 | 3953d786 | ths | /* Have config3, no tertiary/secondary caches implemented */
|
45 | 3953d786 | ths | #define MIPS_CONFIG2 \
|
46 | 3953d786 | ths | ((1 << CP0C2_M))
|
47 | 3953d786 | ths | |
48 | 3953d786 | ths | /* No config4, no DSP ASE, no large physaddr,
|
49 | 3953d786 | ths | no external interrupt controller, no vectored interupts,
|
50 | 3953d786 | ths | no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
|
51 | 3953d786 | ths | #define MIPS_CONFIG3 \
|
52 | 3953d786 | ths | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
53 | 3953d786 | ths | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
54 | 3953d786 | ths | (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
55 | 3953d786 | ths | |
56 | 3953d786 | ths | /* Define a implementation number of 1.
|
57 | 3953d786 | ths | Define a major version 1, minor version 0. */
|
58 | 3953d786 | ths | #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) |
59 | 3953d786 | ths | |
60 | 3953d786 | ths | |
61 | 33d68b5f | ths | struct mips_def_t {
|
62 | 33d68b5f | ths | const unsigned char *name; |
63 | 33d68b5f | ths | int32_t CP0_PRid; |
64 | 33d68b5f | ths | int32_t CP0_Config0; |
65 | 33d68b5f | ths | int32_t CP0_Config1; |
66 | 3953d786 | ths | int32_t CP0_Config2; |
67 | 3953d786 | ths | int32_t CP0_Config3; |
68 | 34ee2ede | ths | int32_t CP0_Config6; |
69 | 34ee2ede | ths | int32_t CP0_Config7; |
70 | 3953d786 | ths | int32_t CP1_fcr0; |
71 | 33d68b5f | ths | }; |
72 | 33d68b5f | ths | |
73 | 33d68b5f | ths | /*****************************************************************************/
|
74 | 33d68b5f | ths | /* MIPS CPU definitions */
|
75 | 33d68b5f | ths | static mips_def_t mips_defs[] =
|
76 | 33d68b5f | ths | { |
77 | 33d68b5f | ths | #ifndef MIPS_HAS_MIPS64
|
78 | 33d68b5f | ths | { |
79 | 33d68b5f | ths | .name = "4Kc",
|
80 | 33d68b5f | ths | .CP0_PRid = 0x00018000,
|
81 | 33d68b5f | ths | .CP0_Config0 = MIPS_CONFIG0, |
82 | 33d68b5f | ths | .CP0_Config1 = MIPS_CONFIG1, |
83 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
84 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
85 | 3953d786 | ths | .CP1_fcr0 = MIPS_FCR0, |
86 | 33d68b5f | ths | }, |
87 | 33d68b5f | ths | { |
88 | 34ee2ede | ths | .name = "4KEcR1",
|
89 | 33d68b5f | ths | .CP0_PRid = 0x00018400,
|
90 | 34ee2ede | ths | .CP0_Config0 = MIPS_CONFIG0, |
91 | 34ee2ede | ths | .CP0_Config1 = MIPS_CONFIG1, |
92 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |
93 | 34ee2ede | ths | .CP0_Config3 = MIPS_CONFIG3, |
94 | 34ee2ede | ths | .CP1_fcr0 = MIPS_FCR0, |
95 | 34ee2ede | ths | }, |
96 | 34ee2ede | ths | { |
97 | 34ee2ede | ths | .name = "4KEc",
|
98 | 34ee2ede | ths | .CP0_PRid = 0x00019000,
|
99 | 34ee2ede | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
|
100 | 34ee2ede | ths | .CP0_Config1 = MIPS_CONFIG1, |
101 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |
102 | 34ee2ede | ths | .CP0_Config3 = MIPS_CONFIG3, |
103 | 34ee2ede | ths | .CP1_fcr0 = MIPS_FCR0, |
104 | 34ee2ede | ths | }, |
105 | 34ee2ede | ths | { |
106 | 34ee2ede | ths | .name = "24Kc",
|
107 | 34ee2ede | ths | .CP0_PRid = 0x00019300,
|
108 | 33d68b5f | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
|
109 | 33d68b5f | ths | .CP0_Config1 = MIPS_CONFIG1, |
110 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
111 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
112 | 3953d786 | ths | .CP1_fcr0 = MIPS_FCR0, |
113 | 33d68b5f | ths | }, |
114 | 33d68b5f | ths | { |
115 | 33d68b5f | ths | .name = "24Kf",
|
116 | 33d68b5f | ths | .CP0_PRid = 0x00019300,
|
117 | 33d68b5f | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
|
118 | 33d68b5f | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
|
119 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
120 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
121 | 3953d786 | ths | .CP1_fcr0 = MIPS_FCR0, |
122 | 33d68b5f | ths | }, |
123 | 33d68b5f | ths | #else
|
124 | 33d68b5f | ths | { |
125 | 33d68b5f | ths | .name = "R4000",
|
126 | 33d68b5f | ths | .CP0_PRid = 0x00000400,
|
127 | 33d68b5f | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
|
128 | 33d68b5f | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
|
129 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
130 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
131 | 3953d786 | ths | .CP1_fcr0 = MIPS_FCR0, |
132 | 33d68b5f | ths | }, |
133 | 33d68b5f | ths | #endif
|
134 | 33d68b5f | ths | }; |
135 | 33d68b5f | ths | |
136 | 33d68b5f | ths | int mips_find_by_name (const unsigned char *name, mips_def_t **def) |
137 | 33d68b5f | ths | { |
138 | 33d68b5f | ths | int i, ret;
|
139 | 33d68b5f | ths | |
140 | 33d68b5f | ths | ret = -1;
|
141 | 33d68b5f | ths | *def = NULL;
|
142 | 33d68b5f | ths | for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) { |
143 | 33d68b5f | ths | if (strcasecmp(name, mips_defs[i].name) == 0) { |
144 | 33d68b5f | ths | *def = &mips_defs[i]; |
145 | 33d68b5f | ths | ret = 0;
|
146 | 33d68b5f | ths | break;
|
147 | 33d68b5f | ths | } |
148 | 33d68b5f | ths | } |
149 | 33d68b5f | ths | |
150 | 33d68b5f | ths | return ret;
|
151 | 33d68b5f | ths | } |
152 | 33d68b5f | ths | |
153 | 33d68b5f | ths | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
154 | 33d68b5f | ths | { |
155 | 33d68b5f | ths | int i;
|
156 | 33d68b5f | ths | |
157 | 33d68b5f | ths | for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) { |
158 | 33d68b5f | ths | (*cpu_fprintf)(f, "MIPS '%s'\n",
|
159 | 33d68b5f | ths | mips_defs[i].name); |
160 | 33d68b5f | ths | } |
161 | 33d68b5f | ths | } |
162 | 33d68b5f | ths | |
163 | 33d68b5f | ths | int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
|
164 | 33d68b5f | ths | { |
165 | 33d68b5f | ths | if (!def)
|
166 | 33d68b5f | ths | cpu_abort(env, "Unable to find MIPS CPU definition\n");
|
167 | 33d68b5f | ths | env->CP0_PRid = def->CP0_PRid; |
168 | 3953d786 | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
169 | 3953d786 | ths | env->CP0_Config0 = def->CP0_Config0 | (1 << CP0C0_BE);
|
170 | 3953d786 | ths | #else
|
171 | 33d68b5f | ths | env->CP0_Config0 = def->CP0_Config0; |
172 | 3953d786 | ths | #endif
|
173 | 33d68b5f | ths | env->CP0_Config1 = def->CP0_Config1; |
174 | 3953d786 | ths | env->CP0_Config2 = def->CP0_Config2; |
175 | 3953d786 | ths | env->CP0_Config3 = def->CP0_Config3; |
176 | 34ee2ede | ths | env->CP0_Config6 = def->CP0_Config6; |
177 | 34ee2ede | ths | env->CP0_Config7 = def->CP0_Config7; |
178 | 3953d786 | ths | env->fcr0 = def->CP1_fcr0; |
179 | 33d68b5f | ths | return 0; |
180 | 33d68b5f | ths | } |