Revision 5f68f5ae target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 1606 | 1606 |
switch (opc) {
|
| 1607 | 1607 |
#if defined(TARGET_MIPS64) |
| 1608 | 1608 |
case OPC_LWU: |
| 1609 |
tcg_gen_qemu_ld32u(t0, t0, ctx->mem_idx);
|
|
| 1609 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
|
|
| 1610 | 1610 |
gen_store_gpr(t0, rt); |
| 1611 | 1611 |
opn = "lwu"; |
| 1612 | 1612 |
break; |
| 1613 | 1613 |
case OPC_LD: |
| 1614 |
tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
|
|
| 1614 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
|
|
| 1615 | 1615 |
gen_store_gpr(t0, rt); |
| 1616 | 1616 |
opn = "ld"; |
| 1617 | 1617 |
break; |
| ... | ... | |
| 1629 | 1629 |
#endif |
| 1630 | 1630 |
tcg_gen_shli_tl(t1, t1, 3); |
| 1631 | 1631 |
tcg_gen_andi_tl(t0, t0, ~7); |
| 1632 |
tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
|
|
| 1632 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
|
|
| 1633 | 1633 |
tcg_gen_shl_tl(t0, t0, t1); |
| 1634 | 1634 |
tcg_gen_xori_tl(t1, t1, 63); |
| 1635 | 1635 |
t2 = tcg_const_tl(0x7fffffffffffffffull); |
| ... | ... | |
| 1650 | 1650 |
#endif |
| 1651 | 1651 |
tcg_gen_shli_tl(t1, t1, 3); |
| 1652 | 1652 |
tcg_gen_andi_tl(t0, t0, ~7); |
| 1653 |
tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
|
|
| 1653 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
|
|
| 1654 | 1654 |
tcg_gen_shr_tl(t0, t0, t1); |
| 1655 | 1655 |
tcg_gen_xori_tl(t1, t1, 63); |
| 1656 | 1656 |
t2 = tcg_const_tl(0xfffffffffffffffeull); |
| ... | ... | |
| 1667 | 1667 |
t1 = tcg_const_tl(pc_relative_pc(ctx)); |
| 1668 | 1668 |
gen_op_addr_add(ctx, t0, t0, t1); |
| 1669 | 1669 |
tcg_temp_free(t1); |
| 1670 |
tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
|
|
| 1670 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
|
|
| 1671 | 1671 |
gen_store_gpr(t0, rt); |
| 1672 | 1672 |
opn = "ldpc"; |
| 1673 | 1673 |
break; |
| ... | ... | |
| 1676 | 1676 |
t1 = tcg_const_tl(pc_relative_pc(ctx)); |
| 1677 | 1677 |
gen_op_addr_add(ctx, t0, t0, t1); |
| 1678 | 1678 |
tcg_temp_free(t1); |
| 1679 |
tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
|
|
| 1679 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
|
|
| 1680 | 1680 |
gen_store_gpr(t0, rt); |
| 1681 | 1681 |
opn = "lwpc"; |
| 1682 | 1682 |
break; |
| 1683 | 1683 |
case OPC_LW: |
| 1684 |
tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
|
|
| 1684 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
|
|
| 1685 | 1685 |
gen_store_gpr(t0, rt); |
| 1686 | 1686 |
opn = "lw"; |
| 1687 | 1687 |
break; |
| 1688 | 1688 |
case OPC_LH: |
| 1689 |
tcg_gen_qemu_ld16s(t0, t0, ctx->mem_idx);
|
|
| 1689 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
|
|
| 1690 | 1690 |
gen_store_gpr(t0, rt); |
| 1691 | 1691 |
opn = "lh"; |
| 1692 | 1692 |
break; |
| 1693 | 1693 |
case OPC_LHU: |
| 1694 |
tcg_gen_qemu_ld16u(t0, t0, ctx->mem_idx);
|
|
| 1694 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW);
|
|
| 1695 | 1695 |
gen_store_gpr(t0, rt); |
| 1696 | 1696 |
opn = "lhu"; |
| 1697 | 1697 |
break; |
| 1698 | 1698 |
case OPC_LB: |
| 1699 |
tcg_gen_qemu_ld8s(t0, t0, ctx->mem_idx);
|
|
| 1699 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
|
|
| 1700 | 1700 |
gen_store_gpr(t0, rt); |
| 1701 | 1701 |
opn = "lb"; |
| 1702 | 1702 |
break; |
| 1703 | 1703 |
case OPC_LBU: |
| 1704 |
tcg_gen_qemu_ld8u(t0, t0, ctx->mem_idx);
|
|
| 1704 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
|
|
| 1705 | 1705 |
gen_store_gpr(t0, rt); |
| 1706 | 1706 |
opn = "lbu"; |
| 1707 | 1707 |
break; |
| ... | ... | |
| 1713 | 1713 |
#endif |
| 1714 | 1714 |
tcg_gen_shli_tl(t1, t1, 3); |
| 1715 | 1715 |
tcg_gen_andi_tl(t0, t0, ~3); |
| 1716 |
tcg_gen_qemu_ld32u(t0, t0, ctx->mem_idx);
|
|
| 1716 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
|
|
| 1717 | 1717 |
tcg_gen_shl_tl(t0, t0, t1); |
| 1718 | 1718 |
tcg_gen_xori_tl(t1, t1, 31); |
| 1719 | 1719 |
t2 = tcg_const_tl(0x7fffffffull); |
| ... | ... | |
| 1735 | 1735 |
#endif |
| 1736 | 1736 |
tcg_gen_shli_tl(t1, t1, 3); |
| 1737 | 1737 |
tcg_gen_andi_tl(t0, t0, ~3); |
| 1738 |
tcg_gen_qemu_ld32u(t0, t0, ctx->mem_idx);
|
|
| 1738 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
|
|
| 1739 | 1739 |
tcg_gen_shr_tl(t0, t0, t1); |
| 1740 | 1740 |
tcg_gen_xori_tl(t1, t1, 31); |
| 1741 | 1741 |
t2 = tcg_const_tl(0xfffffffeull); |
| ... | ... | |
| 1774 | 1774 |
switch (opc) {
|
| 1775 | 1775 |
#if defined(TARGET_MIPS64) |
| 1776 | 1776 |
case OPC_SD: |
| 1777 |
tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
|
|
| 1777 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
|
|
| 1778 | 1778 |
opn = "sd"; |
| 1779 | 1779 |
break; |
| 1780 | 1780 |
case OPC_SDL: |
| ... | ... | |
| 1789 | 1789 |
break; |
| 1790 | 1790 |
#endif |
| 1791 | 1791 |
case OPC_SW: |
| 1792 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
|
|
| 1792 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
|
|
| 1793 | 1793 |
opn = "sw"; |
| 1794 | 1794 |
break; |
| 1795 | 1795 |
case OPC_SH: |
| 1796 |
tcg_gen_qemu_st16(t1, t0, ctx->mem_idx);
|
|
| 1796 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW);
|
|
| 1797 | 1797 |
opn = "sh"; |
| 1798 | 1798 |
break; |
| 1799 | 1799 |
case OPC_SB: |
| 1800 |
tcg_gen_qemu_st8(t1, t0, ctx->mem_idx);
|
|
| 1800 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8);
|
|
| 1801 | 1801 |
opn = "sb"; |
| 1802 | 1802 |
break; |
| 1803 | 1803 |
case OPC_SWL: |
| ... | ... | |
| 1868 | 1868 |
case OPC_LWC1: |
| 1869 | 1869 |
{
|
| 1870 | 1870 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 1871 |
|
|
| 1872 |
tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); |
|
| 1873 |
tcg_gen_trunc_tl_i32(fp0, t0); |
|
| 1871 |
tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL); |
|
| 1874 | 1872 |
gen_store_fpr32(fp0, ft); |
| 1875 | 1873 |
tcg_temp_free_i32(fp0); |
| 1876 | 1874 |
} |
| ... | ... | |
| 1879 | 1877 |
case OPC_SWC1: |
| 1880 | 1878 |
{
|
| 1881 | 1879 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 1882 |
TCGv t1 = tcg_temp_new(); |
|
| 1883 |
|
|
| 1884 | 1880 |
gen_load_fpr32(fp0, ft); |
| 1885 |
tcg_gen_extu_i32_tl(t1, fp0); |
|
| 1886 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); |
|
| 1887 |
tcg_temp_free(t1); |
|
| 1881 |
tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); |
|
| 1888 | 1882 |
tcg_temp_free_i32(fp0); |
| 1889 | 1883 |
} |
| 1890 | 1884 |
opn = "swc1"; |
| ... | ... | |
| 1892 | 1886 |
case OPC_LDC1: |
| 1893 | 1887 |
{
|
| 1894 | 1888 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 1895 |
|
|
| 1896 |
tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); |
|
| 1889 |
tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ); |
|
| 1897 | 1890 |
gen_store_fpr64(ctx, fp0, ft); |
| 1898 | 1891 |
tcg_temp_free_i64(fp0); |
| 1899 | 1892 |
} |
| ... | ... | |
| 1902 | 1895 |
case OPC_SDC1: |
| 1903 | 1896 |
{
|
| 1904 | 1897 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 1905 |
|
|
| 1906 | 1898 |
gen_load_fpr64(ctx, fp0, ft); |
| 1907 |
tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
|
|
| 1899 |
tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
|
|
| 1908 | 1900 |
tcg_temp_free_i64(fp0); |
| 1909 | 1901 |
} |
| 1910 | 1902 |
opn = "sdc1"; |
| ... | ... | |
| 8652 | 8644 |
{
|
| 8653 | 8645 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 8654 | 8646 |
|
| 8655 |
tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
|
|
| 8647 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
|
|
| 8656 | 8648 |
tcg_gen_trunc_tl_i32(fp0, t0); |
| 8657 | 8649 |
gen_store_fpr32(fp0, fd); |
| 8658 | 8650 |
tcg_temp_free_i32(fp0); |
| ... | ... | |
| 8664 | 8656 |
check_cp1_registers(ctx, fd); |
| 8665 | 8657 |
{
|
| 8666 | 8658 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 8667 |
|
|
| 8668 |
tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); |
|
| 8659 |
tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ); |
|
| 8669 | 8660 |
gen_store_fpr64(ctx, fp0, fd); |
| 8670 | 8661 |
tcg_temp_free_i64(fp0); |
| 8671 | 8662 |
} |
| ... | ... | |
| 8677 | 8668 |
{
|
| 8678 | 8669 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 8679 | 8670 |
|
| 8680 |
tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
|
|
| 8671 |
tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
|
|
| 8681 | 8672 |
gen_store_fpr64(ctx, fp0, fd); |
| 8682 | 8673 |
tcg_temp_free_i64(fp0); |
| 8683 | 8674 |
} |
| ... | ... | |
| 8687 | 8678 |
check_cop1x(ctx); |
| 8688 | 8679 |
{
|
| 8689 | 8680 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 8690 |
TCGv t1 = tcg_temp_new(); |
|
| 8691 |
|
|
| 8692 | 8681 |
gen_load_fpr32(fp0, fs); |
| 8693 |
tcg_gen_extu_i32_tl(t1, fp0); |
|
| 8694 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); |
|
| 8682 |
tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); |
|
| 8695 | 8683 |
tcg_temp_free_i32(fp0); |
| 8696 |
tcg_temp_free(t1); |
|
| 8697 | 8684 |
} |
| 8698 | 8685 |
opn = "swxc1"; |
| 8699 | 8686 |
store = 1; |
| ... | ... | |
| 8703 | 8690 |
check_cp1_registers(ctx, fs); |
| 8704 | 8691 |
{
|
| 8705 | 8692 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 8706 |
|
|
| 8707 | 8693 |
gen_load_fpr64(ctx, fp0, fs); |
| 8708 |
tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
|
|
| 8694 |
tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
|
|
| 8709 | 8695 |
tcg_temp_free_i64(fp0); |
| 8710 | 8696 |
} |
| 8711 | 8697 |
opn = "sdxc1"; |
| ... | ... | |
| 8716 | 8702 |
tcg_gen_andi_tl(t0, t0, ~0x7); |
| 8717 | 8703 |
{
|
| 8718 | 8704 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 8719 |
|
|
| 8720 | 8705 |
gen_load_fpr64(ctx, fp0, fs); |
| 8721 |
tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
|
|
| 8706 |
tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
|
|
| 8722 | 8707 |
tcg_temp_free_i64(fp0); |
| 8723 | 8708 |
} |
| 8724 | 8709 |
opn = "suxc1"; |
| ... | ... | |
| 9286 | 9271 |
case 4: |
| 9287 | 9272 |
gen_base_offset_addr(ctx, t0, 29, 12); |
| 9288 | 9273 |
gen_load_gpr(t1, 7); |
| 9289 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
|
|
| 9274 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
|
|
| 9290 | 9275 |
/* Fall through */ |
| 9291 | 9276 |
case 3: |
| 9292 | 9277 |
gen_base_offset_addr(ctx, t0, 29, 8); |
| 9293 | 9278 |
gen_load_gpr(t1, 6); |
| 9294 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
|
|
| 9279 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
|
|
| 9295 | 9280 |
/* Fall through */ |
| 9296 | 9281 |
case 2: |
| 9297 | 9282 |
gen_base_offset_addr(ctx, t0, 29, 4); |
| 9298 | 9283 |
gen_load_gpr(t1, 5); |
| 9299 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
|
|
| 9284 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
|
|
| 9300 | 9285 |
/* Fall through */ |
| 9301 | 9286 |
case 1: |
| 9302 | 9287 |
gen_base_offset_addr(ctx, t0, 29, 0); |
| 9303 | 9288 |
gen_load_gpr(t1, 4); |
| 9304 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
|
|
| 9289 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
|
|
| 9305 | 9290 |
} |
| 9306 | 9291 |
|
| 9307 | 9292 |
gen_load_gpr(t0, 29); |
| 9308 | 9293 |
|
| 9309 |
#define DECR_AND_STORE(reg) do { \
|
|
| 9310 |
tcg_gen_subi_tl(t0, t0, 4); \ |
|
| 9311 |
gen_load_gpr(t1, reg); \ |
|
| 9312 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); \
|
|
| 9294 |
#define DECR_AND_STORE(reg) do { \
|
|
| 9295 |
tcg_gen_subi_tl(t0, t0, 4); \
|
|
| 9296 |
gen_load_gpr(t1, reg); \
|
|
| 9297 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \
|
|
| 9313 | 9298 |
} while (0) |
| 9314 | 9299 |
|
| 9315 | 9300 |
if (do_ra) {
|
| ... | ... | |
| 9407 | 9392 |
|
| 9408 | 9393 |
tcg_gen_addi_tl(t0, cpu_gpr[29], framesize); |
| 9409 | 9394 |
|
| 9410 |
#define DECR_AND_LOAD(reg) do { \
|
|
| 9411 |
tcg_gen_subi_tl(t0, t0, 4); \ |
|
| 9412 |
tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx); \
|
|
| 9413 |
gen_store_gpr(t1, reg); \ |
|
| 9395 |
#define DECR_AND_LOAD(reg) do { \
|
|
| 9396 |
tcg_gen_subi_tl(t0, t0, 4); \
|
|
| 9397 |
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \
|
|
| 9398 |
gen_store_gpr(t1, reg); \
|
|
| 9414 | 9399 |
} while (0) |
| 9415 | 9400 |
|
| 9416 | 9401 |
if (do_ra) {
|
| ... | ... | |
| 10935 | 10920 |
gen_op_addr_add(ctx, t0, t1, t0); |
| 10936 | 10921 |
} |
| 10937 | 10922 |
|
| 10938 |
tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
|
|
| 10923 |
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
|
|
| 10939 | 10924 |
gen_store_gpr(t1, rd); |
| 10940 | 10925 |
|
| 10941 | 10926 |
tcg_temp_free(t0); |
| ... | ... | |
| 10964 | 10949 |
generate_exception(ctx, EXCP_RI); |
| 10965 | 10950 |
return; |
| 10966 | 10951 |
} |
| 10967 |
tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
|
|
| 10952 |
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
|
|
| 10968 | 10953 |
gen_store_gpr(t1, rd); |
| 10969 | 10954 |
tcg_gen_movi_tl(t1, 4); |
| 10970 | 10955 |
gen_op_addr_add(ctx, t0, t0, t1); |
| 10971 |
tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
|
|
| 10956 |
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
|
|
| 10972 | 10957 |
gen_store_gpr(t1, rd+1); |
| 10973 | 10958 |
opn = "lwp"; |
| 10974 | 10959 |
break; |
| 10975 | 10960 |
case SWP: |
| 10976 | 10961 |
gen_load_gpr(t1, rd); |
| 10977 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
|
|
| 10962 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
|
|
| 10978 | 10963 |
tcg_gen_movi_tl(t1, 4); |
| 10979 | 10964 |
gen_op_addr_add(ctx, t0, t0, t1); |
| 10980 | 10965 |
gen_load_gpr(t1, rd+1); |
| 10981 |
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
|
|
| 10966 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
|
|
| 10982 | 10967 |
opn = "swp"; |
| 10983 | 10968 |
break; |
| 10984 | 10969 |
#ifdef TARGET_MIPS64 |
| ... | ... | |
| 10987 | 10972 |
generate_exception(ctx, EXCP_RI); |
| 10988 | 10973 |
return; |
| 10989 | 10974 |
} |
| 10990 |
tcg_gen_qemu_ld64(t1, t0, ctx->mem_idx);
|
|
| 10975 |
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
|
|
| 10991 | 10976 |
gen_store_gpr(t1, rd); |
| 10992 | 10977 |
tcg_gen_movi_tl(t1, 8); |
| 10993 | 10978 |
gen_op_addr_add(ctx, t0, t0, t1); |
| 10994 |
tcg_gen_qemu_ld64(t1, t0, ctx->mem_idx);
|
|
| 10979 |
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
|
|
| 10995 | 10980 |
gen_store_gpr(t1, rd+1); |
| 10996 | 10981 |
opn = "ldp"; |
| 10997 | 10982 |
break; |
| 10998 | 10983 |
case SDP: |
| 10999 | 10984 |
gen_load_gpr(t1, rd); |
| 11000 |
tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
|
|
| 10985 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
|
|
| 11001 | 10986 |
tcg_gen_movi_tl(t1, 8); |
| 11002 | 10987 |
gen_op_addr_add(ctx, t0, t0, t1); |
| 11003 | 10988 |
gen_load_gpr(t1, rd+1); |
| 11004 |
tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
|
|
| 10989 |
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
|
|
| 11005 | 10990 |
opn = "sdp"; |
| 11006 | 10991 |
break; |
| 11007 | 10992 |
#endif |
| ... | ... | |
| 12672 | 12657 |
|
| 12673 | 12658 |
switch (opc) {
|
| 12674 | 12659 |
case OPC_LBUX: |
| 12675 |
tcg_gen_qemu_ld8u(t0, t0, ctx->mem_idx);
|
|
| 12660 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
|
|
| 12676 | 12661 |
gen_store_gpr(t0, rd); |
| 12677 | 12662 |
opn = "lbux"; |
| 12678 | 12663 |
break; |
| 12679 | 12664 |
case OPC_LHX: |
| 12680 |
tcg_gen_qemu_ld16s(t0, t0, ctx->mem_idx);
|
|
| 12665 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
|
|
| 12681 | 12666 |
gen_store_gpr(t0, rd); |
| 12682 | 12667 |
opn = "lhx"; |
| 12683 | 12668 |
break; |
| 12684 | 12669 |
case OPC_LWX: |
| 12685 |
tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
|
|
| 12670 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
|
|
| 12686 | 12671 |
gen_store_gpr(t0, rd); |
| 12687 | 12672 |
opn = "lwx"; |
| 12688 | 12673 |
break; |
| 12689 | 12674 |
#if defined(TARGET_MIPS64) |
| 12690 | 12675 |
case OPC_LDX: |
| 12691 |
tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
|
|
| 12676 |
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
|
|
| 12692 | 12677 |
gen_store_gpr(t0, rd); |
| 12693 | 12678 |
opn = "ldx"; |
| 12694 | 12679 |
break; |
Also available in: Unified diff