root / cputlb.c @ 5f8ae8e2
History | View | Annotate | Download (10.9 kB)
1 | 0cac1b66 | Blue Swirl | /*
|
---|---|---|---|
2 | 0cac1b66 | Blue Swirl | * Common CPU TLB handling
|
3 | 0cac1b66 | Blue Swirl | *
|
4 | 0cac1b66 | Blue Swirl | * Copyright (c) 2003 Fabrice Bellard
|
5 | 0cac1b66 | Blue Swirl | *
|
6 | 0cac1b66 | Blue Swirl | * This library is free software; you can redistribute it and/or
|
7 | 0cac1b66 | Blue Swirl | * modify it under the terms of the GNU Lesser General Public
|
8 | 0cac1b66 | Blue Swirl | * License as published by the Free Software Foundation; either
|
9 | 0cac1b66 | Blue Swirl | * version 2 of the License, or (at your option) any later version.
|
10 | 0cac1b66 | Blue Swirl | *
|
11 | 0cac1b66 | Blue Swirl | * This library is distributed in the hope that it will be useful,
|
12 | 0cac1b66 | Blue Swirl | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 0cac1b66 | Blue Swirl | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 0cac1b66 | Blue Swirl | * Lesser General Public License for more details.
|
15 | 0cac1b66 | Blue Swirl | *
|
16 | 0cac1b66 | Blue Swirl | * You should have received a copy of the GNU Lesser General Public
|
17 | 0cac1b66 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 | 0cac1b66 | Blue Swirl | */
|
19 | 0cac1b66 | Blue Swirl | |
20 | 0cac1b66 | Blue Swirl | #include "config.h" |
21 | 0cac1b66 | Blue Swirl | #include "cpu.h" |
22 | 0cac1b66 | Blue Swirl | #include "exec-all.h" |
23 | 0cac1b66 | Blue Swirl | #include "memory.h" |
24 | ac1970fb | Avi Kivity | #include "exec-memory.h" |
25 | 0cac1b66 | Blue Swirl | |
26 | 0cac1b66 | Blue Swirl | #include "cputlb.h" |
27 | 0cac1b66 | Blue Swirl | |
28 | 7762c2c1 | Avi Kivity | #include "memory-internal.h" |
29 | 0cac1b66 | Blue Swirl | |
30 | 0cac1b66 | Blue Swirl | //#define DEBUG_TLB
|
31 | 0cac1b66 | Blue Swirl | //#define DEBUG_TLB_CHECK
|
32 | 0cac1b66 | Blue Swirl | |
33 | 0cac1b66 | Blue Swirl | /* statistics */
|
34 | 0cac1b66 | Blue Swirl | int tlb_flush_count;
|
35 | 0cac1b66 | Blue Swirl | |
36 | 0cac1b66 | Blue Swirl | static const CPUTLBEntry s_cputlb_empty_entry = { |
37 | 0cac1b66 | Blue Swirl | .addr_read = -1,
|
38 | 0cac1b66 | Blue Swirl | .addr_write = -1,
|
39 | 0cac1b66 | Blue Swirl | .addr_code = -1,
|
40 | 0cac1b66 | Blue Swirl | .addend = -1,
|
41 | 0cac1b66 | Blue Swirl | }; |
42 | 0cac1b66 | Blue Swirl | |
43 | 0cac1b66 | Blue Swirl | /* NOTE:
|
44 | 0cac1b66 | Blue Swirl | * If flush_global is true (the usual case), flush all tlb entries.
|
45 | 0cac1b66 | Blue Swirl | * If flush_global is false, flush (at least) all tlb entries not
|
46 | 0cac1b66 | Blue Swirl | * marked global.
|
47 | 0cac1b66 | Blue Swirl | *
|
48 | 0cac1b66 | Blue Swirl | * Since QEMU doesn't currently implement a global/not-global flag
|
49 | 0cac1b66 | Blue Swirl | * for tlb entries, at the moment tlb_flush() will also flush all
|
50 | 0cac1b66 | Blue Swirl | * tlb entries in the flush_global == false case. This is OK because
|
51 | 0cac1b66 | Blue Swirl | * CPU architectures generally permit an implementation to drop
|
52 | 0cac1b66 | Blue Swirl | * entries from the TLB at any time, so flushing more entries than
|
53 | 0cac1b66 | Blue Swirl | * required is only an efficiency issue, not a correctness issue.
|
54 | 0cac1b66 | Blue Swirl | */
|
55 | 0cac1b66 | Blue Swirl | void tlb_flush(CPUArchState *env, int flush_global) |
56 | 0cac1b66 | Blue Swirl | { |
57 | 0cac1b66 | Blue Swirl | int i;
|
58 | 0cac1b66 | Blue Swirl | |
59 | 0cac1b66 | Blue Swirl | #if defined(DEBUG_TLB)
|
60 | 0cac1b66 | Blue Swirl | printf("tlb_flush:\n");
|
61 | 0cac1b66 | Blue Swirl | #endif
|
62 | 0cac1b66 | Blue Swirl | /* must reset current TB so that interrupts cannot modify the
|
63 | 0cac1b66 | Blue Swirl | links while we are modifying them */
|
64 | 0cac1b66 | Blue Swirl | env->current_tb = NULL;
|
65 | 0cac1b66 | Blue Swirl | |
66 | 0cac1b66 | Blue Swirl | for (i = 0; i < CPU_TLB_SIZE; i++) { |
67 | 0cac1b66 | Blue Swirl | int mmu_idx;
|
68 | 0cac1b66 | Blue Swirl | |
69 | 0cac1b66 | Blue Swirl | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
70 | 0cac1b66 | Blue Swirl | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
71 | 0cac1b66 | Blue Swirl | } |
72 | 0cac1b66 | Blue Swirl | } |
73 | 0cac1b66 | Blue Swirl | |
74 | 0cac1b66 | Blue Swirl | memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
75 | 0cac1b66 | Blue Swirl | |
76 | 0cac1b66 | Blue Swirl | env->tlb_flush_addr = -1;
|
77 | 0cac1b66 | Blue Swirl | env->tlb_flush_mask = 0;
|
78 | 0cac1b66 | Blue Swirl | tlb_flush_count++; |
79 | 0cac1b66 | Blue Swirl | } |
80 | 0cac1b66 | Blue Swirl | |
81 | 0cac1b66 | Blue Swirl | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
82 | 0cac1b66 | Blue Swirl | { |
83 | 0cac1b66 | Blue Swirl | if (addr == (tlb_entry->addr_read &
|
84 | 0cac1b66 | Blue Swirl | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
85 | 0cac1b66 | Blue Swirl | addr == (tlb_entry->addr_write & |
86 | 0cac1b66 | Blue Swirl | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
87 | 0cac1b66 | Blue Swirl | addr == (tlb_entry->addr_code & |
88 | 0cac1b66 | Blue Swirl | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
89 | 0cac1b66 | Blue Swirl | *tlb_entry = s_cputlb_empty_entry; |
90 | 0cac1b66 | Blue Swirl | } |
91 | 0cac1b66 | Blue Swirl | } |
92 | 0cac1b66 | Blue Swirl | |
93 | 0cac1b66 | Blue Swirl | void tlb_flush_page(CPUArchState *env, target_ulong addr)
|
94 | 0cac1b66 | Blue Swirl | { |
95 | 0cac1b66 | Blue Swirl | int i;
|
96 | 0cac1b66 | Blue Swirl | int mmu_idx;
|
97 | 0cac1b66 | Blue Swirl | |
98 | 0cac1b66 | Blue Swirl | #if defined(DEBUG_TLB)
|
99 | 0cac1b66 | Blue Swirl | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
100 | 0cac1b66 | Blue Swirl | #endif
|
101 | 0cac1b66 | Blue Swirl | /* Check if we need to flush due to large pages. */
|
102 | 0cac1b66 | Blue Swirl | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
|
103 | 0cac1b66 | Blue Swirl | #if defined(DEBUG_TLB)
|
104 | 0cac1b66 | Blue Swirl | printf("tlb_flush_page: forced full flush ("
|
105 | 0cac1b66 | Blue Swirl | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", |
106 | 0cac1b66 | Blue Swirl | env->tlb_flush_addr, env->tlb_flush_mask); |
107 | 0cac1b66 | Blue Swirl | #endif
|
108 | 0cac1b66 | Blue Swirl | tlb_flush(env, 1);
|
109 | 0cac1b66 | Blue Swirl | return;
|
110 | 0cac1b66 | Blue Swirl | } |
111 | 0cac1b66 | Blue Swirl | /* must reset current TB so that interrupts cannot modify the
|
112 | 0cac1b66 | Blue Swirl | links while we are modifying them */
|
113 | 0cac1b66 | Blue Swirl | env->current_tb = NULL;
|
114 | 0cac1b66 | Blue Swirl | |
115 | 0cac1b66 | Blue Swirl | addr &= TARGET_PAGE_MASK; |
116 | 0cac1b66 | Blue Swirl | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
117 | 0cac1b66 | Blue Swirl | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
118 | 0cac1b66 | Blue Swirl | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); |
119 | 0cac1b66 | Blue Swirl | } |
120 | 0cac1b66 | Blue Swirl | |
121 | 0cac1b66 | Blue Swirl | tb_flush_jmp_cache(env, addr); |
122 | 0cac1b66 | Blue Swirl | } |
123 | 0cac1b66 | Blue Swirl | |
124 | 0cac1b66 | Blue Swirl | /* update the TLBs so that writes to code in the virtual page 'addr'
|
125 | 0cac1b66 | Blue Swirl | can be detected */
|
126 | 0cac1b66 | Blue Swirl | void tlb_protect_code(ram_addr_t ram_addr)
|
127 | 0cac1b66 | Blue Swirl | { |
128 | 0cac1b66 | Blue Swirl | cpu_physical_memory_reset_dirty(ram_addr, |
129 | 0cac1b66 | Blue Swirl | ram_addr + TARGET_PAGE_SIZE, |
130 | 0cac1b66 | Blue Swirl | CODE_DIRTY_FLAG); |
131 | 0cac1b66 | Blue Swirl | } |
132 | 0cac1b66 | Blue Swirl | |
133 | 0cac1b66 | Blue Swirl | /* update the TLB so that writes in physical page 'phys_addr' are no longer
|
134 | 0cac1b66 | Blue Swirl | tested for self modifying code */
|
135 | 0cac1b66 | Blue Swirl | void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
|
136 | 0cac1b66 | Blue Swirl | target_ulong vaddr) |
137 | 0cac1b66 | Blue Swirl | { |
138 | 0cac1b66 | Blue Swirl | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
139 | 0cac1b66 | Blue Swirl | } |
140 | 0cac1b66 | Blue Swirl | |
141 | 0cac1b66 | Blue Swirl | static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe) |
142 | 0cac1b66 | Blue Swirl | { |
143 | 0cac1b66 | Blue Swirl | return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0; |
144 | 0cac1b66 | Blue Swirl | } |
145 | 0cac1b66 | Blue Swirl | |
146 | 0cac1b66 | Blue Swirl | void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
|
147 | 0cac1b66 | Blue Swirl | uintptr_t length) |
148 | 0cac1b66 | Blue Swirl | { |
149 | 0cac1b66 | Blue Swirl | uintptr_t addr; |
150 | 0cac1b66 | Blue Swirl | |
151 | 0cac1b66 | Blue Swirl | if (tlb_is_dirty_ram(tlb_entry)) {
|
152 | 0cac1b66 | Blue Swirl | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; |
153 | 0cac1b66 | Blue Swirl | if ((addr - start) < length) {
|
154 | 0cac1b66 | Blue Swirl | tlb_entry->addr_write |= TLB_NOTDIRTY; |
155 | 0cac1b66 | Blue Swirl | } |
156 | 0cac1b66 | Blue Swirl | } |
157 | 0cac1b66 | Blue Swirl | } |
158 | 0cac1b66 | Blue Swirl | |
159 | 0cac1b66 | Blue Swirl | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
160 | 0cac1b66 | Blue Swirl | { |
161 | 0cac1b66 | Blue Swirl | ram_addr_t ram_addr; |
162 | 0cac1b66 | Blue Swirl | void *p;
|
163 | 0cac1b66 | Blue Swirl | |
164 | 0cac1b66 | Blue Swirl | if (tlb_is_dirty_ram(tlb_entry)) {
|
165 | 0cac1b66 | Blue Swirl | p = (void *)(uintptr_t)((tlb_entry->addr_write & TARGET_PAGE_MASK)
|
166 | 0cac1b66 | Blue Swirl | + tlb_entry->addend); |
167 | 0cac1b66 | Blue Swirl | ram_addr = qemu_ram_addr_from_host_nofail(p); |
168 | 0cac1b66 | Blue Swirl | if (!cpu_physical_memory_is_dirty(ram_addr)) {
|
169 | 0cac1b66 | Blue Swirl | tlb_entry->addr_write |= TLB_NOTDIRTY; |
170 | 0cac1b66 | Blue Swirl | } |
171 | 0cac1b66 | Blue Swirl | } |
172 | 0cac1b66 | Blue Swirl | } |
173 | 0cac1b66 | Blue Swirl | |
174 | 0cac1b66 | Blue Swirl | void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
|
175 | 0cac1b66 | Blue Swirl | { |
176 | 0cac1b66 | Blue Swirl | CPUArchState *env; |
177 | 0cac1b66 | Blue Swirl | |
178 | 0cac1b66 | Blue Swirl | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
179 | 0cac1b66 | Blue Swirl | int mmu_idx;
|
180 | 0cac1b66 | Blue Swirl | |
181 | 0cac1b66 | Blue Swirl | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
182 | 0cac1b66 | Blue Swirl | unsigned int i; |
183 | 0cac1b66 | Blue Swirl | |
184 | 0cac1b66 | Blue Swirl | for (i = 0; i < CPU_TLB_SIZE; i++) { |
185 | 0cac1b66 | Blue Swirl | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], |
186 | 0cac1b66 | Blue Swirl | start1, length); |
187 | 0cac1b66 | Blue Swirl | } |
188 | 0cac1b66 | Blue Swirl | } |
189 | 0cac1b66 | Blue Swirl | } |
190 | 0cac1b66 | Blue Swirl | } |
191 | 0cac1b66 | Blue Swirl | |
192 | 0cac1b66 | Blue Swirl | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
193 | 0cac1b66 | Blue Swirl | { |
194 | 0cac1b66 | Blue Swirl | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
|
195 | 0cac1b66 | Blue Swirl | tlb_entry->addr_write = vaddr; |
196 | 0cac1b66 | Blue Swirl | } |
197 | 0cac1b66 | Blue Swirl | } |
198 | 0cac1b66 | Blue Swirl | |
199 | 0cac1b66 | Blue Swirl | /* update the TLB corresponding to virtual page vaddr
|
200 | 0cac1b66 | Blue Swirl | so that it is no longer dirty */
|
201 | 0cac1b66 | Blue Swirl | void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
|
202 | 0cac1b66 | Blue Swirl | { |
203 | 0cac1b66 | Blue Swirl | int i;
|
204 | 0cac1b66 | Blue Swirl | int mmu_idx;
|
205 | 0cac1b66 | Blue Swirl | |
206 | 0cac1b66 | Blue Swirl | vaddr &= TARGET_PAGE_MASK; |
207 | 0cac1b66 | Blue Swirl | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
208 | 0cac1b66 | Blue Swirl | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
209 | 0cac1b66 | Blue Swirl | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); |
210 | 0cac1b66 | Blue Swirl | } |
211 | 0cac1b66 | Blue Swirl | } |
212 | 0cac1b66 | Blue Swirl | |
213 | 0cac1b66 | Blue Swirl | /* Our TLB does not support large pages, so remember the area covered by
|
214 | 0cac1b66 | Blue Swirl | large pages and trigger a full TLB flush if these are invalidated. */
|
215 | 0cac1b66 | Blue Swirl | static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, |
216 | 0cac1b66 | Blue Swirl | target_ulong size) |
217 | 0cac1b66 | Blue Swirl | { |
218 | 0cac1b66 | Blue Swirl | target_ulong mask = ~(size - 1);
|
219 | 0cac1b66 | Blue Swirl | |
220 | 0cac1b66 | Blue Swirl | if (env->tlb_flush_addr == (target_ulong)-1) { |
221 | 0cac1b66 | Blue Swirl | env->tlb_flush_addr = vaddr & mask; |
222 | 0cac1b66 | Blue Swirl | env->tlb_flush_mask = mask; |
223 | 0cac1b66 | Blue Swirl | return;
|
224 | 0cac1b66 | Blue Swirl | } |
225 | 0cac1b66 | Blue Swirl | /* Extend the existing region to include the new page.
|
226 | 0cac1b66 | Blue Swirl | This is a compromise between unnecessary flushes and the cost
|
227 | 0cac1b66 | Blue Swirl | of maintaining a full variable size TLB. */
|
228 | 0cac1b66 | Blue Swirl | mask &= env->tlb_flush_mask; |
229 | 0cac1b66 | Blue Swirl | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { |
230 | 0cac1b66 | Blue Swirl | mask <<= 1;
|
231 | 0cac1b66 | Blue Swirl | } |
232 | 0cac1b66 | Blue Swirl | env->tlb_flush_addr &= mask; |
233 | 0cac1b66 | Blue Swirl | env->tlb_flush_mask = mask; |
234 | 0cac1b66 | Blue Swirl | } |
235 | 0cac1b66 | Blue Swirl | |
236 | 0cac1b66 | Blue Swirl | /* Add a new TLB entry. At most one entry for a given virtual address
|
237 | 0cac1b66 | Blue Swirl | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
|
238 | 0cac1b66 | Blue Swirl | supplied size is only used by tlb_flush_page. */
|
239 | 0cac1b66 | Blue Swirl | void tlb_set_page(CPUArchState *env, target_ulong vaddr,
|
240 | a8170e5e | Avi Kivity | hwaddr paddr, int prot,
|
241 | 0cac1b66 | Blue Swirl | int mmu_idx, target_ulong size)
|
242 | 0cac1b66 | Blue Swirl | { |
243 | 0cac1b66 | Blue Swirl | MemoryRegionSection *section; |
244 | 0cac1b66 | Blue Swirl | unsigned int index; |
245 | 0cac1b66 | Blue Swirl | target_ulong address; |
246 | 0cac1b66 | Blue Swirl | target_ulong code_address; |
247 | 0cac1b66 | Blue Swirl | uintptr_t addend; |
248 | 0cac1b66 | Blue Swirl | CPUTLBEntry *te; |
249 | a8170e5e | Avi Kivity | hwaddr iotlb; |
250 | 0cac1b66 | Blue Swirl | |
251 | 0cac1b66 | Blue Swirl | assert(size >= TARGET_PAGE_SIZE); |
252 | 0cac1b66 | Blue Swirl | if (size != TARGET_PAGE_SIZE) {
|
253 | 0cac1b66 | Blue Swirl | tlb_add_large_page(env, vaddr, size); |
254 | 0cac1b66 | Blue Swirl | } |
255 | ac1970fb | Avi Kivity | section = phys_page_find(address_space_memory.dispatch, paddr >> TARGET_PAGE_BITS); |
256 | 0cac1b66 | Blue Swirl | #if defined(DEBUG_TLB)
|
257 | 0cac1b66 | Blue Swirl | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx |
258 | 0cac1b66 | Blue Swirl | " prot=%x idx=%d pd=0x%08lx\n",
|
259 | 0cac1b66 | Blue Swirl | vaddr, paddr, prot, mmu_idx, pd); |
260 | 0cac1b66 | Blue Swirl | #endif
|
261 | 0cac1b66 | Blue Swirl | |
262 | 0cac1b66 | Blue Swirl | address = vaddr; |
263 | cc5bea60 | Blue Swirl | if (!(memory_region_is_ram(section->mr) ||
|
264 | cc5bea60 | Blue Swirl | memory_region_is_romd(section->mr))) { |
265 | 0cac1b66 | Blue Swirl | /* IO memory case (romd handled later) */
|
266 | 0cac1b66 | Blue Swirl | address |= TLB_MMIO; |
267 | 0cac1b66 | Blue Swirl | } |
268 | cc5bea60 | Blue Swirl | if (memory_region_is_ram(section->mr) ||
|
269 | cc5bea60 | Blue Swirl | memory_region_is_romd(section->mr)) { |
270 | 0cac1b66 | Blue Swirl | addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) |
271 | cc5bea60 | Blue Swirl | + memory_region_section_addr(section, paddr); |
272 | 0cac1b66 | Blue Swirl | } else {
|
273 | 0cac1b66 | Blue Swirl | addend = 0;
|
274 | 0cac1b66 | Blue Swirl | } |
275 | 0cac1b66 | Blue Swirl | |
276 | 0cac1b66 | Blue Swirl | code_address = address; |
277 | 56eb21e1 | Max Filippov | iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, prot, |
278 | 56eb21e1 | Max Filippov | &address); |
279 | 0cac1b66 | Blue Swirl | |
280 | 0cac1b66 | Blue Swirl | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
281 | 0cac1b66 | Blue Swirl | env->iotlb[mmu_idx][index] = iotlb - vaddr; |
282 | 0cac1b66 | Blue Swirl | te = &env->tlb_table[mmu_idx][index]; |
283 | 0cac1b66 | Blue Swirl | te->addend = addend - vaddr; |
284 | 0cac1b66 | Blue Swirl | if (prot & PAGE_READ) {
|
285 | 0cac1b66 | Blue Swirl | te->addr_read = address; |
286 | 0cac1b66 | Blue Swirl | } else {
|
287 | 0cac1b66 | Blue Swirl | te->addr_read = -1;
|
288 | 0cac1b66 | Blue Swirl | } |
289 | 0cac1b66 | Blue Swirl | |
290 | 0cac1b66 | Blue Swirl | if (prot & PAGE_EXEC) {
|
291 | 0cac1b66 | Blue Swirl | te->addr_code = code_address; |
292 | 0cac1b66 | Blue Swirl | } else {
|
293 | 0cac1b66 | Blue Swirl | te->addr_code = -1;
|
294 | 0cac1b66 | Blue Swirl | } |
295 | 0cac1b66 | Blue Swirl | if (prot & PAGE_WRITE) {
|
296 | 0cac1b66 | Blue Swirl | if ((memory_region_is_ram(section->mr) && section->readonly)
|
297 | cc5bea60 | Blue Swirl | || memory_region_is_romd(section->mr)) { |
298 | 0cac1b66 | Blue Swirl | /* Write access calls the I/O callback. */
|
299 | 0cac1b66 | Blue Swirl | te->addr_write = address | TLB_MMIO; |
300 | 0cac1b66 | Blue Swirl | } else if (memory_region_is_ram(section->mr) |
301 | 0cac1b66 | Blue Swirl | && !cpu_physical_memory_is_dirty( |
302 | 0cac1b66 | Blue Swirl | section->mr->ram_addr |
303 | cc5bea60 | Blue Swirl | + memory_region_section_addr(section, paddr))) { |
304 | 0cac1b66 | Blue Swirl | te->addr_write = address | TLB_NOTDIRTY; |
305 | 0cac1b66 | Blue Swirl | } else {
|
306 | 0cac1b66 | Blue Swirl | te->addr_write = address; |
307 | 0cac1b66 | Blue Swirl | } |
308 | 0cac1b66 | Blue Swirl | } else {
|
309 | 0cac1b66 | Blue Swirl | te->addr_write = -1;
|
310 | 0cac1b66 | Blue Swirl | } |
311 | 0cac1b66 | Blue Swirl | } |
312 | 0cac1b66 | Blue Swirl | |
313 | 0cac1b66 | Blue Swirl | /* NOTE: this function can trigger an exception */
|
314 | 0cac1b66 | Blue Swirl | /* NOTE2: the returned address is not exactly the physical address: it
|
315 | 116aae36 | Peter Maydell | * is actually a ram_addr_t (in system mode; the user mode emulation
|
316 | 116aae36 | Peter Maydell | * version of this function returns a guest virtual address).
|
317 | 116aae36 | Peter Maydell | */
|
318 | 0cac1b66 | Blue Swirl | tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) |
319 | 0cac1b66 | Blue Swirl | { |
320 | 0cac1b66 | Blue Swirl | int mmu_idx, page_index, pd;
|
321 | 0cac1b66 | Blue Swirl | void *p;
|
322 | 0cac1b66 | Blue Swirl | MemoryRegion *mr; |
323 | 0cac1b66 | Blue Swirl | |
324 | 0cac1b66 | Blue Swirl | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
325 | 0cac1b66 | Blue Swirl | mmu_idx = cpu_mmu_index(env1); |
326 | 0cac1b66 | Blue Swirl | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
|
327 | 0cac1b66 | Blue Swirl | (addr & TARGET_PAGE_MASK))) { |
328 | 0cac1b66 | Blue Swirl | cpu_ldub_code(env1, addr); |
329 | 0cac1b66 | Blue Swirl | } |
330 | 0cac1b66 | Blue Swirl | pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK; |
331 | 0cac1b66 | Blue Swirl | mr = iotlb_to_region(pd); |
332 | 0cac1b66 | Blue Swirl | if (memory_region_is_unassigned(mr)) {
|
333 | 0cac1b66 | Blue Swirl | #if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
|
334 | 0cac1b66 | Blue Swirl | cpu_unassigned_access(env1, addr, 0, 1, 0, 4); |
335 | 0cac1b66 | Blue Swirl | #else
|
336 | 0cac1b66 | Blue Swirl | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
|
337 | 0cac1b66 | Blue Swirl | TARGET_FMT_lx "\n", addr);
|
338 | 0cac1b66 | Blue Swirl | #endif
|
339 | 0cac1b66 | Blue Swirl | } |
340 | 0cac1b66 | Blue Swirl | p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
|
341 | 0cac1b66 | Blue Swirl | return qemu_ram_addr_from_host_nofail(p);
|
342 | 0cac1b66 | Blue Swirl | } |
343 | 0cac1b66 | Blue Swirl | |
344 | 0cac1b66 | Blue Swirl | #define MMUSUFFIX _cmmu
|
345 | 0cac1b66 | Blue Swirl | #undef GETPC
|
346 | 0cac1b66 | Blue Swirl | #define GETPC() ((uintptr_t)0) |
347 | 0cac1b66 | Blue Swirl | #define SOFTMMU_CODE_ACCESS
|
348 | 0cac1b66 | Blue Swirl | |
349 | 0cac1b66 | Blue Swirl | #define SHIFT 0 |
350 | 0cac1b66 | Blue Swirl | #include "softmmu_template.h" |
351 | 0cac1b66 | Blue Swirl | |
352 | 0cac1b66 | Blue Swirl | #define SHIFT 1 |
353 | 0cac1b66 | Blue Swirl | #include "softmmu_template.h" |
354 | 0cac1b66 | Blue Swirl | |
355 | 0cac1b66 | Blue Swirl | #define SHIFT 2 |
356 | 0cac1b66 | Blue Swirl | #include "softmmu_template.h" |
357 | 0cac1b66 | Blue Swirl | |
358 | 0cac1b66 | Blue Swirl | #define SHIFT 3 |
359 | 0cac1b66 | Blue Swirl | #include "softmmu_template.h" |
360 | 0cac1b66 | Blue Swirl | |
361 | 0cac1b66 | Blue Swirl | #undef env |