Revision 5f9fc5ad hw/ppc405_boards.c

b/hw/ppc405_boards.c
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#endif
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        pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
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                              dinfo->bdrv, 65536, fl_sectors, 1,
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                              2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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                              2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
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                              1);
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        fl_idx++;
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    } else
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#endif
......
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#endif
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        pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
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                              dinfo->bdrv, 65536, fl_sectors, 1,
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                              4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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                              4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
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                              1);
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        fl_idx++;
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    } else
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#endif
......
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        bios_offset = qemu_ram_alloc(bios_size);
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        pflash_cfi02_register(0xfc000000, bios_offset,
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                              dinfo->bdrv, 65536, fl_sectors, 1,
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                              4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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                              4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
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                              1);
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        fl_idx++;
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    }
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    /* Register CLPD & LCD display */

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