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/*
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 * TI TWL92230C energy-management companion device for the OMAP24xx.
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 * Aka. Menelaus (N4200 MENELAUS1_V2.2)
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 *
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 * Copyright (C) 2008 Nokia Corporation
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 * Written by Andrzej Zaborowski <andrew@openedhand.com>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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 * MA 02111-1307 USA
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 */
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#include "hw.h"
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#include "qemu-timer.h"
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#include "i2c.h"
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#include "sysemu.h"
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#include "console.h"
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#define VERBOSE 1
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struct menelaus_s {
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    i2c_slave i2c;
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    qemu_irq irq;
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    int firstbyte;
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    uint8_t reg;
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    uint8_t vcore[5];
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    uint8_t dcdc[3];
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    uint8_t ldo[8];
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    uint8_t sleep[2];
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    uint8_t osc;
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    uint8_t detect;
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    uint16_t mask;
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    uint16_t status;
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    uint8_t dir;
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    uint8_t inputs;
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    uint8_t outputs;
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    uint8_t bbsms;
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    uint8_t pull[4];
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    uint8_t mmc_ctrl[3];
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    uint8_t mmc_debounce;
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    struct {
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        uint8_t ctrl;
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        uint16_t comp;
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        QEMUTimer *hz;
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        int64_t next;
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        struct tm tm;
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        struct tm new;
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        struct tm alm;
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        int sec_offset;
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        int alm_sec;
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        int next_comp;
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    } rtc;
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    qemu_irq handler[3];
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    qemu_irq *in;
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    int pwrbtn_state;
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    qemu_irq pwrbtn;
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};
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static inline void menelaus_update(struct menelaus_s *s)
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{
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    qemu_set_irq(s->irq, s->status & ~s->mask);
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}
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static inline void menelaus_rtc_start(struct menelaus_s *s)
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{
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    s->rtc.next =+ qemu_get_clock(rt_clock);
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    qemu_mod_timer(s->rtc.hz, s->rtc.next);
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}
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static inline void menelaus_rtc_stop(struct menelaus_s *s)
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{
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    qemu_del_timer(s->rtc.hz);
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    s->rtc.next =- qemu_get_clock(rt_clock);
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    if (s->rtc.next < 1)
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        s->rtc.next = 1;
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}
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static void menelaus_rtc_update(struct menelaus_s *s)
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{
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    qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset);
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}
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static void menelaus_alm_update(struct menelaus_s *s)
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{
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    if ((s->rtc.ctrl & 3) == 3)
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        s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset;
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}
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static void menelaus_rtc_hz(void *opaque)
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{
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    struct menelaus_s *s = (struct menelaus_s *) opaque;
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    s->rtc.next_comp --;
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    s->rtc.alm_sec --;
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    s->rtc.next += 1000;
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    qemu_mod_timer(s->rtc.hz, s->rtc.next);
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    if ((s->rtc.ctrl >> 3) & 3) {                                /* EVERY */
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        menelaus_rtc_update(s);
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        if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
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            s->status |= 1 << 8;                                /* RTCTMR */
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        else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min)
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            s->status |= 1 << 8;                                /* RTCTMR */
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        else if (!s->rtc.tm.tm_hour)
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            s->status |= 1 << 8;                                /* RTCTMR */
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    } else
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        s->status |= 1 << 8;                                        /* RTCTMR */
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    if ((s->rtc.ctrl >> 1) & 1) {                                /* RTC_AL_EN */
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        if (s->rtc.alm_sec == 0)
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            s->status |= 1 << 9;                                /* RTCALM */
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        /* TODO: wake-up */
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    }
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    if (s->rtc.next_comp <= 0) {
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        s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000);
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        s->rtc.next_comp = 3600;
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    }
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    menelaus_update(s);
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}
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void menelaus_reset(i2c_slave *i2c)
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{
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    struct menelaus_s *s = (struct menelaus_s *) i2c;
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    s->reg = 0x00;
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    s->vcore[0] = 0x0c;        /* XXX: X-loader needs 0x8c? check!  */
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    s->vcore[1] = 0x05;
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    s->vcore[2] = 0x02;
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    s->vcore[3] = 0x0c;
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    s->vcore[4] = 0x03;
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    s->dcdc[0] = 0x33;        /* Depends on wiring */
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    s->dcdc[1] = 0x03;
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    s->dcdc[2] = 0x00;
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    s->ldo[0] = 0x95;
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    s->ldo[1] = 0x7e;
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    s->ldo[2] = 0x00;
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    s->ldo[3] = 0x00;        /* Depends on wiring */
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    s->ldo[4] = 0x03;        /* Depends on wiring */
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    s->ldo[5] = 0x00;
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    s->ldo[6] = 0x00;
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    s->ldo[7] = 0x00;
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    s->sleep[0] = 0x00;
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    s->sleep[1] = 0x00;
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    s->osc = 0x01;
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    s->detect = 0x09;
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    s->mask = 0x0fff;
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    s->status = 0;
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    s->dir = 0x07;
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    s->outputs = 0x00;
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    s->bbsms = 0x00;
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    s->pull[0] = 0x00;
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    s->pull[1] = 0x00;
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    s->pull[2] = 0x00;
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    s->pull[3] = 0x00;
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    s->mmc_ctrl[0] = 0x03;
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    s->mmc_ctrl[1] = 0xc0;
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    s->mmc_ctrl[2] = 0x00;
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    s->mmc_debounce = 0x05;
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    if (s->rtc.ctrl & 1)
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        menelaus_rtc_stop(s);
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    s->rtc.ctrl = 0x00;
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    s->rtc.comp = 0x0000;
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    s->rtc.next = 1000;
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    s->rtc.sec_offset = 0;
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    s->rtc.next_comp = 1800;
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    s->rtc.alm_sec = 1800;
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    s->rtc.alm.tm_sec = 0x00;
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    s->rtc.alm.tm_min = 0x00;
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    s->rtc.alm.tm_hour = 0x00;
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    s->rtc.alm.tm_mday = 0x01;
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    s->rtc.alm.tm_mon = 0x00;
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    s->rtc.alm.tm_year = 2004;
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    menelaus_update(s);
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}
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static inline uint8_t to_bcd(int val)
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{
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    return ((val / 10) << 4) | (val % 10);
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}
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static inline int from_bcd(uint8_t val)
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{
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    return ((val >> 4) * 10) + (val & 0x0f);
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}
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static void menelaus_gpio_set(void *opaque, int line, int level)
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{
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    struct menelaus_s *s = (struct menelaus_s *) opaque;
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    /* No interrupt generated */
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    s->inputs &= ~(1 << line);
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    s->inputs |= level << line;
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}
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static void menelaus_pwrbtn_set(void *opaque, int line, int level)
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{
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    struct menelaus_s *s = (struct menelaus_s *) opaque;
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    if (!s->pwrbtn_state && level) {
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        s->status |= 1 << 11;                                        /* PSHBTN */
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        menelaus_update(s);
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    }
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    s->pwrbtn_state = level;
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}
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#define MENELAUS_REV                0x01
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#define MENELAUS_VCORE_CTRL1        0x02
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#define MENELAUS_VCORE_CTRL2        0x03
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#define MENELAUS_VCORE_CTRL3        0x04
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#define MENELAUS_VCORE_CTRL4        0x05
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#define MENELAUS_VCORE_CTRL5        0x06
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#define MENELAUS_DCDC_CTRL1        0x07
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#define MENELAUS_DCDC_CTRL2        0x08
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#define MENELAUS_DCDC_CTRL3        0x09
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#define MENELAUS_LDO_CTRL1        0x0a
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#define MENELAUS_LDO_CTRL2        0x0b
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#define MENELAUS_LDO_CTRL3        0x0c
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#define MENELAUS_LDO_CTRL4        0x0d
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#define MENELAUS_LDO_CTRL5        0x0e
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#define MENELAUS_LDO_CTRL6        0x0f
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#define MENELAUS_LDO_CTRL7        0x10
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#define MENELAUS_LDO_CTRL8        0x11
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#define MENELAUS_SLEEP_CTRL1        0x12
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#define MENELAUS_SLEEP_CTRL2        0x13
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#define MENELAUS_DEVICE_OFF        0x14
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#define MENELAUS_OSC_CTRL        0x15
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#define MENELAUS_DETECT_CTRL        0x16
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#define MENELAUS_INT_MASK1        0x17
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#define MENELAUS_INT_MASK2        0x18
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#define MENELAUS_INT_STATUS1        0x19
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#define MENELAUS_INT_STATUS2        0x1a
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#define MENELAUS_INT_ACK1        0x1b
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#define MENELAUS_INT_ACK2        0x1c
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#define MENELAUS_GPIO_CTRL        0x1d
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#define MENELAUS_GPIO_IN        0x1e
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#define MENELAUS_GPIO_OUT        0x1f
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#define MENELAUS_BBSMS                0x20
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#define MENELAUS_RTC_CTRL        0x21
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#define MENELAUS_RTC_UPDATE        0x22
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#define MENELAUS_RTC_SEC        0x23
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#define MENELAUS_RTC_MIN        0x24
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#define MENELAUS_RTC_HR                0x25
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#define MENELAUS_RTC_DAY        0x26
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#define MENELAUS_RTC_MON        0x27
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#define MENELAUS_RTC_YR                0x28
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#define MENELAUS_RTC_WKDAY        0x29
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#define MENELAUS_RTC_AL_SEC        0x2a
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#define MENELAUS_RTC_AL_MIN        0x2b
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#define MENELAUS_RTC_AL_HR        0x2c
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#define MENELAUS_RTC_AL_DAY        0x2d
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#define MENELAUS_RTC_AL_MON        0x2e
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#define MENELAUS_RTC_AL_YR        0x2f
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#define MENELAUS_RTC_COMP_MSB        0x30
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#define MENELAUS_RTC_COMP_LSB        0x31
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#define MENELAUS_S1_PULL_EN        0x32
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#define MENELAUS_S1_PULL_DIR        0x33
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#define MENELAUS_S2_PULL_EN        0x34
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#define MENELAUS_S2_PULL_DIR        0x35
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#define MENELAUS_MCT_CTRL1        0x36
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#define MENELAUS_MCT_CTRL2        0x37
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#define MENELAUS_MCT_CTRL3        0x38
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#define MENELAUS_MCT_PIN_ST        0x39
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#define MENELAUS_DEBOUNCE1        0x3a
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static uint8_t menelaus_read(void *opaque, uint8_t addr)
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{
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    struct menelaus_s *s = (struct menelaus_s *) opaque;
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    int reg = 0;
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    switch (addr) {
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    case MENELAUS_REV:
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        return 0x22;
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    case MENELAUS_VCORE_CTRL5: reg ++;
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    case MENELAUS_VCORE_CTRL4: reg ++;
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    case MENELAUS_VCORE_CTRL3: reg ++;
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    case MENELAUS_VCORE_CTRL2: reg ++;
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    case MENELAUS_VCORE_CTRL1:
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        return s->vcore[reg];
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    case MENELAUS_DCDC_CTRL3: reg ++;
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    case MENELAUS_DCDC_CTRL2: reg ++;
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    case MENELAUS_DCDC_CTRL1:
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        return s->dcdc[reg];
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    case MENELAUS_LDO_CTRL8: reg ++;
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    case MENELAUS_LDO_CTRL7: reg ++;
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    case MENELAUS_LDO_CTRL6: reg ++;
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    case MENELAUS_LDO_CTRL5: reg ++;
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    case MENELAUS_LDO_CTRL4: reg ++;
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    case MENELAUS_LDO_CTRL3: reg ++;
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    case MENELAUS_LDO_CTRL2: reg ++;
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    case MENELAUS_LDO_CTRL1:
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        return s->ldo[reg];
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    case MENELAUS_SLEEP_CTRL2: reg ++;
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    case MENELAUS_SLEEP_CTRL1:
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        return s->sleep[reg];
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    case MENELAUS_DEVICE_OFF:
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        return 0;
314 7e7c5e4c balrog
315 7e7c5e4c balrog
    case MENELAUS_OSC_CTRL:
316 7e7c5e4c balrog
        return s->osc | (1 << 7);                        /* CLK32K_GOOD */
317 7e7c5e4c balrog
318 7e7c5e4c balrog
    case MENELAUS_DETECT_CTRL:
319 7e7c5e4c balrog
        return s->detect;
320 7e7c5e4c balrog
321 7e7c5e4c balrog
    case MENELAUS_INT_MASK1:
322 7e7c5e4c balrog
        return (s->mask >> 0) & 0xff;
323 7e7c5e4c balrog
    case MENELAUS_INT_MASK2:
324 7e7c5e4c balrog
        return (s->mask >> 8) & 0xff;
325 7e7c5e4c balrog
326 7e7c5e4c balrog
    case MENELAUS_INT_STATUS1:
327 7e7c5e4c balrog
        return (s->status >> 0) & 0xff;
328 7e7c5e4c balrog
    case MENELAUS_INT_STATUS2:
329 7e7c5e4c balrog
        return (s->status >> 8) & 0xff;
330 7e7c5e4c balrog
331 7e7c5e4c balrog
    case MENELAUS_INT_ACK1:
332 7e7c5e4c balrog
    case MENELAUS_INT_ACK2:
333 7e7c5e4c balrog
        return 0;
334 7e7c5e4c balrog
335 7e7c5e4c balrog
    case MENELAUS_GPIO_CTRL:
336 7e7c5e4c balrog
        return s->dir;
337 7e7c5e4c balrog
    case MENELAUS_GPIO_IN:
338 7e7c5e4c balrog
        return s->inputs | (~s->dir & s->outputs);
339 7e7c5e4c balrog
    case MENELAUS_GPIO_OUT:
340 7e7c5e4c balrog
        return s->outputs;
341 7e7c5e4c balrog
342 7e7c5e4c balrog
    case MENELAUS_BBSMS:
343 7e7c5e4c balrog
        return s->bbsms;
344 7e7c5e4c balrog
345 7e7c5e4c balrog
    case MENELAUS_RTC_CTRL:
346 7e7c5e4c balrog
        return s->rtc.ctrl;
347 7e7c5e4c balrog
    case MENELAUS_RTC_UPDATE:
348 7e7c5e4c balrog
        return 0x00;
349 7e7c5e4c balrog
    case MENELAUS_RTC_SEC:
350 7e7c5e4c balrog
        menelaus_rtc_update(s);
351 7e7c5e4c balrog
        return to_bcd(s->rtc.tm.tm_sec);
352 7e7c5e4c balrog
    case MENELAUS_RTC_MIN:
353 7e7c5e4c balrog
        menelaus_rtc_update(s);
354 7e7c5e4c balrog
        return to_bcd(s->rtc.tm.tm_min);
355 7e7c5e4c balrog
    case MENELAUS_RTC_HR:
356 7e7c5e4c balrog
        menelaus_rtc_update(s);
357 7e7c5e4c balrog
        if ((s->rtc.ctrl >> 2) & 1)                        /* MODE12_n24 */
358 7e7c5e4c balrog
            return to_bcd((s->rtc.tm.tm_hour % 12) + 1) |
359 7e7c5e4c balrog
                    (!!(s->rtc.tm.tm_hour >= 12) << 7);        /* PM_nAM */
360 7e7c5e4c balrog
        else
361 7e7c5e4c balrog
            return to_bcd(s->rtc.tm.tm_hour);
362 7e7c5e4c balrog
    case MENELAUS_RTC_DAY:
363 7e7c5e4c balrog
        menelaus_rtc_update(s);
364 7e7c5e4c balrog
        return to_bcd(s->rtc.tm.tm_mday);
365 7e7c5e4c balrog
    case MENELAUS_RTC_MON:
366 7e7c5e4c balrog
        menelaus_rtc_update(s);
367 7e7c5e4c balrog
        return to_bcd(s->rtc.tm.tm_mon + 1);
368 7e7c5e4c balrog
    case MENELAUS_RTC_YR:
369 7e7c5e4c balrog
        menelaus_rtc_update(s);
370 7e7c5e4c balrog
        return to_bcd(s->rtc.tm.tm_year - 2000);
371 7e7c5e4c balrog
    case MENELAUS_RTC_WKDAY:
372 7e7c5e4c balrog
        menelaus_rtc_update(s);
373 7e7c5e4c balrog
        return to_bcd(s->rtc.tm.tm_wday);
374 7e7c5e4c balrog
    case MENELAUS_RTC_AL_SEC:
375 7e7c5e4c balrog
        return to_bcd(s->rtc.alm.tm_sec);
376 7e7c5e4c balrog
    case MENELAUS_RTC_AL_MIN:
377 7e7c5e4c balrog
        return to_bcd(s->rtc.alm.tm_min);
378 7e7c5e4c balrog
    case MENELAUS_RTC_AL_HR:
379 7e7c5e4c balrog
        if ((s->rtc.ctrl >> 2) & 1)                        /* MODE12_n24 */
380 7e7c5e4c balrog
            return to_bcd((s->rtc.alm.tm_hour % 12) + 1) |
381 7e7c5e4c balrog
                    (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */
382 7e7c5e4c balrog
        else
383 7e7c5e4c balrog
            return to_bcd(s->rtc.alm.tm_hour);
384 7e7c5e4c balrog
    case MENELAUS_RTC_AL_DAY:
385 7e7c5e4c balrog
        return to_bcd(s->rtc.alm.tm_mday);
386 7e7c5e4c balrog
    case MENELAUS_RTC_AL_MON:
387 7e7c5e4c balrog
        return to_bcd(s->rtc.alm.tm_mon + 1);
388 7e7c5e4c balrog
    case MENELAUS_RTC_AL_YR:
389 7e7c5e4c balrog
        return to_bcd(s->rtc.alm.tm_year - 2000);
390 7e7c5e4c balrog
    case MENELAUS_RTC_COMP_MSB:
391 7e7c5e4c balrog
        return (s->rtc.comp >> 8) & 0xff;
392 7e7c5e4c balrog
    case MENELAUS_RTC_COMP_LSB:
393 7e7c5e4c balrog
        return (s->rtc.comp >> 0) & 0xff;
394 7e7c5e4c balrog
395 7e7c5e4c balrog
    case MENELAUS_S1_PULL_EN:
396 7e7c5e4c balrog
        return s->pull[0];
397 7e7c5e4c balrog
    case MENELAUS_S1_PULL_DIR:
398 7e7c5e4c balrog
        return s->pull[1];
399 7e7c5e4c balrog
    case MENELAUS_S2_PULL_EN:
400 7e7c5e4c balrog
        return s->pull[2];
401 7e7c5e4c balrog
    case MENELAUS_S2_PULL_DIR:
402 7e7c5e4c balrog
        return s->pull[3];
403 7e7c5e4c balrog
404 7e7c5e4c balrog
    case MENELAUS_MCT_CTRL3: reg ++;
405 7e7c5e4c balrog
    case MENELAUS_MCT_CTRL2: reg ++;
406 7e7c5e4c balrog
    case MENELAUS_MCT_CTRL1:
407 7e7c5e4c balrog
        return s->mmc_ctrl[reg];
408 7e7c5e4c balrog
    case MENELAUS_MCT_PIN_ST:
409 7e7c5e4c balrog
        /* TODO: return the real Card Detect */
410 7e7c5e4c balrog
        return 0;
411 7e7c5e4c balrog
    case MENELAUS_DEBOUNCE1:
412 7e7c5e4c balrog
        return s->mmc_debounce;
413 7e7c5e4c balrog
414 7e7c5e4c balrog
    default:
415 7e7c5e4c balrog
#ifdef VERBOSE
416 7e7c5e4c balrog
        printf("%s: unknown register %02x\n", __FUNCTION__, addr);
417 7e7c5e4c balrog
#endif
418 7e7c5e4c balrog
        break;
419 7e7c5e4c balrog
    }
420 7e7c5e4c balrog
    return 0;
421 7e7c5e4c balrog
}
422 7e7c5e4c balrog
423 7e7c5e4c balrog
static void menelaus_write(void *opaque, uint8_t addr, uint8_t value)
424 7e7c5e4c balrog
{
425 7e7c5e4c balrog
    struct menelaus_s *s = (struct menelaus_s *) opaque;
426 7e7c5e4c balrog
    int line;
427 7e7c5e4c balrog
    int reg = 0;
428 7e7c5e4c balrog
    struct tm tm;
429 7e7c5e4c balrog
430 7e7c5e4c balrog
    switch (addr) {
431 7e7c5e4c balrog
    case MENELAUS_VCORE_CTRL1:
432 7e7c5e4c balrog
        s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12);
433 7e7c5e4c balrog
        break;
434 7e7c5e4c balrog
    case MENELAUS_VCORE_CTRL2:
435 7e7c5e4c balrog
        s->vcore[1] = value;
436 7e7c5e4c balrog
        break;
437 7e7c5e4c balrog
    case MENELAUS_VCORE_CTRL3:
438 7e7c5e4c balrog
        s->vcore[2] = MIN(value & 0x1f, 0x12);
439 7e7c5e4c balrog
        break;
440 7e7c5e4c balrog
    case MENELAUS_VCORE_CTRL4:
441 7e7c5e4c balrog
        s->vcore[3] = MIN(value & 0x1f, 0x12);
442 7e7c5e4c balrog
        break;
443 7e7c5e4c balrog
    case MENELAUS_VCORE_CTRL5:
444 7e7c5e4c balrog
        s->vcore[4] = value & 3;
445 7e7c5e4c balrog
        /* XXX
446 7e7c5e4c balrog
         * auto set to 3 on M_Active, nRESWARM
447 7e7c5e4c balrog
         * auto set to 0 on M_WaitOn, M_Backup
448 7e7c5e4c balrog
         */
449 7e7c5e4c balrog
        break;
450 7e7c5e4c balrog
451 7e7c5e4c balrog
    case MENELAUS_DCDC_CTRL1:
452 7e7c5e4c balrog
        s->dcdc[0] = value & 0x3f;
453 7e7c5e4c balrog
        break;
454 7e7c5e4c balrog
    case MENELAUS_DCDC_CTRL2:
455 7e7c5e4c balrog
        s->dcdc[1] = value & 0x07;
456 7e7c5e4c balrog
        /* XXX
457 7e7c5e4c balrog
         * auto set to 3 on M_Active, nRESWARM
458 7e7c5e4c balrog
         * auto set to 0 on M_WaitOn, M_Backup
459 7e7c5e4c balrog
         */
460 7e7c5e4c balrog
        break;
461 7e7c5e4c balrog
    case MENELAUS_DCDC_CTRL3:
462 7e7c5e4c balrog
        s->dcdc[2] = value & 0x07;
463 7e7c5e4c balrog
        break;
464 7e7c5e4c balrog
465 7e7c5e4c balrog
    case MENELAUS_LDO_CTRL1:
466 7e7c5e4c balrog
        s->ldo[0] = value;
467 7e7c5e4c balrog
        break;
468 7e7c5e4c balrog
    case MENELAUS_LDO_CTRL2:
469 7e7c5e4c balrog
        s->ldo[1] = value & 0x7f;
470 7e7c5e4c balrog
        /* XXX
471 7e7c5e4c balrog
         * auto set to 0x7e on M_WaitOn, M_Backup
472 7e7c5e4c balrog
         */
473 7e7c5e4c balrog
        break;
474 7e7c5e4c balrog
    case MENELAUS_LDO_CTRL3:
475 7e7c5e4c balrog
        s->ldo[2] = value & 3;
476 7e7c5e4c balrog
        /* XXX
477 7e7c5e4c balrog
         * auto set to 3 on M_Active, nRESWARM
478 7e7c5e4c balrog
         * auto set to 0 on M_WaitOn, M_Backup
479 7e7c5e4c balrog
         */
480 7e7c5e4c balrog
        break;
481 7e7c5e4c balrog
    case MENELAUS_LDO_CTRL4:
482 7e7c5e4c balrog
        s->ldo[3] = value & 3;
483 7e7c5e4c balrog
        /* XXX
484 7e7c5e4c balrog
         * auto set to 3 on M_Active, nRESWARM
485 7e7c5e4c balrog
         * auto set to 0 on M_WaitOn, M_Backup
486 7e7c5e4c balrog
         */
487 7e7c5e4c balrog
        break;
488 7e7c5e4c balrog
    case MENELAUS_LDO_CTRL5:
489 7e7c5e4c balrog
        s->ldo[4] = value & 3;
490 7e7c5e4c balrog
        /* XXX
491 7e7c5e4c balrog
         * auto set to 3 on M_Active, nRESWARM
492 7e7c5e4c balrog
         * auto set to 0 on M_WaitOn, M_Backup
493 7e7c5e4c balrog
         */
494 7e7c5e4c balrog
        break;
495 7e7c5e4c balrog
    case MENELAUS_LDO_CTRL6:
496 7e7c5e4c balrog
        s->ldo[5] = value & 3;
497 7e7c5e4c balrog
        break;
498 7e7c5e4c balrog
    case MENELAUS_LDO_CTRL7:
499 7e7c5e4c balrog
        s->ldo[6] = value & 3;
500 7e7c5e4c balrog
        break;
501 7e7c5e4c balrog
    case MENELAUS_LDO_CTRL8:
502 7e7c5e4c balrog
        s->ldo[7] = value & 3;
503 7e7c5e4c balrog
        break;
504 7e7c5e4c balrog
505 7e7c5e4c balrog
    case MENELAUS_SLEEP_CTRL2: reg ++;
506 7e7c5e4c balrog
    case MENELAUS_SLEEP_CTRL1:
507 7e7c5e4c balrog
        s->sleep[reg] = value;
508 7e7c5e4c balrog
        break;
509 7e7c5e4c balrog
510 7e7c5e4c balrog
    case MENELAUS_DEVICE_OFF:
511 7e7c5e4c balrog
        if (value & 1)
512 7e7c5e4c balrog
            menelaus_reset(&s->i2c);
513 7e7c5e4c balrog
        break;
514 7e7c5e4c balrog
515 7e7c5e4c balrog
    case MENELAUS_OSC_CTRL:
516 7e7c5e4c balrog
        s->osc = value & 7;
517 7e7c5e4c balrog
        break;
518 7e7c5e4c balrog
519 7e7c5e4c balrog
    case MENELAUS_DETECT_CTRL:
520 7e7c5e4c balrog
        s->detect = value & 0x7f;
521 7e7c5e4c balrog
        break;
522 7e7c5e4c balrog
523 7e7c5e4c balrog
    case MENELAUS_INT_MASK1:
524 7e7c5e4c balrog
        s->mask &= 0xf00;
525 7e7c5e4c balrog
        s->mask |= value << 0;
526 7e7c5e4c balrog
        menelaus_update(s);
527 7e7c5e4c balrog
        break;
528 7e7c5e4c balrog
    case MENELAUS_INT_MASK2:
529 7e7c5e4c balrog
        s->mask &= 0x0ff;
530 7e7c5e4c balrog
        s->mask |= value << 8;
531 7e7c5e4c balrog
        menelaus_update(s);
532 7e7c5e4c balrog
        break;
533 7e7c5e4c balrog
534 7e7c5e4c balrog
    case MENELAUS_INT_ACK1:
535 7e7c5e4c balrog
        s->status &= ~(((uint16_t) value) << 0);
536 7e7c5e4c balrog
        menelaus_update(s);
537 7e7c5e4c balrog
        break;
538 7e7c5e4c balrog
    case MENELAUS_INT_ACK2:
539 7e7c5e4c balrog
        s->status &= ~(((uint16_t) value) << 8);
540 7e7c5e4c balrog
        menelaus_update(s);
541 7e7c5e4c balrog
        break;
542 7e7c5e4c balrog
543 7e7c5e4c balrog
    case MENELAUS_GPIO_CTRL:
544 7e7c5e4c balrog
        for (line = 0; line < 3; line ++)
545 7e7c5e4c balrog
            if (((s->dir ^ value) >> line) & 1)
546 7e7c5e4c balrog
                if (s->handler[line])
547 7e7c5e4c balrog
                    qemu_set_irq(s->handler[line],
548 7e7c5e4c balrog
                                    ((s->outputs & ~s->dir) >> line) & 1);
549 7e7c5e4c balrog
        s->dir = value & 0x67;
550 7e7c5e4c balrog
        break;
551 7e7c5e4c balrog
    case MENELAUS_GPIO_OUT:
552 7e7c5e4c balrog
        for (line = 0; line < 3; line ++)
553 7e7c5e4c balrog
            if ((((s->outputs ^ value) & ~s->dir) >> line) & 1)
554 7e7c5e4c balrog
                if (s->handler[line])
555 7e7c5e4c balrog
                    qemu_set_irq(s->handler[line], (s->outputs >> line) & 1);
556 7e7c5e4c balrog
        s->outputs = value & 0x07;
557 7e7c5e4c balrog
        break;
558 7e7c5e4c balrog
559 7e7c5e4c balrog
    case MENELAUS_BBSMS:
560 7e7c5e4c balrog
        s->bbsms = 0x0d;
561 7e7c5e4c balrog
        break;
562 7e7c5e4c balrog
563 7e7c5e4c balrog
    case MENELAUS_RTC_CTRL:
564 7e7c5e4c balrog
        if ((s->rtc.ctrl ^ value) & 1) {                        /* RTC_EN */
565 7e7c5e4c balrog
            if (value & 1)
566 7e7c5e4c balrog
                menelaus_rtc_start(s);
567 7e7c5e4c balrog
            else
568 7e7c5e4c balrog
                menelaus_rtc_stop(s);
569 7e7c5e4c balrog
        }
570 7e7c5e4c balrog
        s->rtc.ctrl = value & 0x1f;
571 7e7c5e4c balrog
        menelaus_alm_update(s);
572 7e7c5e4c balrog
        break;
573 7e7c5e4c balrog
    case MENELAUS_RTC_UPDATE:
574 7e7c5e4c balrog
        menelaus_rtc_update(s);
575 7e7c5e4c balrog
        memcpy(&tm, &s->rtc.tm, sizeof(tm));
576 7e7c5e4c balrog
        switch (value & 0xf) {
577 7e7c5e4c balrog
        case 0:
578 7e7c5e4c balrog
            break;
579 7e7c5e4c balrog
        case 1:
580 7e7c5e4c balrog
            tm.tm_sec = s->rtc.new.tm_sec;
581 7e7c5e4c balrog
            break;
582 7e7c5e4c balrog
        case 2:
583 7e7c5e4c balrog
            tm.tm_min = s->rtc.new.tm_min;
584 7e7c5e4c balrog
            break;
585 7e7c5e4c balrog
        case 3:
586 7e7c5e4c balrog
            if (s->rtc.new.tm_hour > 23)
587 7e7c5e4c balrog
                goto rtc_badness;
588 7e7c5e4c balrog
            tm.tm_hour = s->rtc.new.tm_hour;
589 7e7c5e4c balrog
            break;
590 7e7c5e4c balrog
        case 4:
591 7e7c5e4c balrog
            if (s->rtc.new.tm_mday < 1)
592 7e7c5e4c balrog
                goto rtc_badness;
593 7e7c5e4c balrog
            /* TODO check range */
594 7e7c5e4c balrog
            tm.tm_mday = s->rtc.new.tm_mday;
595 7e7c5e4c balrog
            break;
596 7e7c5e4c balrog
        case 5:
597 7e7c5e4c balrog
            if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
598 7e7c5e4c balrog
                goto rtc_badness;
599 7e7c5e4c balrog
            tm.tm_mon = s->rtc.new.tm_mon;
600 7e7c5e4c balrog
            break;
601 7e7c5e4c balrog
        case 6:
602 7e7c5e4c balrog
            tm.tm_year = s->rtc.new.tm_year;
603 7e7c5e4c balrog
            break;
604 7e7c5e4c balrog
        case 7:
605 7e7c5e4c balrog
            /* TODO set .tm_mday instead */
606 7e7c5e4c balrog
            tm.tm_wday = s->rtc.new.tm_wday;
607 7e7c5e4c balrog
            break;
608 7e7c5e4c balrog
        case 8:
609 7e7c5e4c balrog
            if (s->rtc.new.tm_hour > 23)
610 7e7c5e4c balrog
                goto rtc_badness;
611 7e7c5e4c balrog
            if (s->rtc.new.tm_mday < 1)
612 7e7c5e4c balrog
                goto rtc_badness;
613 7e7c5e4c balrog
            if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
614 7e7c5e4c balrog
                goto rtc_badness;
615 7e7c5e4c balrog
            tm.tm_sec = s->rtc.new.tm_sec;
616 7e7c5e4c balrog
            tm.tm_min = s->rtc.new.tm_min;
617 7e7c5e4c balrog
            tm.tm_hour = s->rtc.new.tm_hour;
618 7e7c5e4c balrog
            tm.tm_mday = s->rtc.new.tm_mday;
619 7e7c5e4c balrog
            tm.tm_mon = s->rtc.new.tm_mon;
620 7e7c5e4c balrog
            tm.tm_year = s->rtc.new.tm_year;
621 7e7c5e4c balrog
            break;
622 7e7c5e4c balrog
        rtc_badness:
623 7e7c5e4c balrog
        default:
624 7e7c5e4c balrog
            fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
625 7e7c5e4c balrog
                            __FUNCTION__, value);
626 7e7c5e4c balrog
            s->status |= 1 << 10;                                /* RTCERR */
627 7e7c5e4c balrog
            menelaus_update(s);
628 7e7c5e4c balrog
        }
629 aec454d2 balrog
        s->rtc.sec_offset = qemu_timedate_diff(&tm);
630 7e7c5e4c balrog
        break;
631 7e7c5e4c balrog
    case MENELAUS_RTC_SEC:
632 7e7c5e4c balrog
        s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
633 7e7c5e4c balrog
        break;
634 7e7c5e4c balrog
    case MENELAUS_RTC_MIN:
635 7e7c5e4c balrog
        s->rtc.tm.tm_min = from_bcd(value & 0x7f);
636 7e7c5e4c balrog
        break;
637 7e7c5e4c balrog
    case MENELAUS_RTC_HR:
638 7e7c5e4c balrog
        s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ?        /* MODE12_n24 */
639 7e7c5e4c balrog
                MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
640 7e7c5e4c balrog
                from_bcd(value & 0x3f);
641 7e7c5e4c balrog
        break;
642 7e7c5e4c balrog
    case MENELAUS_RTC_DAY:
643 7e7c5e4c balrog
        s->rtc.tm.tm_mday = from_bcd(value);
644 7e7c5e4c balrog
        break;
645 7e7c5e4c balrog
    case MENELAUS_RTC_MON:
646 7e7c5e4c balrog
        s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1;
647 7e7c5e4c balrog
        break;
648 7e7c5e4c balrog
    case MENELAUS_RTC_YR:
649 7e7c5e4c balrog
        s->rtc.tm.tm_year = 2000 + from_bcd(value);
650 7e7c5e4c balrog
        break;
651 7e7c5e4c balrog
    case MENELAUS_RTC_WKDAY:
652 7e7c5e4c balrog
        s->rtc.tm.tm_mday = from_bcd(value);
653 7e7c5e4c balrog
        break;
654 7e7c5e4c balrog
    case MENELAUS_RTC_AL_SEC:
655 7e7c5e4c balrog
        s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
656 7e7c5e4c balrog
        menelaus_alm_update(s);
657 7e7c5e4c balrog
        break;
658 7e7c5e4c balrog
    case MENELAUS_RTC_AL_MIN:
659 7e7c5e4c balrog
        s->rtc.alm.tm_min = from_bcd(value & 0x7f);
660 7e7c5e4c balrog
        menelaus_alm_update(s);
661 7e7c5e4c balrog
        break;
662 7e7c5e4c balrog
    case MENELAUS_RTC_AL_HR:
663 7e7c5e4c balrog
        s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ?        /* MODE12_n24 */
664 7e7c5e4c balrog
                MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
665 7e7c5e4c balrog
                from_bcd(value & 0x3f);
666 7e7c5e4c balrog
        menelaus_alm_update(s);
667 7e7c5e4c balrog
        break;
668 7e7c5e4c balrog
    case MENELAUS_RTC_AL_DAY:
669 7e7c5e4c balrog
        s->rtc.alm.tm_mday = from_bcd(value);
670 7e7c5e4c balrog
        menelaus_alm_update(s);
671 7e7c5e4c balrog
        break;
672 7e7c5e4c balrog
    case MENELAUS_RTC_AL_MON:
673 7e7c5e4c balrog
        s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1;
674 7e7c5e4c balrog
        menelaus_alm_update(s);
675 7e7c5e4c balrog
        break;
676 7e7c5e4c balrog
    case MENELAUS_RTC_AL_YR:
677 7e7c5e4c balrog
        s->rtc.alm.tm_year = 2000 + from_bcd(value);
678 7e7c5e4c balrog
        menelaus_alm_update(s);
679 7e7c5e4c balrog
        break;
680 7e7c5e4c balrog
    case MENELAUS_RTC_COMP_MSB:
681 7e7c5e4c balrog
        s->rtc.comp &= 0xff;
682 7e7c5e4c balrog
        s->rtc.comp |= value << 8;
683 7e7c5e4c balrog
        break;
684 7e7c5e4c balrog
    case MENELAUS_RTC_COMP_LSB:
685 7e7c5e4c balrog
        s->rtc.comp &= 0xff << 8;
686 7e7c5e4c balrog
        s->rtc.comp |= value;
687 7e7c5e4c balrog
        break;
688 7e7c5e4c balrog
689 7e7c5e4c balrog
    case MENELAUS_S1_PULL_EN:
690 7e7c5e4c balrog
        s->pull[0] = value;
691 7e7c5e4c balrog
        break;
692 7e7c5e4c balrog
    case MENELAUS_S1_PULL_DIR:
693 7e7c5e4c balrog
        s->pull[1] = value & 0x1f;
694 7e7c5e4c balrog
        break;
695 7e7c5e4c balrog
    case MENELAUS_S2_PULL_EN:
696 7e7c5e4c balrog
        s->pull[2] = value;
697 7e7c5e4c balrog
        break;
698 7e7c5e4c balrog
    case MENELAUS_S2_PULL_DIR:
699 7e7c5e4c balrog
        s->pull[3] = value & 0x1f;
700 7e7c5e4c balrog
        break;
701 7e7c5e4c balrog
702 7e7c5e4c balrog
    case MENELAUS_MCT_CTRL1:
703 7e7c5e4c balrog
        s->mmc_ctrl[0] = value & 0x7f;
704 7e7c5e4c balrog
        break;
705 7e7c5e4c balrog
    case MENELAUS_MCT_CTRL2:
706 7e7c5e4c balrog
        s->mmc_ctrl[1] = value;
707 7e7c5e4c balrog
        /* TODO update Card Detect interrupts */
708 7e7c5e4c balrog
        break;
709 7e7c5e4c balrog
    case MENELAUS_MCT_CTRL3:
710 7e7c5e4c balrog
        s->mmc_ctrl[2] = value & 0xf;
711 7e7c5e4c balrog
        break;
712 7e7c5e4c balrog
    case MENELAUS_DEBOUNCE1:
713 7e7c5e4c balrog
        s->mmc_debounce = value & 0x3f;
714 7e7c5e4c balrog
        break;
715 7e7c5e4c balrog
716 7e7c5e4c balrog
    default:
717 7e7c5e4c balrog
#ifdef VERBOSE
718 7e7c5e4c balrog
        printf("%s: unknown register %02x\n", __FUNCTION__, addr);
719 7e7c5e4c balrog
#endif
720 7e7c5e4c balrog
    }
721 7e7c5e4c balrog
}
722 7e7c5e4c balrog
723 7e7c5e4c balrog
static void menelaus_event(i2c_slave *i2c, enum i2c_event event)
724 7e7c5e4c balrog
{
725 7e7c5e4c balrog
    struct menelaus_s *s = (struct menelaus_s *) i2c;
726 7e7c5e4c balrog
727 7e7c5e4c balrog
    if (event == I2C_START_SEND)
728 7e7c5e4c balrog
        s->firstbyte = 1;
729 7e7c5e4c balrog
}
730 7e7c5e4c balrog
731 7e7c5e4c balrog
static int menelaus_tx(i2c_slave *i2c, uint8_t data)
732 7e7c5e4c balrog
{
733 7e7c5e4c balrog
    struct menelaus_s *s = (struct menelaus_s *) i2c;
734 7e7c5e4c balrog
    /* Interpret register address byte */
735 7e7c5e4c balrog
    if (s->firstbyte) {
736 7e7c5e4c balrog
        s->reg = data;
737 7e7c5e4c balrog
        s->firstbyte = 0;
738 7e7c5e4c balrog
    } else
739 7e7c5e4c balrog
        menelaus_write(s, s->reg ++, data);
740 7e7c5e4c balrog
741 7e7c5e4c balrog
    return 0;
742 7e7c5e4c balrog
}
743 7e7c5e4c balrog
744 7e7c5e4c balrog
static int menelaus_rx(i2c_slave *i2c)
745 7e7c5e4c balrog
{
746 7e7c5e4c balrog
    struct menelaus_s *s = (struct menelaus_s *) i2c;
747 7e7c5e4c balrog
748 7e7c5e4c balrog
    return menelaus_read(s, s->reg ++);
749 7e7c5e4c balrog
}
750 7e7c5e4c balrog
751 7e7c5e4c balrog
static void tm_put(QEMUFile *f, struct tm *tm) {
752 7e7c5e4c balrog
    qemu_put_be16(f, tm->tm_sec);
753 7e7c5e4c balrog
    qemu_put_be16(f, tm->tm_min);
754 7e7c5e4c balrog
    qemu_put_be16(f, tm->tm_hour);
755 7e7c5e4c balrog
    qemu_put_be16(f, tm->tm_mday);
756 7e7c5e4c balrog
    qemu_put_be16(f, tm->tm_min);
757 7e7c5e4c balrog
    qemu_put_be16(f, tm->tm_year);
758 7e7c5e4c balrog
}
759 7e7c5e4c balrog
760 7e7c5e4c balrog
static void tm_get(QEMUFile *f, struct tm *tm) {
761 7e7c5e4c balrog
    tm->tm_sec = qemu_get_be16(f);
762 7e7c5e4c balrog
    tm->tm_min = qemu_get_be16(f);
763 7e7c5e4c balrog
    tm->tm_hour = qemu_get_be16(f);
764 7e7c5e4c balrog
    tm->tm_mday = qemu_get_be16(f);
765 7e7c5e4c balrog
    tm->tm_min = qemu_get_be16(f);
766 7e7c5e4c balrog
    tm->tm_year = qemu_get_be16(f);
767 7e7c5e4c balrog
}
768 7e7c5e4c balrog
769 7e7c5e4c balrog
static void menelaus_save(QEMUFile *f, void *opaque)
770 7e7c5e4c balrog
{
771 7e7c5e4c balrog
    struct menelaus_s *s = (struct menelaus_s *) opaque;
772 7e7c5e4c balrog
773 7e7c5e4c balrog
    qemu_put_be32(f, s->firstbyte);
774 7e7c5e4c balrog
    qemu_put_8s(f, &s->reg);
775 7e7c5e4c balrog
776 7e7c5e4c balrog
    qemu_put_8s(f, &s->vcore[0]);
777 7e7c5e4c balrog
    qemu_put_8s(f, &s->vcore[1]);
778 7e7c5e4c balrog
    qemu_put_8s(f, &s->vcore[2]);
779 7e7c5e4c balrog
    qemu_put_8s(f, &s->vcore[3]);
780 7e7c5e4c balrog
    qemu_put_8s(f, &s->vcore[4]);
781 7e7c5e4c balrog
    qemu_put_8s(f, &s->dcdc[3]);
782 7e7c5e4c balrog
    qemu_put_8s(f, &s->dcdc[3]);
783 7e7c5e4c balrog
    qemu_put_8s(f, &s->dcdc[3]);
784 7e7c5e4c balrog
    qemu_put_8s(f, &s->ldo[0]);
785 7e7c5e4c balrog
    qemu_put_8s(f, &s->ldo[1]);
786 7e7c5e4c balrog
    qemu_put_8s(f, &s->ldo[2]);
787 7e7c5e4c balrog
    qemu_put_8s(f, &s->ldo[3]);
788 7e7c5e4c balrog
    qemu_put_8s(f, &s->ldo[4]);
789 7e7c5e4c balrog
    qemu_put_8s(f, &s->ldo[5]);
790 7e7c5e4c balrog
    qemu_put_8s(f, &s->ldo[6]);
791 7e7c5e4c balrog
    qemu_put_8s(f, &s->ldo[7]);
792 7e7c5e4c balrog
    qemu_put_8s(f, &s->sleep[0]);
793 7e7c5e4c balrog
    qemu_put_8s(f, &s->sleep[1]);
794 7e7c5e4c balrog
    qemu_put_8s(f, &s->osc);
795 7e7c5e4c balrog
    qemu_put_8s(f, &s->detect);
796 7e7c5e4c balrog
    qemu_put_be16s(f, &s->mask);
797 7e7c5e4c balrog
    qemu_put_be16s(f, &s->status);
798 7e7c5e4c balrog
    qemu_put_8s(f, &s->dir);
799 7e7c5e4c balrog
    qemu_put_8s(f, &s->inputs);
800 7e7c5e4c balrog
    qemu_put_8s(f, &s->outputs);
801 7e7c5e4c balrog
    qemu_put_8s(f, &s->bbsms);
802 7e7c5e4c balrog
    qemu_put_8s(f, &s->pull[0]);
803 7e7c5e4c balrog
    qemu_put_8s(f, &s->pull[1]);
804 7e7c5e4c balrog
    qemu_put_8s(f, &s->pull[2]);
805 7e7c5e4c balrog
    qemu_put_8s(f, &s->pull[3]);
806 7e7c5e4c balrog
    qemu_put_8s(f, &s->mmc_ctrl[0]);
807 7e7c5e4c balrog
    qemu_put_8s(f, &s->mmc_ctrl[1]);
808 7e7c5e4c balrog
    qemu_put_8s(f, &s->mmc_ctrl[2]);
809 7e7c5e4c balrog
    qemu_put_8s(f, &s->mmc_debounce);
810 7e7c5e4c balrog
    qemu_put_8s(f, &s->rtc.ctrl);
811 7e7c5e4c balrog
    qemu_put_be16s(f, &s->rtc.comp);
812 7e7c5e4c balrog
    /* Should be <= 1000 */
813 7e7c5e4c balrog
    qemu_put_be16(f, s->rtc.next - qemu_get_clock(rt_clock));
814 7e7c5e4c balrog
    tm_put(f, &s->rtc.new);
815 7e7c5e4c balrog
    tm_put(f, &s->rtc.alm);
816 7e7c5e4c balrog
    qemu_put_byte(f, s->pwrbtn_state);
817 7e7c5e4c balrog
818 7e7c5e4c balrog
    i2c_slave_save(f, &s->i2c);
819 7e7c5e4c balrog
}
820 7e7c5e4c balrog
821 7e7c5e4c balrog
static int menelaus_load(QEMUFile *f, void *opaque, int version_id)
822 7e7c5e4c balrog
{
823 7e7c5e4c balrog
    struct menelaus_s *s = (struct menelaus_s *) opaque;
824 7e7c5e4c balrog
825 7e7c5e4c balrog
    s->firstbyte = qemu_get_be32(f);
826 7e7c5e4c balrog
    qemu_get_8s(f, &s->reg);
827 7e7c5e4c balrog
828 7e7c5e4c balrog
    if (s->rtc.ctrl & 1)                                        /* RTC_EN */
829 7e7c5e4c balrog
        menelaus_rtc_stop(s);
830 7e7c5e4c balrog
    qemu_get_8s(f, &s->vcore[0]);
831 7e7c5e4c balrog
    qemu_get_8s(f, &s->vcore[1]);
832 7e7c5e4c balrog
    qemu_get_8s(f, &s->vcore[2]);
833 7e7c5e4c balrog
    qemu_get_8s(f, &s->vcore[3]);
834 7e7c5e4c balrog
    qemu_get_8s(f, &s->vcore[4]);
835 7e7c5e4c balrog
    qemu_get_8s(f, &s->dcdc[3]);
836 7e7c5e4c balrog
    qemu_get_8s(f, &s->dcdc[3]);
837 7e7c5e4c balrog
    qemu_get_8s(f, &s->dcdc[3]);
838 7e7c5e4c balrog
    qemu_get_8s(f, &s->ldo[0]);
839 7e7c5e4c balrog
    qemu_get_8s(f, &s->ldo[1]);
840 7e7c5e4c balrog
    qemu_get_8s(f, &s->ldo[2]);
841 7e7c5e4c balrog
    qemu_get_8s(f, &s->ldo[3]);
842 7e7c5e4c balrog
    qemu_get_8s(f, &s->ldo[4]);
843 7e7c5e4c balrog
    qemu_get_8s(f, &s->ldo[5]);
844 7e7c5e4c balrog
    qemu_get_8s(f, &s->ldo[6]);
845 7e7c5e4c balrog
    qemu_get_8s(f, &s->ldo[7]);
846 7e7c5e4c balrog
    qemu_get_8s(f, &s->sleep[0]);
847 7e7c5e4c balrog
    qemu_get_8s(f, &s->sleep[1]);
848 7e7c5e4c balrog
    qemu_get_8s(f, &s->osc);
849 7e7c5e4c balrog
    qemu_get_8s(f, &s->detect);
850 7e7c5e4c balrog
    qemu_get_be16s(f, &s->mask);
851 7e7c5e4c balrog
    qemu_get_be16s(f, &s->status);
852 7e7c5e4c balrog
    qemu_get_8s(f, &s->dir);
853 7e7c5e4c balrog
    qemu_get_8s(f, &s->inputs);
854 7e7c5e4c balrog
    qemu_get_8s(f, &s->outputs);
855 7e7c5e4c balrog
    qemu_get_8s(f, &s->bbsms);
856 7e7c5e4c balrog
    qemu_get_8s(f, &s->pull[0]);
857 7e7c5e4c balrog
    qemu_get_8s(f, &s->pull[1]);
858 7e7c5e4c balrog
    qemu_get_8s(f, &s->pull[2]);
859 7e7c5e4c balrog
    qemu_get_8s(f, &s->pull[3]);
860 7e7c5e4c balrog
    qemu_get_8s(f, &s->mmc_ctrl[0]);
861 7e7c5e4c balrog
    qemu_get_8s(f, &s->mmc_ctrl[1]);
862 7e7c5e4c balrog
    qemu_get_8s(f, &s->mmc_ctrl[2]);
863 7e7c5e4c balrog
    qemu_get_8s(f, &s->mmc_debounce);
864 7e7c5e4c balrog
    qemu_get_8s(f, &s->rtc.ctrl);
865 7e7c5e4c balrog
    qemu_get_be16s(f, &s->rtc.comp);
866 7e7c5e4c balrog
    s->rtc.next = qemu_get_be16(f);
867 7e7c5e4c balrog
    tm_get(f, &s->rtc.new);
868 7e7c5e4c balrog
    tm_get(f, &s->rtc.alm);
869 7e7c5e4c balrog
    s->pwrbtn_state = qemu_get_byte(f);
870 7e7c5e4c balrog
    menelaus_alm_update(s);
871 7e7c5e4c balrog
    menelaus_update(s);
872 7e7c5e4c balrog
    if (s->rtc.ctrl & 1)                                        /* RTC_EN */
873 7e7c5e4c balrog
        menelaus_rtc_start(s);
874 7e7c5e4c balrog
875 7e7c5e4c balrog
    i2c_slave_load(f, &s->i2c);
876 7e7c5e4c balrog
    return 0;
877 7e7c5e4c balrog
}
878 7e7c5e4c balrog
879 7e7c5e4c balrog
static int menelaus_iid = 0;
880 7e7c5e4c balrog
881 7e7c5e4c balrog
i2c_slave *twl92230_init(i2c_bus *bus, qemu_irq irq)
882 7e7c5e4c balrog
{
883 7e7c5e4c balrog
    struct menelaus_s *s = (struct menelaus_s *)
884 7e7c5e4c balrog
            i2c_slave_init(bus, 0, sizeof(struct menelaus_s));
885 7e7c5e4c balrog
886 7e7c5e4c balrog
    s->i2c.event = menelaus_event;
887 7e7c5e4c balrog
    s->i2c.recv = menelaus_rx;
888 7e7c5e4c balrog
    s->i2c.send = menelaus_tx;
889 7e7c5e4c balrog
890 7e7c5e4c balrog
    s->irq = irq;
891 7e7c5e4c balrog
    s->rtc.hz = qemu_new_timer(rt_clock, menelaus_rtc_hz, s);
892 7e7c5e4c balrog
    s->in = qemu_allocate_irqs(menelaus_gpio_set, s, 3);
893 7e7c5e4c balrog
    s->pwrbtn = qemu_allocate_irqs(menelaus_pwrbtn_set, s, 1)[0];
894 7e7c5e4c balrog
895 7e7c5e4c balrog
    menelaus_reset(&s->i2c);
896 7e7c5e4c balrog
897 7e7c5e4c balrog
    register_savevm("menelaus", menelaus_iid ++,
898 7e7c5e4c balrog
                    0, menelaus_save, menelaus_load, s);
899 7e7c5e4c balrog
900 7e7c5e4c balrog
    return &s->i2c;
901 7e7c5e4c balrog
}
902 7e7c5e4c balrog
903 7e7c5e4c balrog
qemu_irq *twl92230_gpio_in_get(i2c_slave *i2c)
904 7e7c5e4c balrog
{
905 7e7c5e4c balrog
    struct menelaus_s *s = (struct menelaus_s *) i2c;
906 7e7c5e4c balrog
907 7e7c5e4c balrog
    return s->in;
908 7e7c5e4c balrog
}
909 7e7c5e4c balrog
910 7e7c5e4c balrog
void twl92230_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler)
911 7e7c5e4c balrog
{
912 7e7c5e4c balrog
    struct menelaus_s *s = (struct menelaus_s *) i2c;
913 7e7c5e4c balrog
914 7e7c5e4c balrog
    if (line >= 3 || line < 0) {
915 7e7c5e4c balrog
        fprintf(stderr, "%s: No GPO line %i\n", __FUNCTION__, line);
916 7e7c5e4c balrog
        exit(-1);
917 7e7c5e4c balrog
    }
918 7e7c5e4c balrog
    s->handler[line] = handler;
919 7e7c5e4c balrog
}