root / hw / m48t59.c @ 60398748
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1 | a541f297 | bellard | /*
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2 | 819385c5 | bellard | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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3 | 5fafdf24 | ths | *
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4 | 3ccacc4a | blueswir1 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "nvram.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | d27cf0ae | Blue Swirl | #include "sysbus.h" |
29 | f80237d4 | Blue Swirl | #include "isa.h" |
30 | a541f297 | bellard | |
31 | 13ab5daa | bellard | //#define DEBUG_NVRAM
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32 | a541f297 | bellard | |
33 | 13ab5daa | bellard | #if defined(DEBUG_NVRAM)
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34 | 001faf32 | Blue Swirl | #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
35 | a541f297 | bellard | #else
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36 | 001faf32 | Blue Swirl | #define NVRAM_PRINTF(fmt, ...) do { } while (0) |
37 | a541f297 | bellard | #endif
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38 | a541f297 | bellard | |
39 | 819385c5 | bellard | /*
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40 | 4aed2c33 | blueswir1 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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41 | 819385c5 | bellard | * alarm and a watchdog timer and related control registers. In the
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42 | 819385c5 | bellard | * PPC platform there is also a nvram lock function.
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43 | 819385c5 | bellard | */
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44 | 930f3fe1 | Blue Swirl | |
45 | 930f3fe1 | Blue Swirl | /*
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46 | 930f3fe1 | Blue Swirl | * Chipset docs:
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47 | 930f3fe1 | Blue Swirl | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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48 | 930f3fe1 | Blue Swirl | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
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49 | 930f3fe1 | Blue Swirl | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
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50 | 930f3fe1 | Blue Swirl | */
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51 | 930f3fe1 | Blue Swirl | |
52 | c227f099 | Anthony Liguori | struct m48t59_t {
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53 | 819385c5 | bellard | /* Model parameters */
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54 | ee6847d1 | Gerd Hoffmann | uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
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55 | a541f297 | bellard | /* Hardware parameters */
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56 | d537cf6c | pbrook | qemu_irq IRQ; |
57 | a541f297 | bellard | uint32_t io_base; |
58 | ee6847d1 | Gerd Hoffmann | uint32_t size; |
59 | a541f297 | bellard | /* RTC management */
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60 | a541f297 | bellard | time_t time_offset; |
61 | a541f297 | bellard | time_t stop_time; |
62 | a541f297 | bellard | /* Alarm & watchdog */
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63 | f6503059 | balrog | struct tm alarm;
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64 | a541f297 | bellard | struct QEMUTimer *alrm_timer;
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65 | a541f297 | bellard | struct QEMUTimer *wd_timer;
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66 | a541f297 | bellard | /* NVRAM storage */
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67 | 13ab5daa | bellard | uint8_t lock; |
68 | a541f297 | bellard | uint16_t addr; |
69 | a541f297 | bellard | uint8_t *buffer; |
70 | c5df018e | bellard | }; |
71 | a541f297 | bellard | |
72 | f80237d4 | Blue Swirl | typedef struct M48t59ISAState { |
73 | f80237d4 | Blue Swirl | ISADevice busdev; |
74 | c227f099 | Anthony Liguori | m48t59_t state; |
75 | f80237d4 | Blue Swirl | } M48t59ISAState; |
76 | f80237d4 | Blue Swirl | |
77 | f80237d4 | Blue Swirl | typedef struct M48t59SysBusState { |
78 | f80237d4 | Blue Swirl | SysBusDevice busdev; |
79 | c227f099 | Anthony Liguori | m48t59_t state; |
80 | f80237d4 | Blue Swirl | } M48t59SysBusState; |
81 | f80237d4 | Blue Swirl | |
82 | a541f297 | bellard | /* Fake timer functions */
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83 | a541f297 | bellard | /* Generic helpers for BCD */
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84 | a541f297 | bellard | static inline uint8_t toBCD (uint8_t value) |
85 | a541f297 | bellard | { |
86 | a541f297 | bellard | return (((value / 10) % 10) << 4) | (value % 10); |
87 | a541f297 | bellard | } |
88 | a541f297 | bellard | |
89 | a541f297 | bellard | static inline uint8_t fromBCD (uint8_t BCD) |
90 | a541f297 | bellard | { |
91 | a541f297 | bellard | return ((BCD >> 4) * 10) + (BCD & 0x0F); |
92 | a541f297 | bellard | } |
93 | a541f297 | bellard | |
94 | a541f297 | bellard | /* Alarm management */
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95 | a541f297 | bellard | static void alarm_cb (void *opaque) |
96 | a541f297 | bellard | { |
97 | f6503059 | balrog | struct tm tm;
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98 | a541f297 | bellard | uint64_t next_time; |
99 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
100 | a541f297 | bellard | |
101 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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102 | 5fafdf24 | ths | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
103 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
104 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
105 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
106 | f6503059 | balrog | /* Repeat once a month */
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107 | f6503059 | balrog | qemu_get_timedate(&tm, NVRAM->time_offset); |
108 | f6503059 | balrog | tm.tm_mon++; |
109 | f6503059 | balrog | if (tm.tm_mon == 13) { |
110 | f6503059 | balrog | tm.tm_mon = 1;
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111 | f6503059 | balrog | tm.tm_year++; |
112 | f6503059 | balrog | } |
113 | f6503059 | balrog | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
114 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
115 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
116 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
117 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
118 | f6503059 | balrog | /* Repeat once a day */
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119 | f6503059 | balrog | next_time = 24 * 60 * 60; |
120 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
121 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
122 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
123 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
124 | f6503059 | balrog | /* Repeat once an hour */
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125 | f6503059 | balrog | next_time = 60 * 60; |
126 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
127 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
128 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
129 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
130 | f6503059 | balrog | /* Repeat once a minute */
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131 | f6503059 | balrog | next_time = 60;
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132 | a541f297 | bellard | } else {
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133 | f6503059 | balrog | /* Repeat once a second */
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134 | f6503059 | balrog | next_time = 1;
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135 | a541f297 | bellard | } |
136 | f6503059 | balrog | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) + |
137 | f6503059 | balrog | next_time * 1000);
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138 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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139 | a541f297 | bellard | } |
140 | a541f297 | bellard | |
141 | c227f099 | Anthony Liguori | static void set_alarm (m48t59_t *NVRAM) |
142 | f6503059 | balrog | { |
143 | f6503059 | balrog | int diff;
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144 | f6503059 | balrog | if (NVRAM->alrm_timer != NULL) { |
145 | f6503059 | balrog | qemu_del_timer(NVRAM->alrm_timer); |
146 | f6503059 | balrog | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
147 | f6503059 | balrog | if (diff > 0) |
148 | f6503059 | balrog | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
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149 | f6503059 | balrog | } |
150 | f6503059 | balrog | } |
151 | a541f297 | bellard | |
152 | f6503059 | balrog | /* RTC management helpers */
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153 | c227f099 | Anthony Liguori | static inline void get_time (m48t59_t *NVRAM, struct tm *tm) |
154 | a541f297 | bellard | { |
155 | f6503059 | balrog | qemu_get_timedate(tm, NVRAM->time_offset); |
156 | a541f297 | bellard | } |
157 | a541f297 | bellard | |
158 | c227f099 | Anthony Liguori | static void set_time (m48t59_t *NVRAM, struct tm *tm) |
159 | a541f297 | bellard | { |
160 | f6503059 | balrog | NVRAM->time_offset = qemu_timedate_diff(tm); |
161 | f6503059 | balrog | set_alarm(NVRAM); |
162 | a541f297 | bellard | } |
163 | a541f297 | bellard | |
164 | a541f297 | bellard | /* Watchdog management */
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165 | a541f297 | bellard | static void watchdog_cb (void *opaque) |
166 | a541f297 | bellard | { |
167 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
168 | a541f297 | bellard | |
169 | a541f297 | bellard | NVRAM->buffer[0x1FF0] |= 0x80; |
170 | a541f297 | bellard | if (NVRAM->buffer[0x1FF7] & 0x80) { |
171 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = 0x00; |
172 | a541f297 | bellard | NVRAM->buffer[0x1FFC] &= ~0x40; |
173 | 13ab5daa | bellard | /* May it be a hw CPU Reset instead ? */
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174 | d7d02e3c | bellard | qemu_system_reset_request(); |
175 | a541f297 | bellard | } else {
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176 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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177 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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178 | a541f297 | bellard | } |
179 | a541f297 | bellard | } |
180 | a541f297 | bellard | |
181 | c227f099 | Anthony Liguori | static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
182 | a541f297 | bellard | { |
183 | a541f297 | bellard | uint64_t interval; /* in 1/16 seconds */
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184 | a541f297 | bellard | |
185 | 868d585a | j_mayer | NVRAM->buffer[0x1FF0] &= ~0x80; |
186 | a541f297 | bellard | if (NVRAM->wd_timer != NULL) { |
187 | a541f297 | bellard | qemu_del_timer(NVRAM->wd_timer); |
188 | 868d585a | j_mayer | if (value != 0) { |
189 | 868d585a | j_mayer | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
190 | 868d585a | j_mayer | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
191 | 868d585a | j_mayer | ((interval * 1000) >> 4)); |
192 | 868d585a | j_mayer | } |
193 | a541f297 | bellard | } |
194 | a541f297 | bellard | } |
195 | a541f297 | bellard | |
196 | a541f297 | bellard | /* Direct access to NVRAM */
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197 | 897b4c6c | j_mayer | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
198 | a541f297 | bellard | { |
199 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
200 | a541f297 | bellard | struct tm tm;
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201 | a541f297 | bellard | int tmp;
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202 | a541f297 | bellard | |
203 | 819385c5 | bellard | if (addr > 0x1FF8 && addr < 0x2000) |
204 | 819385c5 | bellard | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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205 | 4aed2c33 | blueswir1 | |
206 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
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207 | 4aed2c33 | blueswir1 | if ((NVRAM->type == 2 && addr < 0x7f8) || |
208 | 4aed2c33 | blueswir1 | (NVRAM->type == 8 && addr < 0x1ff8) || |
209 | 4aed2c33 | blueswir1 | (NVRAM->type == 59 && addr < 0x1ff0)) |
210 | 819385c5 | bellard | goto do_write;
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211 | 4aed2c33 | blueswir1 | |
212 | 4aed2c33 | blueswir1 | /* TOD access */
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213 | 819385c5 | bellard | switch (addr) {
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214 | a541f297 | bellard | case 0x1FF0: |
215 | a541f297 | bellard | /* flags register : read-only */
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216 | a541f297 | bellard | break;
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217 | a541f297 | bellard | case 0x1FF1: |
218 | a541f297 | bellard | /* unused */
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219 | a541f297 | bellard | break;
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220 | a541f297 | bellard | case 0x1FF2: |
221 | a541f297 | bellard | /* alarm seconds */
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222 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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223 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
224 | f6503059 | balrog | NVRAM->alarm.tm_sec = tmp; |
225 | 819385c5 | bellard | NVRAM->buffer[0x1FF2] = val;
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226 | f6503059 | balrog | set_alarm(NVRAM); |
227 | 819385c5 | bellard | } |
228 | a541f297 | bellard | break;
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229 | a541f297 | bellard | case 0x1FF3: |
230 | a541f297 | bellard | /* alarm minutes */
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231 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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232 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
233 | f6503059 | balrog | NVRAM->alarm.tm_min = tmp; |
234 | 819385c5 | bellard | NVRAM->buffer[0x1FF3] = val;
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235 | f6503059 | balrog | set_alarm(NVRAM); |
236 | 819385c5 | bellard | } |
237 | a541f297 | bellard | break;
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238 | a541f297 | bellard | case 0x1FF4: |
239 | a541f297 | bellard | /* alarm hours */
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240 | 819385c5 | bellard | tmp = fromBCD(val & 0x3F);
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241 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 23) { |
242 | f6503059 | balrog | NVRAM->alarm.tm_hour = tmp; |
243 | 819385c5 | bellard | NVRAM->buffer[0x1FF4] = val;
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244 | f6503059 | balrog | set_alarm(NVRAM); |
245 | 819385c5 | bellard | } |
246 | a541f297 | bellard | break;
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247 | a541f297 | bellard | case 0x1FF5: |
248 | a541f297 | bellard | /* alarm date */
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249 | 819385c5 | bellard | tmp = fromBCD(val & 0x1F);
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250 | 819385c5 | bellard | if (tmp != 0) { |
251 | f6503059 | balrog | NVRAM->alarm.tm_mday = tmp; |
252 | 819385c5 | bellard | NVRAM->buffer[0x1FF5] = val;
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253 | f6503059 | balrog | set_alarm(NVRAM); |
254 | 819385c5 | bellard | } |
255 | a541f297 | bellard | break;
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256 | a541f297 | bellard | case 0x1FF6: |
257 | a541f297 | bellard | /* interrupts */
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258 | 819385c5 | bellard | NVRAM->buffer[0x1FF6] = val;
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259 | a541f297 | bellard | break;
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260 | a541f297 | bellard | case 0x1FF7: |
261 | a541f297 | bellard | /* watchdog */
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262 | 819385c5 | bellard | NVRAM->buffer[0x1FF7] = val;
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263 | 819385c5 | bellard | set_up_watchdog(NVRAM, val); |
264 | a541f297 | bellard | break;
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265 | a541f297 | bellard | case 0x1FF8: |
266 | 4aed2c33 | blueswir1 | case 0x07F8: |
267 | a541f297 | bellard | /* control */
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268 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
269 | a541f297 | bellard | break;
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270 | a541f297 | bellard | case 0x1FF9: |
271 | 4aed2c33 | blueswir1 | case 0x07F9: |
272 | a541f297 | bellard | /* seconds (BCD) */
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273 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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274 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
275 | a541f297 | bellard | get_time(NVRAM, &tm); |
276 | a541f297 | bellard | tm.tm_sec = tmp; |
277 | a541f297 | bellard | set_time(NVRAM, &tm); |
278 | a541f297 | bellard | } |
279 | f6503059 | balrog | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
280 | a541f297 | bellard | if (val & 0x80) { |
281 | a541f297 | bellard | NVRAM->stop_time = time(NULL);
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282 | a541f297 | bellard | } else {
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283 | a541f297 | bellard | NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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284 | a541f297 | bellard | NVRAM->stop_time = 0;
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285 | a541f297 | bellard | } |
286 | a541f297 | bellard | } |
287 | f6503059 | balrog | NVRAM->buffer[addr] = val & 0x80;
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288 | a541f297 | bellard | break;
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289 | a541f297 | bellard | case 0x1FFA: |
290 | 4aed2c33 | blueswir1 | case 0x07FA: |
291 | a541f297 | bellard | /* minutes (BCD) */
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292 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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293 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
294 | a541f297 | bellard | get_time(NVRAM, &tm); |
295 | a541f297 | bellard | tm.tm_min = tmp; |
296 | a541f297 | bellard | set_time(NVRAM, &tm); |
297 | a541f297 | bellard | } |
298 | a541f297 | bellard | break;
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299 | a541f297 | bellard | case 0x1FFB: |
300 | 4aed2c33 | blueswir1 | case 0x07FB: |
301 | a541f297 | bellard | /* hours (BCD) */
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302 | a541f297 | bellard | tmp = fromBCD(val & 0x3F);
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303 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
304 | a541f297 | bellard | get_time(NVRAM, &tm); |
305 | a541f297 | bellard | tm.tm_hour = tmp; |
306 | a541f297 | bellard | set_time(NVRAM, &tm); |
307 | a541f297 | bellard | } |
308 | a541f297 | bellard | break;
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309 | a541f297 | bellard | case 0x1FFC: |
310 | 4aed2c33 | blueswir1 | case 0x07FC: |
311 | a541f297 | bellard | /* day of the week / century */
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312 | a541f297 | bellard | tmp = fromBCD(val & 0x07);
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313 | a541f297 | bellard | get_time(NVRAM, &tm); |
314 | a541f297 | bellard | tm.tm_wday = tmp; |
315 | a541f297 | bellard | set_time(NVRAM, &tm); |
316 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = val & 0x40;
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317 | a541f297 | bellard | break;
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318 | a541f297 | bellard | case 0x1FFD: |
319 | 4aed2c33 | blueswir1 | case 0x07FD: |
320 | a541f297 | bellard | /* date */
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321 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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322 | a541f297 | bellard | if (tmp != 0) { |
323 | a541f297 | bellard | get_time(NVRAM, &tm); |
324 | a541f297 | bellard | tm.tm_mday = tmp; |
325 | a541f297 | bellard | set_time(NVRAM, &tm); |
326 | a541f297 | bellard | } |
327 | a541f297 | bellard | break;
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328 | a541f297 | bellard | case 0x1FFE: |
329 | 4aed2c33 | blueswir1 | case 0x07FE: |
330 | a541f297 | bellard | /* month */
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331 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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332 | a541f297 | bellard | if (tmp >= 1 && tmp <= 12) { |
333 | a541f297 | bellard | get_time(NVRAM, &tm); |
334 | a541f297 | bellard | tm.tm_mon = tmp - 1;
|
335 | a541f297 | bellard | set_time(NVRAM, &tm); |
336 | a541f297 | bellard | } |
337 | a541f297 | bellard | break;
|
338 | a541f297 | bellard | case 0x1FFF: |
339 | 4aed2c33 | blueswir1 | case 0x07FF: |
340 | a541f297 | bellard | /* year */
|
341 | a541f297 | bellard | tmp = fromBCD(val); |
342 | a541f297 | bellard | if (tmp >= 0 && tmp <= 99) { |
343 | a541f297 | bellard | get_time(NVRAM, &tm); |
344 | 180b700d | bellard | if (NVRAM->type == 8) |
345 | 180b700d | bellard | tm.tm_year = fromBCD(val) + 68; // Base year is 1968 |
346 | 180b700d | bellard | else
|
347 | 180b700d | bellard | tm.tm_year = fromBCD(val); |
348 | a541f297 | bellard | set_time(NVRAM, &tm); |
349 | a541f297 | bellard | } |
350 | a541f297 | bellard | break;
|
351 | a541f297 | bellard | default:
|
352 | 13ab5daa | bellard | /* Check lock registers state */
|
353 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
354 | 13ab5daa | bellard | break;
|
355 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
356 | 13ab5daa | bellard | break;
|
357 | 819385c5 | bellard | do_write:
|
358 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
359 | 819385c5 | bellard | NVRAM->buffer[addr] = val & 0xFF;
|
360 | a541f297 | bellard | } |
361 | a541f297 | bellard | break;
|
362 | a541f297 | bellard | } |
363 | a541f297 | bellard | } |
364 | a541f297 | bellard | |
365 | 897b4c6c | j_mayer | uint32_t m48t59_read (void *opaque, uint32_t addr)
|
366 | a541f297 | bellard | { |
367 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
368 | a541f297 | bellard | struct tm tm;
|
369 | a541f297 | bellard | uint32_t retval = 0xFF;
|
370 | a541f297 | bellard | |
371 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
|
372 | 4aed2c33 | blueswir1 | if ((NVRAM->type == 2 && addr < 0x078f) || |
373 | 4aed2c33 | blueswir1 | (NVRAM->type == 8 && addr < 0x1ff8) || |
374 | 4aed2c33 | blueswir1 | (NVRAM->type == 59 && addr < 0x1ff0)) |
375 | 819385c5 | bellard | goto do_read;
|
376 | 4aed2c33 | blueswir1 | |
377 | 4aed2c33 | blueswir1 | /* TOD access */
|
378 | 819385c5 | bellard | switch (addr) {
|
379 | a541f297 | bellard | case 0x1FF0: |
380 | a541f297 | bellard | /* flags register */
|
381 | a541f297 | bellard | goto do_read;
|
382 | a541f297 | bellard | case 0x1FF1: |
383 | a541f297 | bellard | /* unused */
|
384 | a541f297 | bellard | retval = 0;
|
385 | a541f297 | bellard | break;
|
386 | a541f297 | bellard | case 0x1FF2: |
387 | a541f297 | bellard | /* alarm seconds */
|
388 | a541f297 | bellard | goto do_read;
|
389 | a541f297 | bellard | case 0x1FF3: |
390 | a541f297 | bellard | /* alarm minutes */
|
391 | a541f297 | bellard | goto do_read;
|
392 | a541f297 | bellard | case 0x1FF4: |
393 | a541f297 | bellard | /* alarm hours */
|
394 | a541f297 | bellard | goto do_read;
|
395 | a541f297 | bellard | case 0x1FF5: |
396 | a541f297 | bellard | /* alarm date */
|
397 | a541f297 | bellard | goto do_read;
|
398 | a541f297 | bellard | case 0x1FF6: |
399 | a541f297 | bellard | /* interrupts */
|
400 | a541f297 | bellard | goto do_read;
|
401 | a541f297 | bellard | case 0x1FF7: |
402 | a541f297 | bellard | /* A read resets the watchdog */
|
403 | a541f297 | bellard | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
404 | a541f297 | bellard | goto do_read;
|
405 | a541f297 | bellard | case 0x1FF8: |
406 | 4aed2c33 | blueswir1 | case 0x07F8: |
407 | a541f297 | bellard | /* control */
|
408 | a541f297 | bellard | goto do_read;
|
409 | a541f297 | bellard | case 0x1FF9: |
410 | 4aed2c33 | blueswir1 | case 0x07F9: |
411 | a541f297 | bellard | /* seconds (BCD) */
|
412 | a541f297 | bellard | get_time(NVRAM, &tm); |
413 | 4aed2c33 | blueswir1 | retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
|
414 | a541f297 | bellard | break;
|
415 | a541f297 | bellard | case 0x1FFA: |
416 | 4aed2c33 | blueswir1 | case 0x07FA: |
417 | a541f297 | bellard | /* minutes (BCD) */
|
418 | a541f297 | bellard | get_time(NVRAM, &tm); |
419 | a541f297 | bellard | retval = toBCD(tm.tm_min); |
420 | a541f297 | bellard | break;
|
421 | a541f297 | bellard | case 0x1FFB: |
422 | 4aed2c33 | blueswir1 | case 0x07FB: |
423 | a541f297 | bellard | /* hours (BCD) */
|
424 | a541f297 | bellard | get_time(NVRAM, &tm); |
425 | a541f297 | bellard | retval = toBCD(tm.tm_hour); |
426 | a541f297 | bellard | break;
|
427 | a541f297 | bellard | case 0x1FFC: |
428 | 4aed2c33 | blueswir1 | case 0x07FC: |
429 | a541f297 | bellard | /* day of the week / century */
|
430 | a541f297 | bellard | get_time(NVRAM, &tm); |
431 | 4aed2c33 | blueswir1 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
432 | a541f297 | bellard | break;
|
433 | a541f297 | bellard | case 0x1FFD: |
434 | 4aed2c33 | blueswir1 | case 0x07FD: |
435 | a541f297 | bellard | /* date */
|
436 | a541f297 | bellard | get_time(NVRAM, &tm); |
437 | a541f297 | bellard | retval = toBCD(tm.tm_mday); |
438 | a541f297 | bellard | break;
|
439 | a541f297 | bellard | case 0x1FFE: |
440 | 4aed2c33 | blueswir1 | case 0x07FE: |
441 | a541f297 | bellard | /* month */
|
442 | a541f297 | bellard | get_time(NVRAM, &tm); |
443 | a541f297 | bellard | retval = toBCD(tm.tm_mon + 1);
|
444 | a541f297 | bellard | break;
|
445 | a541f297 | bellard | case 0x1FFF: |
446 | 4aed2c33 | blueswir1 | case 0x07FF: |
447 | a541f297 | bellard | /* year */
|
448 | a541f297 | bellard | get_time(NVRAM, &tm); |
449 | 5fafdf24 | ths | if (NVRAM->type == 8) |
450 | 180b700d | bellard | retval = toBCD(tm.tm_year - 68); // Base year is 1968 |
451 | 180b700d | bellard | else
|
452 | 180b700d | bellard | retval = toBCD(tm.tm_year); |
453 | a541f297 | bellard | break;
|
454 | a541f297 | bellard | default:
|
455 | 13ab5daa | bellard | /* Check lock registers state */
|
456 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
457 | 13ab5daa | bellard | break;
|
458 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
459 | 13ab5daa | bellard | break;
|
460 | 819385c5 | bellard | do_read:
|
461 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
462 | 819385c5 | bellard | retval = NVRAM->buffer[addr]; |
463 | a541f297 | bellard | } |
464 | a541f297 | bellard | break;
|
465 | a541f297 | bellard | } |
466 | 819385c5 | bellard | if (addr > 0x1FF9 && addr < 0x2000) |
467 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
468 | a541f297 | bellard | |
469 | a541f297 | bellard | return retval;
|
470 | a541f297 | bellard | } |
471 | a541f297 | bellard | |
472 | 897b4c6c | j_mayer | void m48t59_set_addr (void *opaque, uint32_t addr) |
473 | a541f297 | bellard | { |
474 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
475 | 897b4c6c | j_mayer | |
476 | a541f297 | bellard | NVRAM->addr = addr; |
477 | a541f297 | bellard | } |
478 | a541f297 | bellard | |
479 | 897b4c6c | j_mayer | void m48t59_toggle_lock (void *opaque, int lock) |
480 | 13ab5daa | bellard | { |
481 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
482 | 897b4c6c | j_mayer | |
483 | 13ab5daa | bellard | NVRAM->lock ^= 1 << lock;
|
484 | 13ab5daa | bellard | } |
485 | 13ab5daa | bellard | |
486 | a541f297 | bellard | /* IO access to NVRAM */
|
487 | a541f297 | bellard | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
488 | a541f297 | bellard | { |
489 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
490 | a541f297 | bellard | |
491 | a541f297 | bellard | addr -= NVRAM->io_base; |
492 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
493 | a541f297 | bellard | switch (addr) {
|
494 | a541f297 | bellard | case 0: |
495 | a541f297 | bellard | NVRAM->addr &= ~0x00FF;
|
496 | a541f297 | bellard | NVRAM->addr |= val; |
497 | a541f297 | bellard | break;
|
498 | a541f297 | bellard | case 1: |
499 | a541f297 | bellard | NVRAM->addr &= ~0xFF00;
|
500 | a541f297 | bellard | NVRAM->addr |= val << 8;
|
501 | a541f297 | bellard | break;
|
502 | a541f297 | bellard | case 3: |
503 | 819385c5 | bellard | m48t59_write(NVRAM, val, NVRAM->addr); |
504 | a541f297 | bellard | NVRAM->addr = 0x0000;
|
505 | a541f297 | bellard | break;
|
506 | a541f297 | bellard | default:
|
507 | a541f297 | bellard | break;
|
508 | a541f297 | bellard | } |
509 | a541f297 | bellard | } |
510 | a541f297 | bellard | |
511 | a541f297 | bellard | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
512 | a541f297 | bellard | { |
513 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
514 | 13ab5daa | bellard | uint32_t retval; |
515 | a541f297 | bellard | |
516 | 13ab5daa | bellard | addr -= NVRAM->io_base; |
517 | 13ab5daa | bellard | switch (addr) {
|
518 | 13ab5daa | bellard | case 3: |
519 | 819385c5 | bellard | retval = m48t59_read(NVRAM, NVRAM->addr); |
520 | 13ab5daa | bellard | break;
|
521 | 13ab5daa | bellard | default:
|
522 | 13ab5daa | bellard | retval = -1;
|
523 | 13ab5daa | bellard | break;
|
524 | 13ab5daa | bellard | } |
525 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
526 | a541f297 | bellard | |
527 | 13ab5daa | bellard | return retval;
|
528 | a541f297 | bellard | } |
529 | a541f297 | bellard | |
530 | c227f099 | Anthony Liguori | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
531 | e1bb04f7 | bellard | { |
532 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
533 | 3b46e624 | ths | |
534 | 819385c5 | bellard | m48t59_write(NVRAM, addr, value & 0xff);
|
535 | e1bb04f7 | bellard | } |
536 | e1bb04f7 | bellard | |
537 | c227f099 | Anthony Liguori | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
538 | e1bb04f7 | bellard | { |
539 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
540 | 3b46e624 | ths | |
541 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
542 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, value & 0xff); |
543 | e1bb04f7 | bellard | } |
544 | e1bb04f7 | bellard | |
545 | c227f099 | Anthony Liguori | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
546 | e1bb04f7 | bellard | { |
547 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
548 | 3b46e624 | ths | |
549 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
550 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
551 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
552 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 3, value & 0xff); |
553 | e1bb04f7 | bellard | } |
554 | e1bb04f7 | bellard | |
555 | c227f099 | Anthony Liguori | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
556 | e1bb04f7 | bellard | { |
557 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
558 | 819385c5 | bellard | uint32_t retval; |
559 | 3b46e624 | ths | |
560 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr); |
561 | e1bb04f7 | bellard | return retval;
|
562 | e1bb04f7 | bellard | } |
563 | e1bb04f7 | bellard | |
564 | c227f099 | Anthony Liguori | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
565 | e1bb04f7 | bellard | { |
566 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
567 | 819385c5 | bellard | uint32_t retval; |
568 | 3b46e624 | ths | |
569 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 8;
|
570 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1);
|
571 | e1bb04f7 | bellard | return retval;
|
572 | e1bb04f7 | bellard | } |
573 | e1bb04f7 | bellard | |
574 | c227f099 | Anthony Liguori | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
575 | e1bb04f7 | bellard | { |
576 | c227f099 | Anthony Liguori | m48t59_t *NVRAM = opaque; |
577 | 819385c5 | bellard | uint32_t retval; |
578 | e1bb04f7 | bellard | |
579 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 24;
|
580 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1) << 16; |
581 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 2) << 8; |
582 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 3);
|
583 | e1bb04f7 | bellard | return retval;
|
584 | e1bb04f7 | bellard | } |
585 | e1bb04f7 | bellard | |
586 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const nvram_write[] = { |
587 | e1bb04f7 | bellard | &nvram_writeb, |
588 | e1bb04f7 | bellard | &nvram_writew, |
589 | e1bb04f7 | bellard | &nvram_writel, |
590 | e1bb04f7 | bellard | }; |
591 | e1bb04f7 | bellard | |
592 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const nvram_read[] = { |
593 | e1bb04f7 | bellard | &nvram_readb, |
594 | e1bb04f7 | bellard | &nvram_readw, |
595 | e1bb04f7 | bellard | &nvram_readl, |
596 | e1bb04f7 | bellard | }; |
597 | 819385c5 | bellard | |
598 | 3ccacc4a | blueswir1 | static void m48t59_save(QEMUFile *f, void *opaque) |
599 | 3ccacc4a | blueswir1 | { |
600 | c227f099 | Anthony Liguori | m48t59_t *s = opaque; |
601 | 3ccacc4a | blueswir1 | |
602 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->lock); |
603 | 3ccacc4a | blueswir1 | qemu_put_be16s(f, &s->addr); |
604 | 3ccacc4a | blueswir1 | qemu_put_buffer(f, s->buffer, s->size); |
605 | 3ccacc4a | blueswir1 | } |
606 | 3ccacc4a | blueswir1 | |
607 | 3ccacc4a | blueswir1 | static int m48t59_load(QEMUFile *f, void *opaque, int version_id) |
608 | 3ccacc4a | blueswir1 | { |
609 | c227f099 | Anthony Liguori | m48t59_t *s = opaque; |
610 | 3ccacc4a | blueswir1 | |
611 | 3ccacc4a | blueswir1 | if (version_id != 1) |
612 | 3ccacc4a | blueswir1 | return -EINVAL;
|
613 | 3ccacc4a | blueswir1 | |
614 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->lock); |
615 | 3ccacc4a | blueswir1 | qemu_get_be16s(f, &s->addr); |
616 | 3ccacc4a | blueswir1 | qemu_get_buffer(f, s->buffer, s->size); |
617 | 3ccacc4a | blueswir1 | |
618 | 3ccacc4a | blueswir1 | return 0; |
619 | 3ccacc4a | blueswir1 | } |
620 | 3ccacc4a | blueswir1 | |
621 | 285e468d | Blue Swirl | static void m48t59_reset_common(m48t59_t *NVRAM) |
622 | 3ccacc4a | blueswir1 | { |
623 | 6e6b7363 | blueswir1 | NVRAM->addr = 0;
|
624 | 6e6b7363 | blueswir1 | NVRAM->lock = 0;
|
625 | 3ccacc4a | blueswir1 | if (NVRAM->alrm_timer != NULL) |
626 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->alrm_timer); |
627 | 3ccacc4a | blueswir1 | |
628 | 3ccacc4a | blueswir1 | if (NVRAM->wd_timer != NULL) |
629 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->wd_timer); |
630 | 3ccacc4a | blueswir1 | } |
631 | 3ccacc4a | blueswir1 | |
632 | 285e468d | Blue Swirl | static void m48t59_reset_isa(DeviceState *d) |
633 | 285e468d | Blue Swirl | { |
634 | 285e468d | Blue Swirl | M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev); |
635 | 285e468d | Blue Swirl | m48t59_t *NVRAM = &isa->state; |
636 | 285e468d | Blue Swirl | |
637 | 285e468d | Blue Swirl | m48t59_reset_common(NVRAM); |
638 | 285e468d | Blue Swirl | } |
639 | 285e468d | Blue Swirl | |
640 | 285e468d | Blue Swirl | static void m48t59_reset_sysbus(DeviceState *d) |
641 | 285e468d | Blue Swirl | { |
642 | 285e468d | Blue Swirl | M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); |
643 | 285e468d | Blue Swirl | m48t59_t *NVRAM = &sys->state; |
644 | 285e468d | Blue Swirl | |
645 | 285e468d | Blue Swirl | m48t59_reset_common(NVRAM); |
646 | 285e468d | Blue Swirl | } |
647 | 285e468d | Blue Swirl | |
648 | a541f297 | bellard | /* Initialisation routine */
|
649 | c227f099 | Anthony Liguori | m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, |
650 | 819385c5 | bellard | uint32_t io_base, uint16_t size, |
651 | 819385c5 | bellard | int type)
|
652 | a541f297 | bellard | { |
653 | d27cf0ae | Blue Swirl | DeviceState *dev; |
654 | d27cf0ae | Blue Swirl | SysBusDevice *s; |
655 | f80237d4 | Blue Swirl | M48t59SysBusState *d; |
656 | d27cf0ae | Blue Swirl | |
657 | d27cf0ae | Blue Swirl | dev = qdev_create(NULL, "m48t59"); |
658 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "type", type);
|
659 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "size", size);
|
660 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "io_base", io_base);
|
661 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
662 | d27cf0ae | Blue Swirl | s = sysbus_from_qdev(dev); |
663 | d27cf0ae | Blue Swirl | sysbus_connect_irq(s, 0, IRQ);
|
664 | 819385c5 | bellard | if (io_base != 0) { |
665 | 819385c5 | bellard | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
666 | 819385c5 | bellard | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
667 | 819385c5 | bellard | } |
668 | e1bb04f7 | bellard | if (mem_base != 0) { |
669 | d27cf0ae | Blue Swirl | sysbus_mmio_map(s, 0, mem_base);
|
670 | e1bb04f7 | bellard | } |
671 | d27cf0ae | Blue Swirl | |
672 | f80237d4 | Blue Swirl | d = FROM_SYSBUS(M48t59SysBusState, s); |
673 | d27cf0ae | Blue Swirl | |
674 | f80237d4 | Blue Swirl | return &d->state;
|
675 | d27cf0ae | Blue Swirl | } |
676 | d27cf0ae | Blue Swirl | |
677 | c227f099 | Anthony Liguori | m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
|
678 | d27cf0ae | Blue Swirl | { |
679 | f80237d4 | Blue Swirl | M48t59ISAState *d; |
680 | f80237d4 | Blue Swirl | ISADevice *dev; |
681 | c227f099 | Anthony Liguori | m48t59_t *s; |
682 | f80237d4 | Blue Swirl | |
683 | f80237d4 | Blue Swirl | dev = isa_create("m48t59_isa");
|
684 | f80237d4 | Blue Swirl | qdev_prop_set_uint32(&dev->qdev, "type", type);
|
685 | f80237d4 | Blue Swirl | qdev_prop_set_uint32(&dev->qdev, "size", size);
|
686 | f80237d4 | Blue Swirl | qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
|
687 | e23a1b33 | Markus Armbruster | qdev_init_nofail(&dev->qdev); |
688 | f80237d4 | Blue Swirl | d = DO_UPCAST(M48t59ISAState, busdev, dev); |
689 | f80237d4 | Blue Swirl | s = &d->state; |
690 | d27cf0ae | Blue Swirl | |
691 | f80237d4 | Blue Swirl | if (io_base != 0) { |
692 | f80237d4 | Blue Swirl | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
693 | f80237d4 | Blue Swirl | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
694 | f80237d4 | Blue Swirl | } |
695 | d27cf0ae | Blue Swirl | |
696 | f80237d4 | Blue Swirl | return s;
|
697 | f80237d4 | Blue Swirl | } |
698 | d27cf0ae | Blue Swirl | |
699 | c227f099 | Anthony Liguori | static void m48t59_init_common(m48t59_t *s) |
700 | f80237d4 | Blue Swirl | { |
701 | f80237d4 | Blue Swirl | s->buffer = qemu_mallocz(s->size); |
702 | d27cf0ae | Blue Swirl | if (s->type == 59) { |
703 | 819385c5 | bellard | s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
704 | 819385c5 | bellard | s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
705 | 819385c5 | bellard | } |
706 | f6503059 | balrog | qemu_get_timedate(&s->alarm, 0);
|
707 | 13ab5daa | bellard | |
708 | d27cf0ae | Blue Swirl | register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s); |
709 | f80237d4 | Blue Swirl | } |
710 | f80237d4 | Blue Swirl | |
711 | f80237d4 | Blue Swirl | static int m48t59_init_isa1(ISADevice *dev) |
712 | f80237d4 | Blue Swirl | { |
713 | f80237d4 | Blue Swirl | M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); |
714 | c227f099 | Anthony Liguori | m48t59_t *s = &d->state; |
715 | f80237d4 | Blue Swirl | |
716 | f80237d4 | Blue Swirl | isa_init_irq(dev, &s->IRQ, 8);
|
717 | f80237d4 | Blue Swirl | m48t59_init_common(s); |
718 | f80237d4 | Blue Swirl | |
719 | 81a322d4 | Gerd Hoffmann | return 0; |
720 | d27cf0ae | Blue Swirl | } |
721 | 3ccacc4a | blueswir1 | |
722 | f80237d4 | Blue Swirl | static int m48t59_init1(SysBusDevice *dev) |
723 | f80237d4 | Blue Swirl | { |
724 | f80237d4 | Blue Swirl | M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); |
725 | c227f099 | Anthony Liguori | m48t59_t *s = &d->state; |
726 | f80237d4 | Blue Swirl | int mem_index;
|
727 | f80237d4 | Blue Swirl | |
728 | f80237d4 | Blue Swirl | sysbus_init_irq(dev, &s->IRQ); |
729 | f80237d4 | Blue Swirl | |
730 | f80237d4 | Blue Swirl | mem_index = cpu_register_io_memory(nvram_read, nvram_write, s); |
731 | f80237d4 | Blue Swirl | sysbus_init_mmio(dev, s->size, mem_index); |
732 | f80237d4 | Blue Swirl | m48t59_init_common(s); |
733 | f80237d4 | Blue Swirl | |
734 | f80237d4 | Blue Swirl | return 0; |
735 | f80237d4 | Blue Swirl | } |
736 | f80237d4 | Blue Swirl | |
737 | f80237d4 | Blue Swirl | static ISADeviceInfo m48t59_isa_info = {
|
738 | f80237d4 | Blue Swirl | .init = m48t59_init_isa1, |
739 | f80237d4 | Blue Swirl | .qdev.name = "m48t59_isa",
|
740 | f80237d4 | Blue Swirl | .qdev.size = sizeof(M48t59ISAState),
|
741 | 285e468d | Blue Swirl | .qdev.reset = m48t59_reset_isa, |
742 | f80237d4 | Blue Swirl | .qdev.no_user = 1,
|
743 | f80237d4 | Blue Swirl | .qdev.props = (Property[]) { |
744 | f80237d4 | Blue Swirl | DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), |
745 | f80237d4 | Blue Swirl | DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1), |
746 | f80237d4 | Blue Swirl | DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
747 | f80237d4 | Blue Swirl | DEFINE_PROP_END_OF_LIST(), |
748 | f80237d4 | Blue Swirl | } |
749 | f80237d4 | Blue Swirl | }; |
750 | f80237d4 | Blue Swirl | |
751 | ee6847d1 | Gerd Hoffmann | static SysBusDeviceInfo m48t59_info = {
|
752 | ee6847d1 | Gerd Hoffmann | .init = m48t59_init1, |
753 | ee6847d1 | Gerd Hoffmann | .qdev.name = "m48t59",
|
754 | f80237d4 | Blue Swirl | .qdev.size = sizeof(M48t59SysBusState),
|
755 | 285e468d | Blue Swirl | .qdev.reset = m48t59_reset_sysbus, |
756 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
757 | f80237d4 | Blue Swirl | DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
758 | f80237d4 | Blue Swirl | DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1), |
759 | f80237d4 | Blue Swirl | DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
760 | 01274424 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
761 | ee6847d1 | Gerd Hoffmann | } |
762 | ee6847d1 | Gerd Hoffmann | }; |
763 | ee6847d1 | Gerd Hoffmann | |
764 | d27cf0ae | Blue Swirl | static void m48t59_register_devices(void) |
765 | d27cf0ae | Blue Swirl | { |
766 | ee6847d1 | Gerd Hoffmann | sysbus_register_withprop(&m48t59_info); |
767 | f80237d4 | Blue Swirl | isa_qdev_register(&m48t59_isa_info); |
768 | a541f297 | bellard | } |
769 | d27cf0ae | Blue Swirl | |
770 | d27cf0ae | Blue Swirl | device_init(m48t59_register_devices) |