Archipelago » qemu

/*

 * PowerPC implementation of KVM hooks

 *

 * Copyright IBM Corp. 2007

 * Copyright (C) 2011 Freescale Semiconductor, Inc.

 *

 * Authors:

 *  Jerone Young <jyoung5@us.ibm.com>

 *  Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>

 *  Hollis Blanchard <hollisb@us.ibm.com>

 *

 * This work is licensed under the terms of the GNU GPL, version 2 or later.

 * See the COPYING file in the top-level directory.

 *

 */

#include <dirent.h>

#include <sys/types.h>

#include <sys/ioctl.h>

#include <sys/mman.h>

#include <sys/vfs.h>

#include <linux/kvm.h>

#include "qemu-common.h"

#include "qemu/timer.h"

#include "sysemu/sysemu.h"

#include "sysemu/kvm.h"

#include "kvm_ppc.h"

#include "cpu.h"

#include "sysemu/cpus.h"

#include "sysemu/device_tree.h"

#include "hw/sysbus.h"

#include "hw/spapr.h"

#include "hw/sysbus.h"

#include "hw/spapr.h"

#include "hw/spapr_vio.h"

//#define DEBUG_KVM

#ifdef DEBUG_KVM

#define dprintf(fmt, ...) \

    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)

#else

#define dprintf(fmt, ...) \

    do { } while (0)

#endif

#define PROC_DEVTREE_CPU      "/proc/device-tree/cpus/"

const KVMCapabilityInfo kvm_arch_required_capabilities[] = {

    KVM_CAP_LAST_INFO

};

static int cap_interrupt_unset = false;

static int cap_interrupt_level = false;

static int cap_segstate;

static int cap_booke_sregs;

static int cap_ppc_smt;

static int cap_ppc_rma;

static int cap_spapr_tce;

static int cap_hior;

/* XXX We have a race condition where we actually have a level triggered

 *     interrupt, but the infrastructure can't expose that yet, so the guest

 *     takes but ignores it, goes to sleep and never gets notified that there's

 *     still an interrupt pending.

 *

 *     As a quick workaround, let's just wake up again 20 ms after we injected

 *     an interrupt. That way we can assure that we're always reinjecting

 *     interrupts in case the guest swallowed them.

 */

static QEMUTimer *idle_timer;

static void kvm_kick_cpu(void *opaque)

{

    PowerPCCPU *cpu = opaque;

    qemu_cpu_kick(CPU(cpu));

}

int kvm_arch_init(KVMState *s)

{

    cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);

    cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);

    cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);

    cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);

    cap_ppc_smt = kvm_check_extension(s, KVM_CAP_PPC_SMT);

    cap_ppc_rma = kvm_check_extension(s, KVM_CAP_PPC_RMA);

    cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);

    cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);

    if (!cap_interrupt_level) {

        fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "

                        "VM to stall at times!\n");

    }

    return 0;

}

static int kvm_arch_sync_sregs(PowerPCCPU *cpu)

{

    CPUPPCState *cenv = &cpu->env;

    CPUState *cs = CPU(cpu);

    struct kvm_sregs sregs;

    int ret;

    if (cenv->excp_model == POWERPC_EXCP_BOOKE) {

        /* What we're really trying to say is "if we're on BookE, we use

           the native PVR for now". This is the only sane way to check

           it though, so we potentially confuse users that they can run

           BookE guests on BookS. Let's hope nobody dares enough :) */

        return 0;

    } else {

        if (!cap_segstate) {

            fprintf(stderr, "kvm error: missing PVR setting capability\n");

            return -ENOSYS;

        }

    }

    ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);

    if (ret) {

        return ret;

    }

    sregs.pvr = cenv->spr[SPR_PVR];

    return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);

}

/* Set up a shared TLB array with KVM */

static int kvm_booke206_tlb_init(PowerPCCPU *cpu)

{

    CPUPPCState *env = &cpu->env;

    CPUState *cs = CPU(cpu);

    struct kvm_book3e_206_tlb_params params = {};

    struct kvm_config_tlb cfg = {};

    struct kvm_enable_cap encap = {};

    unsigned int entries = 0;

    int ret, i;

    if (!kvm_enabled() ||

        !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {

        return 0;

    }

    assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);

    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {

        params.tlb_sizes[i] = booke206_tlb_size(env, i);

        params.tlb_ways[i] = booke206_tlb_ways(env, i);

        entries += params.tlb_sizes[i];

    }

    assert(entries == env->nb_tlb);

    assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));

    env->tlb_dirty = true;

    cfg.array = (uintptr_t)env->tlb.tlbm;

    cfg.array_len = sizeof(ppcmas_tlb_t) * entries;

    cfg.params = (uintptr_t)&params;

    cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;

    encap.cap = KVM_CAP_SW_TLB;

    encap.args[0] = (uintptr_t)&cfg;

    ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap);

    if (ret < 0) {

        fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",

                __func__, strerror(-ret));

        return ret;

    }

    env->kvm_sw_tlb = true;

    return 0;

}

#if defined(TARGET_PPC64)

static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,

                                       struct kvm_ppc_smmu_info *info)

{

    CPUPPCState *env = &cpu->env;

    CPUState *cs = CPU(cpu);

    memset(info, 0, sizeof(*info));

    /* We don't have the new KVM_PPC_GET_SMMU_INFO ioctl, so

     * need to "guess" what the supported page sizes are.

     *

     * For that to work we make a few assumptions:

     *

     * - If KVM_CAP_PPC_GET_PVINFO is supported we are running "PR"

     *   KVM which only supports 4K and 16M pages, but supports them

     *   regardless of the backing store characteritics. We also don't

     *   support 1T segments.

     *

     *   This is safe as if HV KVM ever supports that capability or PR

     *   KVM grows supports for more page/segment sizes, those versions

     *   will have implemented KVM_CAP_PPC_GET_SMMU_INFO and thus we

     *   will not hit this fallback

     *

     * - Else we are running HV KVM. This means we only support page

     *   sizes that fit in the backing store. Additionally we only

     *   advertize 64K pages if the processor is ARCH 2.06 and we assume

     *   P7 encodings for the SLB and hash table. Here too, we assume

     *   support for any newer processor will mean a kernel that

     *   implements KVM_CAP_PPC_GET_SMMU_INFO and thus doesn't hit

     *   this fallback.

     */

    if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO)) {

        /* No flags */

        info->flags = 0;

        info->slb_size = 64;

        /* Standard 4k base page size segment */

        info->sps[0].page_shift = 12;

        info->sps[0].slb_enc = 0;

        info->sps[0].enc[0].page_shift = 12;

        info->sps[0].enc[0].pte_enc = 0;

        /* Standard 16M large page size segment */

        info->sps[1].page_shift = 24;

        info->sps[1].slb_enc = SLB_VSID_L;

        info->sps[1].enc[0].page_shift = 24;

        info->sps[1].enc[0].pte_enc = 0;

    } else {

        int i = 0;

        /* HV KVM has backing store size restrictions */

        info->flags = KVM_PPC_PAGE_SIZES_REAL;

        if (env->mmu_model & POWERPC_MMU_1TSEG) {

            info->flags |= KVM_PPC_1T_SEGMENTS;

        }

        if (env->mmu_model == POWERPC_MMU_2_06) {

            info->slb_size = 32;

        } else {

            info->slb_size = 64;

        }

        /* Standard 4k base page size segment */

        info->sps[i].page_shift = 12;

        info->sps[i].slb_enc = 0;

        info->sps[i].enc[0].page_shift = 12;

        info->sps[i].enc[0].pte_enc = 0;

        i++;

        /* 64K on MMU 2.06 */

        if (env->mmu_model == POWERPC_MMU_2_06) {

            info->sps[i].page_shift = 16;

            info->sps[i].slb_enc = 0x110;

            info->sps[i].enc[0].page_shift = 16;

            info->sps[i].enc[0].pte_enc = 1;

            i++;

        }

        /* Standard 16M large page size segment */

        info->sps[i].page_shift = 24;

        info->sps[i].slb_enc = SLB_VSID_L;

        info->sps[i].enc[0].page_shift = 24;

        info->sps[i].enc[0].pte_enc = 0;

    }

}

static void kvm_get_smmu_info(PowerPCCPU *cpu, struct kvm_ppc_smmu_info *info)

{

    CPUState *cs = CPU(cpu);

    int ret;

    if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {

        ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_SMMU_INFO, info);

        if (ret == 0) {

            return;

        }

    }

    kvm_get_fallback_smmu_info(cpu, info);

}

static long getrampagesize(void)

{

    struct statfs fs;

    int ret;

    if (!mem_path) {

        /* guest RAM is backed by normal anonymous pages */

        return getpagesize();

    }

    do {

        ret = statfs(mem_path, &fs);

    } while (ret != 0 && errno == EINTR);

    if (ret != 0) {

        fprintf(stderr, "Couldn't statfs() memory path: %s\n",

                strerror(errno));

        exit(1);

    }

#define HUGETLBFS_MAGIC       0x958458f6

    if (fs.f_type != HUGETLBFS_MAGIC) {

        /* Explicit mempath, but it's ordinary pages */

        return getpagesize();

    }

    /* It's hugepage, return the huge page size */

    return fs.f_bsize;

}

static bool kvm_valid_page_size(uint32_t flags, long rampgsize, uint32_t shift)

{

    if (!(flags & KVM_PPC_PAGE_SIZES_REAL)) {

        return true;

    }

    return (1ul << shift) <= rampgsize;

}

static void kvm_fixup_page_sizes(PowerPCCPU *cpu)

{

    static struct kvm_ppc_smmu_info smmu_info;

    static bool has_smmu_info;

    CPUPPCState *env = &cpu->env;

    long rampagesize;

    int iq, ik, jq, jk;

    /* We only handle page sizes for 64-bit server guests for now */

    if (!(env->mmu_model & POWERPC_MMU_64)) {

        return;

    }

    /* Collect MMU info from kernel if not already */

    if (!has_smmu_info) {

        kvm_get_smmu_info(cpu, &smmu_info);

        has_smmu_info = true;

    }

    rampagesize = getrampagesize();

    /* Convert to QEMU form */

    memset(&env->sps, 0, sizeof(env->sps));

    for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) {

        struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];

        struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];

        if (!kvm_valid_page_size(smmu_info.flags, rampagesize,

                                 ksps->page_shift)) {

            continue;

        }

        qsps->page_shift = ksps->page_shift;

        qsps->slb_enc = ksps->slb_enc;

        for (jk = jq = 0; jk < KVM_PPC_PAGE_SIZES_MAX_SZ; jk++) {

            if (!kvm_valid_page_size(smmu_info.flags, rampagesize,

                                     ksps->enc[jk].page_shift)) {

                continue;

            }

            qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;

            qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;

            if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {

                break;

            }

        }

        if (++iq >= PPC_PAGE_SIZES_MAX_SZ) {

            break;

        }

    }

    env->slb_nr = smmu_info.slb_size;

    if (smmu_info.flags & KVM_PPC_1T_SEGMENTS) {

        env->mmu_model |= POWERPC_MMU_1TSEG;

    } else {

        env->mmu_model &= ~POWERPC_MMU_1TSEG;

    }

}

#else /* defined (TARGET_PPC64) */

static inline void kvm_fixup_page_sizes(PowerPCCPU *cpu)

{

}

#endif /* !defined (TARGET_PPC64) */

unsigned long kvm_arch_vcpu_id(CPUState *cpu)

{

    return cpu->cpu_index;

}

int kvm_arch_init_vcpu(CPUState *cs)

{

    PowerPCCPU *cpu = POWERPC_CPU(cs);

    CPUPPCState *cenv = &cpu->env;

    int ret;

    /* Gather server mmu info from KVM and update the CPU state */

    kvm_fixup_page_sizes(cpu);

    /* Synchronize sregs with kvm */

    ret = kvm_arch_sync_sregs(cpu);

    if (ret) {

        return ret;

    }

    idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_cpu, cpu);

    /* Some targets support access to KVM's guest TLB. */

    switch (cenv->mmu_model) {

    case POWERPC_MMU_BOOKE206:

        ret = kvm_booke206_tlb_init(cpu);

        break;

    default:

        break;

    }

    return ret;

}

void kvm_arch_reset_vcpu(CPUState *cpu)

{

}

static void kvm_sw_tlb_put(PowerPCCPU *cpu)

{

    CPUPPCState *env = &cpu->env;

    CPUState *cs = CPU(cpu);

    struct kvm_dirty_tlb dirty_tlb;

    unsigned char *bitmap;

    int ret;

    if (!env->kvm_sw_tlb) {

        return;

    }

    bitmap = g_malloc((env->nb_tlb + 7) / 8);

    memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);

    dirty_tlb.bitmap = (uintptr_t)bitmap;

    dirty_tlb.num_dirty = env->nb_tlb;

    ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);

    if (ret) {

        fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",

                __func__, strerror(-ret));

    }

    g_free(bitmap);

}

int kvm_arch_put_registers(CPUState *cs, int level)

{

    PowerPCCPU *cpu = POWERPC_CPU(cs);

    CPUPPCState *env = &cpu->env;

    struct kvm_regs regs;

    int ret;

    int i;

    ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);

    if (ret < 0) {

        return ret;

    }

    regs.ctr = env->ctr;

    regs.lr  = env->lr;

    regs.xer = env->xer;

    regs.msr = env->msr;

    regs.pc = env->nip;

    regs.srr0 = env->spr[SPR_SRR0];

    regs.srr1 = env->spr[SPR_SRR1];

    regs.sprg0 = env->spr[SPR_SPRG0];

    regs.sprg1 = env->spr[SPR_SPRG1];

    regs.sprg2 = env->spr[SPR_SPRG2];

    regs.sprg3 = env->spr[SPR_SPRG3];

    regs.sprg4 = env->spr[SPR_SPRG4];

    regs.sprg5 = env->spr[SPR_SPRG5];

    regs.sprg6 = env->spr[SPR_SPRG6];

    regs.sprg7 = env->spr[SPR_SPRG7];

    regs.pid = env->spr[SPR_BOOKE_PID];

    for (i = 0;i < 32; i++)

        regs.gpr[i] = env->gpr[i];

    ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);

    if (ret < 0)

        return ret;

    if (env->tlb_dirty) {

        kvm_sw_tlb_put(cpu);

        env->tlb_dirty = false;

    }

    if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {

        struct kvm_sregs sregs;

        sregs.pvr = env->spr[SPR_PVR];

        sregs.u.s.sdr1 = env->spr[SPR_SDR1];

        /* Sync SLB */

#ifdef TARGET_PPC64

        for (i = 0; i < 64; i++) {

            sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;

            sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;

        }

#endif

        /* Sync SRs */

        for (i = 0; i < 16; i++) {

            sregs.u.s.ppc32.sr[i] = env->sr[i];

        }

        /* Sync BATs */

        for (i = 0; i < 8; i++) {

            /* Beware. We have to swap upper and lower bits here */

            sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)

                | env->DBAT[1][i];

            sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)

                | env->IBAT[1][i];

        }

        ret = kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);

        if (ret) {

            return ret;

        }

    }

    if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {

        uint64_t hior = env->spr[SPR_HIOR];

        struct kvm_one_reg reg = {

            .id = KVM_REG_PPC_HIOR,

            .addr = (uintptr_t) &hior,

        };

        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

        if (ret) {

            return ret;

        }

    }

    return ret;

}

int kvm_arch_get_registers(CPUState *cs)

{

    PowerPCCPU *cpu = POWERPC_CPU(cs);

    CPUPPCState *env = &cpu->env;

    struct kvm_regs regs;

    struct kvm_sregs sregs;

    uint32_t cr;

    int i, ret;

    ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);

    if (ret < 0)

        return ret;

    cr = regs.cr;

    for (i = 7; i >= 0; i--) {

        env->crf[i] = cr & 15;

        cr >>= 4;

    }

    env->ctr = regs.ctr;

    env->lr = regs.lr;

    env->xer = regs.xer;

    env->msr = regs.msr;

    env->nip = regs.pc;

    env->spr[SPR_SRR0] = regs.srr0;

    env->spr[SPR_SRR1] = regs.srr1;

    env->spr[SPR_SPRG0] = regs.sprg0;

    env->spr[SPR_SPRG1] = regs.sprg1;

    env->spr[SPR_SPRG2] = regs.sprg2;

    env->spr[SPR_SPRG3] = regs.sprg3;

    env->spr[SPR_SPRG4] = regs.sprg4;

    env->spr[SPR_SPRG5] = regs.sprg5;

    env->spr[SPR_SPRG6] = regs.sprg6;

    env->spr[SPR_SPRG7] = regs.sprg7;

    env->spr[SPR_BOOKE_PID] = regs.pid;

    for (i = 0;i < 32; i++)

        env->gpr[i] = regs.gpr[i];

    if (cap_booke_sregs) {

        ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);

        if (ret < 0) {

            return ret;

        }

        if (sregs.u.e.features & KVM_SREGS_E_BASE) {

            env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;

            env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;

            env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;

            env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;

            env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;

            env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;

            env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;

            env->spr[SPR_DECR] = sregs.u.e.dec;

            env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;

            env->spr[SPR_TBU] = sregs.u.e.tb >> 32;

            env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;

        }

        if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {

            env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;

            env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;

            env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;

            env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;

            env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;

        }

        if (sregs.u.e.features & KVM_SREGS_E_64) {

            env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;

        }

        if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {

            env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;

        }

        if (sregs.u.e.features & KVM_SREGS_E_IVOR) {

            env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];

            env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];

            env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];

            env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];

            env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];

            env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];

            env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];

            env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];

            env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];

            env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];

            env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];

            env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];

            env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];

            env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];

            env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];

            env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];

            if (sregs.u.e.features & KVM_SREGS_E_SPE) {

                env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];

                env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];

                env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];

            }

            if (sregs.u.e.features & KVM_SREGS_E_PM) {

                env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];

            }

            if (sregs.u.e.features & KVM_SREGS_E_PC) {

                env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];

                env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];

            }

        }

        if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {

            env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;

            env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;

            env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;

            env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;

            env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;

            env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;

            env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;

            env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;

            env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];

            env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];

        }

        if (sregs.u.e.features & KVM_SREGS_EXP) {

            env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;

        }

        if (sregs.u.e.features & KVM_SREGS_E_PD) {

            env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;

            env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;

        }

        if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {

            env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;

            env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;

            env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;

            if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {

                env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;

                env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;

            }

        }

    }

    if (cap_segstate) {

        ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);

        if (ret < 0) {

            return ret;

        }

        ppc_store_sdr1(env, sregs.u.s.sdr1);

        /* Sync SLB */

#ifdef TARGET_PPC64

        for (i = 0; i < 64; i++) {

            ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,

                               sregs.u.s.ppc64.slb[i].slbv);

        }

#endif

        /* Sync SRs */

        for (i = 0; i < 16; i++) {

            env->sr[i] = sregs.u.s.ppc32.sr[i];

        }

        /* Sync BATs */

        for (i = 0; i < 8; i++) {

            env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;

            env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;

            env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;

            env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;

        }

    }

    return 0;

}

int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)

{

    unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;

    if (irq != PPC_INTERRUPT_EXT) {

        return 0;

    }

    if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {

        return 0;

    }

    kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);

    return 0;

}

#if defined(TARGET_PPCEMB)

#define PPC_INPUT_INT PPC40x_INPUT_INT

#elif defined(TARGET_PPC64)

#define PPC_INPUT_INT PPC970_INPUT_INT

#else

#define PPC_INPUT_INT PPC6xx_INPUT_INT

#endif

void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)

{

    PowerPCCPU *cpu = POWERPC_CPU(cs);

    CPUPPCState *env = &cpu->env;

    int r;

    unsigned irq;

    /* PowerPC QEMU tracks the various core input pins (interrupt, critical

     * interrupt, reset, etc) in PPC-specific env->irq_input_state. */

    if (!cap_interrupt_level &&

        run->ready_for_interrupt_injection &&

        (env->interrupt_request & CPU_INTERRUPT_HARD) &&

        (env->irq_input_state & (1<<PPC_INPUT_INT)))

    {

        /* For now KVM disregards the 'irq' argument. However, in the

         * future KVM could cache it in-kernel to avoid a heavyweight exit

         * when reading the UIC.

         */

        irq = KVM_INTERRUPT_SET;

        dprintf("injected interrupt %d\n", irq);

        r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq);

        if (r < 0) {

            printf("cpu %d fail inject %x\n", cs->cpu_index, irq);

        }

        /* Always wake up soon in case the interrupt was level based */

        qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) +

                       (get_ticks_per_sec() / 50));

    }

    /* We don't know if there are more interrupts pending after this. However,

     * the guest will return to userspace in the course of handling this one

     * anyways, so we will get a chance to deliver the rest. */

}

void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)

{

}

int kvm_arch_process_async_events(CPUState *cs)

{

    PowerPCCPU *cpu = POWERPC_CPU(cs);

    return cpu->env.halted;

}

static int kvmppc_handle_halt(CPUPPCState *env)

{

    if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {

        env->halted = 1;

        env->exception_index = EXCP_HLT;

    }

    return 0;

}

/* map dcr access to existing qemu dcr emulation */

static int kvmppc_handle_dcr_read(CPUPPCState *env, uint32_t dcrn, uint32_t *data)

{

    if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0)

        fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);

    return 0;

}

static int kvmppc_handle_dcr_write(CPUPPCState *env, uint32_t dcrn, uint32_t data)

{

    if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0)

        fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);

    return 0;

}

int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)

{

    PowerPCCPU *cpu = POWERPC_CPU(cs);

    CPUPPCState *env = &cpu->env;

    int ret;

    switch (run->exit_reason) {

    case KVM_EXIT_DCR:

        if (run->dcr.is_write) {

            dprintf("handle dcr write\n");

            ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);

        } else {

            dprintf("handle dcr read\n");

            ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);

        }

        break;

    case KVM_EXIT_HLT:

        dprintf("handle halt\n");

        ret = kvmppc_handle_halt(env);

        break;

#ifdef CONFIG_PSERIES

    case KVM_EXIT_PAPR_HCALL:

        dprintf("handle PAPR hypercall\n");

        run->papr_hcall.ret = spapr_hypercall(cpu,

                                              run->papr_hcall.nr,

                                              run->papr_hcall.args);

        ret = 0;

        break;

#endif

    case KVM_EXIT_EPR:

        dprintf("handle epr\n");

        run->epr.epr = ldl_phys(env->mpic_iack);

        ret = 0;

        break;

    default:

        fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);

        ret = -1;

        break;

    }

    return ret;

}

static int read_cpuinfo(const char *field, char *value, int len)

{

    FILE *f;

    int ret = -1;

    int field_len = strlen(field);

    char line[512];

    f = fopen("/proc/cpuinfo", "r");

    if (!f) {

        return -1;

    }

    do {

        if(!fgets(line, sizeof(line), f)) {

            break;

        }

        if (!strncmp(line, field, field_len)) {

            pstrcpy(value, len, line);

            ret = 0;

            break;

        }

    } while(*line);

    fclose(f);

    return ret;

}

uint32_t kvmppc_get_tbfreq(void)

{

    char line[512];

    char *ns;

    uint32_t retval = get_ticks_per_sec();

    if (read_cpuinfo("timebase", line, sizeof(line))) {

        return retval;

    }

    if (!(ns = strchr(line, ':'))) {