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/*
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* QEMU Malta board support
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*
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* Copyright (c) 2006 Aurelien Jarno
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#ifdef TARGET_WORDS_BIGENDIAN
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#define BIOS_FILENAME "mips_bios.bin" |
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#else
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#define BIOS_FILENAME "mipsel_bios.bin" |
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#endif
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#ifdef TARGET_MIPS64
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#define INITRD_LOAD_ADDR (int64_t)0x80800000 |
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#else
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#define INITRD_LOAD_ADDR (int32_t)0x80800000 |
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#endif
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#define ENVP_ADDR (int32_t)0x80002000 |
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#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
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#define ENVP_NB_ENTRIES 16 |
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#define ENVP_ENTRY_SIZE 256 |
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extern FILE *logfile;
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typedef struct { |
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uint32_t leds; |
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uint32_t brk; |
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uint32_t gpout; |
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uint32_t i2cin; |
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uint32_t i2coe; |
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uint32_t i2cout; |
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uint32_t i2csel; |
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CharDriverState *display; |
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char display_text[9]; |
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SerialState *uart; |
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} MaltaFPGAState; |
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static PITState *pit;
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/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
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static void pic_irq_request(void *opaque, int level) |
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{ |
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cpu_mips_irq_request(opaque, 2, level);
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} |
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/* Malta FPGA */
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static void malta_fpga_update_display(void *opaque) |
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{ |
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char leds_text[9]; |
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int i;
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MaltaFPGAState *s = opaque; |
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for (i = 7 ; i >= 0 ; i--) { |
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if (s->leds & (1 << i)) |
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leds_text[i] = '#';
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else
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leds_text[i] = ' ';
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} |
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leds_text[8] = '\0'; |
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qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text); |
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qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text); |
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} |
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/*
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* EEPROM 24C01 / 24C02 emulation.
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*
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* Emulation for serial EEPROMs:
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* 24C01 - 1024 bit (128 x 8)
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* 24C02 - 2048 bit (256 x 8)
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*
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* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
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*/
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//~ #define DEBUG
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#if defined(DEBUG)
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# define logout(fmt, args...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ##args) |
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#else
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# define logout(fmt, args...) ((void)0) |
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#endif
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struct _eeprom24c0x_t {
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uint8_t tick; |
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uint8_t address; |
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uint8_t command; |
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uint8_t ack; |
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uint8_t scl; |
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uint8_t sda; |
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uint8_t data; |
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//~ uint16_t size;
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uint8_t contents[256];
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}; |
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typedef struct _eeprom24c0x_t eeprom24c0x_t; |
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static eeprom24c0x_t eeprom = {
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contents: {
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/* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00, |
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/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01, |
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/* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00, |
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/* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40, |
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/* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00, |
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/* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
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/* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
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/* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0, |
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/* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
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/* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
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/* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
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/* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
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/* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
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/* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
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/* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
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/* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4, |
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}, |
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}; |
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static uint8_t eeprom24c0x_read()
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{ |
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logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
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eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data); |
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return eeprom.sda;
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} |
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static void eeprom24c0x_write(int scl, int sda) |
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{ |
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if (eeprom.scl && scl && (eeprom.sda != sda)) {
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logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
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eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start"); |
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if (!sda) {
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eeprom.tick = 1;
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eeprom.command = 0;
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} |
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} else if (eeprom.tick == 0 && !eeprom.ack) { |
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/* Waiting for start. */
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logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
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eeprom.tick, eeprom.scl, scl, eeprom.sda, sda); |
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} else if (!eeprom.scl && scl) { |
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logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
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eeprom.tick, eeprom.scl, scl, eeprom.sda, sda); |
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if (eeprom.ack) {
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logout("\ti2c ack bit = 0\n");
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sda = 0;
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eeprom.ack = 0;
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} else if (eeprom.sda == sda) { |
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uint8_t bit = (sda != 0);
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logout("\ti2c bit = %d\n", bit);
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if (eeprom.tick < 9) { |
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eeprom.command <<= 1;
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eeprom.command += bit; |
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eeprom.tick++; |
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if (eeprom.tick == 9) { |
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logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write"); |
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eeprom.ack = 1;
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} |
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} else if (eeprom.tick < 17) { |
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if (eeprom.command & 1) { |
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sda = ((eeprom.data & 0x80) != 0); |
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} |
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eeprom.address <<= 1;
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eeprom.address += bit; |
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eeprom.tick++; |
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eeprom.data <<= 1;
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if (eeprom.tick == 17) { |
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eeprom.data = eeprom.contents[eeprom.address]; |
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logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
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eeprom.ack = 1;
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eeprom.tick = 0;
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} |
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} else if (eeprom.tick >= 17) { |
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sda = 0;
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} |
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} else {
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logout("\tsda changed with raising scl\n");
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} |
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} else {
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logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
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} |
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eeprom.scl = scl; |
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eeprom.sda = sda; |
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} |
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static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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MaltaFPGAState *s = opaque; |
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uint32_t val = 0;
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uint32_t saddr; |
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saddr = (addr & 0xfffff);
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switch (saddr) {
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/* SWITCH Register */
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case 0x00200: |
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val = 0x00000000; /* All switches closed */ |
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break;
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/* STATUS Register */
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case 0x00208: |
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#ifdef TARGET_WORDS_BIGENDIAN
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val = 0x00000012;
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#else
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val = 0x00000010;
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#endif
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break;
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/* JMPRS Register */
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case 0x00210: |
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val = 0x00;
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break;
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/* LEDBAR Register */
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case 0x00408: |
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val = s->leds; |
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break;
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/* BRKRES Register */
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case 0x00508: |
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val = s->brk; |
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break;
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/* UART Registers */
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case 0x00900: |
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case 0x00904: |
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case 0x00908: |
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case 0x0090c: |
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case 0x00910: |
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case 0x00914: |
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case 0x00918: |
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case 0x0091c: |
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val = serial_mm_readl(s->uart, addr); |
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break;
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/* GPOUT Register */
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case 0x00a00: |
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val = s->gpout; |
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break;
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/* XXX: implement a real I2C controller */
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/* GPINP Register */
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case 0x00a08: |
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/* IN = OUT until a real I2C control is implemented */
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if (s->i2csel)
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val = s->i2cout; |
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else
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val = 0x00;
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break;
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/* I2CINP Register */
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case 0x00b00: |
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val = ((s->i2cin & ~1) | eeprom24c0x_read());
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break;
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/* I2COE Register */
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case 0x00b08: |
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val = s->i2coe; |
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break;
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/* I2COUT Register */
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case 0x00b10: |
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val = s->i2cout; |
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break;
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/* I2CSEL Register */
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case 0x00b18: |
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val = s->i2csel; |
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break;
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default:
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#if 0
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printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
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addr);
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#endif
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break;
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} |
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return val;
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} |
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static void malta_fpga_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MaltaFPGAState *s = opaque; |
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uint32_t saddr; |
308 |
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saddr = (addr & 0xfffff);
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switch (saddr) {
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/* SWITCH Register */
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case 0x00200: |
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break;
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/* JMPRS Register */
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case 0x00210: |
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break;
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/* LEDBAR Register */
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/* XXX: implement a 8-LED array */
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case 0x00408: |
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s->leds = val & 0xff;
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break;
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326 |
|
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/* ASCIIWORD Register */
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case 0x00410: |
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snprintf(s->display_text, 9, "%08X", val); |
330 |
malta_fpga_update_display(s); |
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break;
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|
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/* ASCIIPOS0 to ASCIIPOS7 Registers */
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case 0x00418: |
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case 0x00420: |
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case 0x00428: |
337 |
case 0x00430: |
338 |
case 0x00438: |
339 |
case 0x00440: |
340 |
case 0x00448: |
341 |
case 0x00450: |
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s->display_text[(saddr - 0x00418) >> 3] = (char) val; |
343 |
malta_fpga_update_display(s); |
344 |
break;
|
345 |
|
346 |
/* SOFTRES Register */
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case 0x00500: |
348 |
if (val == 0x42) |
349 |
qemu_system_reset_request (); |
350 |
break;
|
351 |
|
352 |
/* BRKRES Register */
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case 0x00508: |
354 |
s->brk = val & 0xff;
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break;
|
356 |
|
357 |
/* UART Registers */
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358 |
case 0x00900: |
359 |
case 0x00904: |
360 |
case 0x00908: |
361 |
case 0x0090c: |
362 |
case 0x00910: |
363 |
case 0x00914: |
364 |
case 0x00918: |
365 |
case 0x0091c: |
366 |
serial_mm_writel(s->uart, addr, val); |
367 |
break;
|
368 |
|
369 |
/* GPOUT Register */
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370 |
case 0x00a00: |
371 |
s->gpout = val & 0xff;
|
372 |
break;
|
373 |
|
374 |
/* I2COE Register */
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375 |
case 0x00b08: |
376 |
s->i2coe = val & 0x03;
|
377 |
break;
|
378 |
|
379 |
/* I2COUT Register */
|
380 |
case 0x00b10: |
381 |
eeprom24c0x_write(val & 0x02, val & 0x01); |
382 |
s->i2cout = val; |
383 |
break;
|
384 |
|
385 |
/* I2CSEL Register */
|
386 |
case 0x00b18: |
387 |
s->i2csel = val & 0x01;
|
388 |
break;
|
389 |
|
390 |
default:
|
391 |
#if 0
|
392 |
printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
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393 |
addr);
|
394 |
#endif
|
395 |
break;
|
396 |
} |
397 |
} |
398 |
|
399 |
static CPUReadMemoryFunc *malta_fpga_read[] = {
|
400 |
malta_fpga_readl, |
401 |
malta_fpga_readl, |
402 |
malta_fpga_readl |
403 |
}; |
404 |
|
405 |
static CPUWriteMemoryFunc *malta_fpga_write[] = {
|
406 |
malta_fpga_writel, |
407 |
malta_fpga_writel, |
408 |
malta_fpga_writel |
409 |
}; |
410 |
|
411 |
void malta_fpga_reset(void *opaque) |
412 |
{ |
413 |
MaltaFPGAState *s = opaque; |
414 |
|
415 |
s->leds = 0x00;
|
416 |
s->brk = 0x0a;
|
417 |
s->gpout = 0x00;
|
418 |
s->i2cin = 0x3;
|
419 |
s->i2coe = 0x0;
|
420 |
s->i2cout = 0x3;
|
421 |
s->i2csel = 0x1;
|
422 |
|
423 |
s->display_text[8] = '\0'; |
424 |
snprintf(s->display_text, 9, " "); |
425 |
malta_fpga_update_display(s); |
426 |
} |
427 |
|
428 |
MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env) |
429 |
{ |
430 |
MaltaFPGAState *s; |
431 |
CharDriverState *uart_chr; |
432 |
int malta;
|
433 |
|
434 |
s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
|
435 |
|
436 |
malta = cpu_register_io_memory(0, malta_fpga_read,
|
437 |
malta_fpga_write, s); |
438 |
|
439 |
cpu_register_physical_memory(base, 0x100000, malta);
|
440 |
|
441 |
s->display = qemu_chr_open("vc");
|
442 |
qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n"); |
443 |
qemu_chr_printf(s->display, "+--------+\r\n");
|
444 |
qemu_chr_printf(s->display, "+ +\r\n");
|
445 |
qemu_chr_printf(s->display, "+--------+\r\n");
|
446 |
qemu_chr_printf(s->display, "\n");
|
447 |
qemu_chr_printf(s->display, "Malta ASCII\r\n");
|
448 |
qemu_chr_printf(s->display, "+--------+\r\n");
|
449 |
qemu_chr_printf(s->display, "+ +\r\n");
|
450 |
qemu_chr_printf(s->display, "+--------+\r\n");
|
451 |
|
452 |
uart_chr = qemu_chr_open("vc");
|
453 |
qemu_chr_printf(uart_chr, "CBUS UART\r\n");
|
454 |
s->uart = serial_mm_init(&cpu_mips_irq_request, env, base, 3, 2, |
455 |
uart_chr, 0);
|
456 |
|
457 |
malta_fpga_reset(s); |
458 |
qemu_register_reset(malta_fpga_reset, s); |
459 |
|
460 |
return s;
|
461 |
} |
462 |
|
463 |
/* Audio support */
|
464 |
#ifdef HAS_AUDIO
|
465 |
static void audio_init (PCIBus *pci_bus) |
466 |
{ |
467 |
struct soundhw *c;
|
468 |
int audio_enabled = 0; |
469 |
|
470 |
for (c = soundhw; !audio_enabled && c->name; ++c) {
|
471 |
audio_enabled = c->enabled; |
472 |
} |
473 |
|
474 |
if (audio_enabled) {
|
475 |
AudioState *s; |
476 |
|
477 |
s = AUD_init (); |
478 |
if (s) {
|
479 |
for (c = soundhw; c->name; ++c) {
|
480 |
if (c->enabled) {
|
481 |
if (c->isa) {
|
482 |
fprintf(stderr, "qemu: Unsupported Sound Card: %s\n", c->name);
|
483 |
exit(1);
|
484 |
} |
485 |
else {
|
486 |
if (pci_bus) {
|
487 |
c->init.init_pci (pci_bus, s); |
488 |
} |
489 |
} |
490 |
} |
491 |
} |
492 |
} |
493 |
} |
494 |
} |
495 |
#endif
|
496 |
|
497 |
/* Network support */
|
498 |
static void network_init (PCIBus *pci_bus) |
499 |
{ |
500 |
int i;
|
501 |
NICInfo *nd; |
502 |
|
503 |
for(i = 0; i < nb_nics; i++) { |
504 |
nd = &nd_table[i]; |
505 |
if (!nd->model) {
|
506 |
nd->model = "pcnet";
|
507 |
} |
508 |
if (i == 0 && strcmp(nd->model, "pcnet") == 0) { |
509 |
/* The malta board has a PCNet card using PCI SLOT 11 */
|
510 |
pci_nic_init(pci_bus, nd, 88);
|
511 |
} else {
|
512 |
pci_nic_init(pci_bus, nd, -1);
|
513 |
} |
514 |
} |
515 |
} |
516 |
|
517 |
/* ROM and pseudo bootloader
|
518 |
|
519 |
The following code implements a very very simple bootloader. It first
|
520 |
loads the registers a0 to a3 to the values expected by the OS, and
|
521 |
then jump at the kernel address.
|
522 |
|
523 |
The bootloader should pass the locations of the kernel arguments and
|
524 |
environment variables tables. Those tables contain the 32-bit address
|
525 |
of NULL terminated strings. The environment variables table should be
|
526 |
terminated by a NULL address.
|
527 |
|
528 |
For a simpler implementation, the number of kernel arguments is fixed
|
529 |
to two (the name of the kernel and the command line), and the two
|
530 |
tables are actually the same one.
|
531 |
|
532 |
The registers a0 to a3 should contain the following values:
|
533 |
a0 - number of kernel arguments
|
534 |
a1 - 32-bit address of the kernel arguments table
|
535 |
a2 - 32-bit address of the environment variables table
|
536 |
a3 - RAM size in bytes
|
537 |
*/
|
538 |
|
539 |
static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_addr) |
540 |
{ |
541 |
uint32_t *p; |
542 |
|
543 |
/* Small bootloader */
|
544 |
p = (uint32_t *) (phys_ram_base + bios_offset); |
545 |
stl_raw(p++, 0x0bf00010); /* j 0x1fc00040 */ |
546 |
stl_raw(p++, 0x00000000); /* nop */ |
547 |
|
548 |
/* Second part of the bootloader */
|
549 |
p = (uint32_t *) (phys_ram_base + bios_offset + 0x040);
|
550 |
stl_raw(p++, 0x3c040000); /* lui a0, 0 */ |
551 |
stl_raw(p++, 0x34840002); /* ori a0, a0, 2 */ |
552 |
stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */ |
553 |
stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */ |
554 |
stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */ |
555 |
stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */ |
556 |
stl_raw(p++, 0x3c070000 | (env->ram_size >> 16)); /* lui a3, high(env->ram_size) */ |
557 |
stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */ |
558 |
stl_raw(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */; |
559 |
stl_raw(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */ |
560 |
stl_raw(p++, 0x03e00008); /* jr ra */ |
561 |
stl_raw(p++, 0x00000000); /* nop */ |
562 |
} |
563 |
|
564 |
static void prom_set(int index, const char *string, ...) |
565 |
{ |
566 |
va_list ap; |
567 |
int32_t *p; |
568 |
int32_t table_addr; |
569 |
char *s;
|
570 |
|
571 |
if (index >= ENVP_NB_ENTRIES)
|
572 |
return;
|
573 |
|
574 |
p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND); |
575 |
p += index; |
576 |
|
577 |
if (string == NULL) { |
578 |
stl_raw(p, 0);
|
579 |
return;
|
580 |
} |
581 |
|
582 |
table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
|
583 |
s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
|
584 |
|
585 |
stl_raw(p, table_addr); |
586 |
|
587 |
va_start(ap, string); |
588 |
vsnprintf (s, ENVP_ENTRY_SIZE, string, ap); |
589 |
va_end(ap); |
590 |
} |
591 |
|
592 |
/* Kernel */
|
593 |
static int64_t load_kernel (CPUState *env)
|
594 |
{ |
595 |
int64_t kernel_addr = 0;
|
596 |
int index = 0; |
597 |
long initrd_size;
|
598 |
|
599 |
if (load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND, &kernel_addr) < 0) { |
600 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
601 |
env->kernel_filename); |
602 |
exit(1);
|
603 |
} |
604 |
|
605 |
/* load initrd */
|
606 |
initrd_size = 0;
|
607 |
if (env->initrd_filename) {
|
608 |
initrd_size = load_image(env->initrd_filename, |
609 |
phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND); |
610 |
if (initrd_size == (target_ulong) -1) { |
611 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
612 |
env->initrd_filename); |
613 |
exit(1);
|
614 |
} |
615 |
} |
616 |
|
617 |
/* Store command line. */
|
618 |
prom_set(index++, env->kernel_filename); |
619 |
if (initrd_size > 0) |
620 |
prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", INITRD_LOAD_ADDR, initrd_size, env->kernel_cmdline); |
621 |
else
|
622 |
prom_set(index++, env->kernel_cmdline); |
623 |
|
624 |
/* Setup minimum environment variables */
|
625 |
prom_set(index++, "memsize");
|
626 |
prom_set(index++, "%i", env->ram_size);
|
627 |
prom_set(index++, "modetty0");
|
628 |
prom_set(index++, "38400n8r");
|
629 |
prom_set(index++, NULL);
|
630 |
|
631 |
return kernel_addr;
|
632 |
} |
633 |
|
634 |
static void main_cpu_reset(void *opaque) |
635 |
{ |
636 |
CPUState *env = opaque; |
637 |
cpu_reset(env); |
638 |
|
639 |
/* The bootload does not need to be rewritten as it is located in a
|
640 |
read only location. The kernel location and the arguments table
|
641 |
location does not change. */
|
642 |
if (env->kernel_filename)
|
643 |
load_kernel (env); |
644 |
} |
645 |
|
646 |
static
|
647 |
void mips_malta_init (int ram_size, int vga_ram_size, int boot_device, |
648 |
DisplayState *ds, const char **fd_filename, int snapshot, |
649 |
const char *kernel_filename, const char *kernel_cmdline, |
650 |
const char *initrd_filename, const char *cpu_model) |
651 |
{ |
652 |
char buf[1024]; |
653 |
unsigned long bios_offset; |
654 |
int64_t kernel_addr; |
655 |
PCIBus *pci_bus; |
656 |
CPUState *env; |
657 |
RTCState *rtc_state; |
658 |
/* fdctrl_t *floppy_controller; */
|
659 |
MaltaFPGAState *malta_fpga; |
660 |
int ret;
|
661 |
mips_def_t *def; |
662 |
|
663 |
/* init CPUs */
|
664 |
if (cpu_model == NULL) { |
665 |
#ifdef TARGET_MIPS64
|
666 |
cpu_model = "R4000";
|
667 |
#else
|
668 |
cpu_model = "4KEc";
|
669 |
#endif
|
670 |
} |
671 |
if (mips_find_by_name(cpu_model, &def) != 0) |
672 |
def = NULL;
|
673 |
env = cpu_init(); |
674 |
cpu_mips_register(env, def); |
675 |
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
676 |
qemu_register_reset(main_cpu_reset, env); |
677 |
|
678 |
/* allocate RAM */
|
679 |
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
680 |
|
681 |
/* Map the bios at two physical locations, as on the real board */
|
682 |
bios_offset = ram_size + vga_ram_size; |
683 |
cpu_register_physical_memory(0x1e000000LL,
|
684 |
BIOS_SIZE, bios_offset | IO_MEM_ROM); |
685 |
cpu_register_physical_memory(0x1fc00000LL,
|
686 |
BIOS_SIZE, bios_offset | IO_MEM_ROM); |
687 |
|
688 |
/* Load a BIOS image except if a kernel image has been specified. In
|
689 |
the later case, just write a small bootloader to the flash
|
690 |
location. */
|
691 |
if (kernel_filename) {
|
692 |
env->ram_size = ram_size; |
693 |
env->kernel_filename = kernel_filename; |
694 |
env->kernel_cmdline = kernel_cmdline; |
695 |
env->initrd_filename = initrd_filename; |
696 |
kernel_addr = load_kernel(env); |
697 |
write_bootloader(env, bios_offset, kernel_addr); |
698 |
} else {
|
699 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
700 |
ret = load_image(buf, phys_ram_base + bios_offset); |
701 |
if (ret < 0 || ret > BIOS_SIZE) { |
702 |
fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
|
703 |
buf); |
704 |
exit(1);
|
705 |
} |
706 |
} |
707 |
|
708 |
/* Board ID = 0x420 (Malta Board with CoreLV)
|
709 |
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
|
710 |
map to the board ID. */
|
711 |
stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420); |
712 |
|
713 |
/* Init internal devices */
|
714 |
cpu_mips_clock_init(env); |
715 |
cpu_mips_irqctrl_init(); |
716 |
|
717 |
/* FPGA */
|
718 |
malta_fpga = malta_fpga_init(0x1f000000LL, env);
|
719 |
|
720 |
/* Interrupt controller */
|
721 |
isa_pic = pic_init(pic_irq_request, env); |
722 |
|
723 |
/* Northbridge */
|
724 |
pci_bus = pci_gt64120_init(isa_pic); |
725 |
|
726 |
/* Southbridge */
|
727 |
piix4_init(pci_bus, 80);
|
728 |
pci_piix3_ide_init(pci_bus, bs_table, 81);
|
729 |
usb_uhci_init(pci_bus, 82);
|
730 |
piix4_pm_init(pci_bus, 83);
|
731 |
pit = pit_init(0x40, 0); |
732 |
DMA_init(0);
|
733 |
|
734 |
/* Super I/O */
|
735 |
kbd_init(); |
736 |
rtc_state = rtc_init(0x70, 8); |
737 |
if (serial_hds[0]) |
738 |
serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
739 |
if (serial_hds[1]) |
740 |
serial_init(&pic_set_irq_new, isa_pic, 0x2f8, 3, serial_hds[1]); |
741 |
if (parallel_hds[0]) |
742 |
parallel_init(0x378, 7, parallel_hds[0]); |
743 |
/* XXX: The floppy controller does not work correctly, something is
|
744 |
probably wrong.
|
745 |
floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table); */
|
746 |
|
747 |
/* Sound card */
|
748 |
#ifdef HAS_AUDIO
|
749 |
audio_init(pci_bus); |
750 |
#endif
|
751 |
|
752 |
/* Network card */
|
753 |
network_init(pci_bus); |
754 |
|
755 |
/* Optional PCI video card */
|
756 |
pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
757 |
ram_size, vga_ram_size); |
758 |
} |
759 |
|
760 |
QEMUMachine mips_malta_machine = { |
761 |
"malta",
|
762 |
"MIPS Malta Core LV",
|
763 |
mips_malta_init, |
764 |
}; |