Revision 61074e46 hw/integratorcp.c
| b/hw/integratorcp.c | ||
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typedef struct icp_pic_state |
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{
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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uint32_t level; |
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uint32_t irq_enabled; |
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uint32_t fiq_enabled; |
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icp_pic_update(s); |
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} |
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static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset) |
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static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset, |
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unsigned size) |
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{
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icp_pic_state *s = (icp_pic_state *)opaque; |
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|
| ... | ... | |
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} |
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static void icp_pic_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value)
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uint64_t value, unsigned size)
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{
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icp_pic_state *s = (icp_pic_state *)opaque; |
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|
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icp_pic_update(s); |
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} |
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static CPUReadMemoryFunc * const icp_pic_readfn[] = {
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icp_pic_read, |
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icp_pic_read, |
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icp_pic_read |
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}; |
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static CPUWriteMemoryFunc * const icp_pic_writefn[] = {
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icp_pic_write, |
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icp_pic_write, |
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icp_pic_write |
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static const MemoryRegionOps icp_pic_ops = {
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.read = icp_pic_read, |
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.write = icp_pic_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static int icp_pic_init(SysBusDevice *dev) |
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{
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icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev); |
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int iomemtype; |
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qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32); |
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sysbus_init_irq(dev, &s->parent_irq); |
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sysbus_init_irq(dev, &s->parent_fiq); |
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iomemtype = cpu_register_io_memory(icp_pic_readfn, |
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icp_pic_writefn, s, |
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DEVICE_NATIVE_ENDIAN); |
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sysbus_init_mmio(dev, 0x00800000, iomemtype); |
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memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000); |
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sysbus_init_mmio_region(dev, &s->iomem); |
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return 0; |
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} |
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