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/*
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|---|---|
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "monitor.h" |
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#include "net.h" |
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#include "sysemu.h" |
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|
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//#define DEBUG_PCI
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struct PCIBus {
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BusState qbus; |
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int bus_num;
|
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int devfn_min;
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pci_set_irq_fn set_irq; |
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pci_map_irq_fn map_irq; |
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uint32_t config_reg; /* XXX: suppress */
|
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/* low level pic */
|
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SetIRQFunc *low_set_irq; |
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qemu_irq *irq_opaque; |
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PCIDevice *devices[256];
|
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PCIDevice *parent_dev; |
| 44 |
PCIBus *next; |
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
|
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int *irq_count;
|
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}; |
| 50 |
|
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
| 52 |
|
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static struct BusInfo pci_bus_info = { |
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.name = "PCI",
|
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.size = sizeof(PCIBus),
|
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.print_dev = pcibus_dev_print, |
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}; |
| 58 |
|
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static void pci_update_mappings(PCIDevice *d); |
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static void pci_set_irq(void *opaque, int irq_num, int level); |
| 61 |
|
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target_phys_addr_t pci_mem_base; |
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
|
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
|
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static PCIBus *first_bus;
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|
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static void pcibus_save(QEMUFile *f, void *opaque) |
| 68 |
{
|
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PCIBus *bus = (PCIBus *)opaque; |
| 70 |
int i;
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|
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qemu_put_be32(f, bus->nirq); |
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for (i = 0; i < bus->nirq; i++) |
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qemu_put_be32(f, bus->irq_count[i]); |
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} |
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|
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static int pcibus_load(QEMUFile *f, void *opaque, int version_id) |
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{
|
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PCIBus *bus = (PCIBus *)opaque; |
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int i, nirq;
|
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|
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if (version_id != 1) |
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return -EINVAL;
|
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|
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nirq = qemu_get_be32(f); |
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if (bus->nirq != nirq) {
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fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
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nirq, bus->nirq); |
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return -EINVAL;
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} |
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for (i = 0; i < nirq; i++) |
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bus->irq_count[i] = qemu_get_be32(f); |
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|
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return 0; |
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} |
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|
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static void pci_bus_reset(void *opaque) |
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{
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PCIBus *bus = (PCIBus *)opaque; |
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int i;
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|
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for (i = 0; i < bus->nirq; i++) { |
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bus->irq_count[i] = 0;
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} |
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for (i = 0; i < 256; i++) { |
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if (bus->devices[i])
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memset(bus->devices[i]->irq_state, 0,
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sizeof(bus->devices[i]->irq_state));
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} |
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} |
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|
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PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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qemu_irq *pic, int devfn_min, int nirq) |
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{
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PCIBus *bus; |
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static int nbus = 0; |
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|
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bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name)); |
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bus->set_irq = set_irq; |
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bus->map_irq = map_irq; |
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bus->irq_opaque = pic; |
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bus->devfn_min = devfn_min; |
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bus->nirq = nirq; |
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bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); |
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bus->next = first_bus; |
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first_bus = bus; |
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register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); |
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qemu_register_reset(pci_bus_reset, bus); |
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return bus;
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} |
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|
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static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
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{
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PCIBus *bus; |
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bus = qemu_mallocz(sizeof(PCIBus));
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bus->map_irq = map_irq; |
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bus->parent_dev = dev; |
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bus->next = dev->bus->next; |
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dev->bus->next = bus; |
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return bus;
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} |
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|
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int pci_bus_num(PCIBus *s)
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{
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return s->bus_num;
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} |
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|
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void pci_device_save(PCIDevice *s, QEMUFile *f)
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{
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int i;
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qemu_put_be32(f, 2); /* PCI device version */ |
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qemu_put_buffer(f, s->config, 256);
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for (i = 0; i < 4; i++) |
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qemu_put_be32(f, s->irq_state[i]); |
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} |
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|
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int pci_device_load(PCIDevice *s, QEMUFile *f)
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{
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uint8_t config[PCI_CONFIG_SPACE_SIZE]; |
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uint32_t version_id; |
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int i;
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|
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version_id = qemu_get_be32(f); |
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if (version_id > 2) |
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return -EINVAL;
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qemu_get_buffer(f, config, sizeof config);
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for (i = 0; i < sizeof config; ++i) |
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if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
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return -EINVAL;
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memcpy(s->config, config, sizeof config);
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|
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pci_update_mappings(s); |
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|
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if (version_id >= 2) |
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for (i = 0; i < 4; i ++) |
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s->irq_state[i] = qemu_get_be32(f); |
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return 0; |
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} |
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|
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static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
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{
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uint16_t *id; |
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|
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id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
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id[0] = cpu_to_le16(pci_default_sub_vendor_id);
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id[1] = cpu_to_le16(pci_default_sub_device_id);
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return 0; |
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} |
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|
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/*
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* Parse [[<domain>:]<bus>:]<slot>, return -1 on error
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*/
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static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
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{
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const char *p; |
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char *e;
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unsigned long val; |
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unsigned long dom = 0, bus = 0; |
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unsigned slot = 0; |
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p = addr; |
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
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if (*e == ':') { |
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bus = val; |
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
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if (*e == ':') { |
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dom = bus; |
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bus = val; |
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
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} |
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} |
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|
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if (dom > 0xffff || bus > 0xff || val > 0x1f) |
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return -1; |
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slot = val; |
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|
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if (*e)
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return -1; |
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|
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/* Note: QEMU doesn't implement domains other than 0 */
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if (dom != 0 || pci_find_bus(bus) == NULL) |
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return -1; |
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|
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*domp = dom; |
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*busp = bus; |
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*slotp = slot; |
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return 0; |
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} |
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|
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int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
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unsigned *slotp)
|
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{
|
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/* strip legacy tag */
|
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if (!strncmp(addr, "pci_addr=", 9)) { |
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addr += 9;
|
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} |
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if (pci_parse_devaddr(addr, domp, busp, slotp)) {
|
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monitor_printf(mon, "Invalid pci address\n");
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return -1; |
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} |
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return 0; |
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} |
| 256 |
|
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static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
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{
|
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int dom, bus;
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unsigned slot;
|
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|
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if (!devaddr) {
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*devfnp = -1;
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return pci_find_bus(0); |
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} |
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|
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if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { |
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return NULL; |
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} |
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|
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*devfnp = slot << 3;
|
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return pci_find_bus(bus);
|
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} |
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|
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static void pci_init_cmask(PCIDevice *dev) |
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{
|
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pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
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pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
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dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; |
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dev->cmask[PCI_REVISION_ID] = 0xff;
|
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dev->cmask[PCI_CLASS_PROG] = 0xff;
|
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pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
|
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dev->cmask[PCI_HEADER_TYPE] = 0xff;
|
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dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
|
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} |
| 286 |
|
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static void pci_init_wmask(PCIDevice *dev) |
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{
|
| 289 |
int i;
|
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dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
|
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dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
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dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
| 293 |
| PCI_COMMAND_MASTER; |
| 294 |
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
|
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dev->wmask[i] = 0xff;
|
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} |
| 297 |
|
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/* -1 for devfn means auto assign */
|
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static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
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const char *name, int devfn, |
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PCIConfigReadFunc *config_read, |
| 302 |
PCIConfigWriteFunc *config_write) |
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{
|
| 304 |
if (devfn < 0) { |
| 305 |
for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
| 306 |
if (!bus->devices[devfn])
|
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goto found;
|
| 308 |
} |
| 309 |
return NULL; |
| 310 |
found: ;
|
| 311 |
} else if (bus->devices[devfn]) { |
| 312 |
return NULL; |
| 313 |
} |
| 314 |
pci_dev->bus = bus; |
| 315 |
pci_dev->devfn = devfn; |
| 316 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
| 317 |
memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
| 318 |
pci_set_default_subsystem_id(pci_dev); |
| 319 |
pci_init_cmask(pci_dev); |
| 320 |
pci_init_wmask(pci_dev); |
| 321 |
|
| 322 |
if (!config_read)
|
| 323 |
config_read = pci_default_read_config; |
| 324 |
if (!config_write)
|
| 325 |
config_write = pci_default_write_config; |
| 326 |
pci_dev->config_read = config_read; |
| 327 |
pci_dev->config_write = config_write; |
| 328 |
bus->devices[devfn] = pci_dev; |
| 329 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
|
| 330 |
return pci_dev;
|
| 331 |
} |
| 332 |
|
| 333 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
| 334 |
int instance_size, int devfn, |
| 335 |
PCIConfigReadFunc *config_read, |
| 336 |
PCIConfigWriteFunc *config_write) |
| 337 |
{
|
| 338 |
PCIDevice *pci_dev; |
| 339 |
|
| 340 |
pci_dev = qemu_mallocz(instance_size); |
| 341 |
pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, |
| 342 |
config_read, config_write); |
| 343 |
return pci_dev;
|
| 344 |
} |
| 345 |
static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
|
| 346 |
{
|
| 347 |
return addr + pci_mem_base;
|
| 348 |
} |
| 349 |
|
| 350 |
static void pci_unregister_io_regions(PCIDevice *pci_dev) |
| 351 |
{
|
| 352 |
PCIIORegion *r; |
| 353 |
int i;
|
| 354 |
|
| 355 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
| 356 |
r = &pci_dev->io_regions[i]; |
| 357 |
if (!r->size || r->addr == -1) |
| 358 |
continue;
|
| 359 |
if (r->type == PCI_ADDRESS_SPACE_IO) {
|
| 360 |
isa_unassign_ioport(r->addr, r->size); |
| 361 |
} else {
|
| 362 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
| 363 |
r->size, |
| 364 |
IO_MEM_UNASSIGNED); |
| 365 |
} |
| 366 |
} |
| 367 |
} |
| 368 |
|
| 369 |
int pci_unregister_device(PCIDevice *pci_dev)
|
| 370 |
{
|
| 371 |
int ret = 0; |
| 372 |
|
| 373 |
if (pci_dev->unregister)
|
| 374 |
ret = pci_dev->unregister(pci_dev); |
| 375 |
if (ret)
|
| 376 |
return ret;
|
| 377 |
|
| 378 |
pci_unregister_io_regions(pci_dev); |
| 379 |
|
| 380 |
qemu_free_irqs(pci_dev->irq); |
| 381 |
pci_dev->bus->devices[pci_dev->devfn] = NULL;
|
| 382 |
qdev_free(&pci_dev->qdev); |
| 383 |
return 0; |
| 384 |
} |
| 385 |
|
| 386 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
| 387 |
uint32_t size, int type,
|
| 388 |
PCIMapIORegionFunc *map_func) |
| 389 |
{
|
| 390 |
PCIIORegion *r; |
| 391 |
uint32_t addr; |
| 392 |
uint32_t wmask; |
| 393 |
|
| 394 |
if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
| 395 |
return;
|
| 396 |
|
| 397 |
if (size & (size-1)) { |
| 398 |
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
| 399 |
"type=0x%x, size=0x%x\n", type, size);
|
| 400 |
exit(1);
|
| 401 |
} |
| 402 |
|
| 403 |
r = &pci_dev->io_regions[region_num]; |
| 404 |
r->addr = -1;
|
| 405 |
r->size = size; |
| 406 |
r->type = type; |
| 407 |
r->map_func = map_func; |
| 408 |
|
| 409 |
wmask = ~(size - 1);
|
| 410 |
if (region_num == PCI_ROM_SLOT) {
|
| 411 |
addr = 0x30;
|
| 412 |
/* ROM enable bit is writeable */
|
| 413 |
wmask |= 1;
|
| 414 |
} else {
|
| 415 |
addr = 0x10 + region_num * 4; |
| 416 |
} |
| 417 |
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
| 418 |
*(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask); |
| 419 |
*(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
|
| 420 |
} |
| 421 |
|
| 422 |
static void pci_update_mappings(PCIDevice *d) |
| 423 |
{
|
| 424 |
PCIIORegion *r; |
| 425 |
int cmd, i;
|
| 426 |
uint32_t last_addr, new_addr, config_ofs; |
| 427 |
|
| 428 |
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
| 429 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
| 430 |
r = &d->io_regions[i]; |
| 431 |
if (i == PCI_ROM_SLOT) {
|
| 432 |
config_ofs = 0x30;
|
| 433 |
} else {
|
| 434 |
config_ofs = 0x10 + i * 4; |
| 435 |
} |
| 436 |
if (r->size != 0) { |
| 437 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 438 |
if (cmd & PCI_COMMAND_IO) {
|
| 439 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
| 440 |
config_ofs)); |
| 441 |
new_addr = new_addr & ~(r->size - 1);
|
| 442 |
last_addr = new_addr + r->size - 1;
|
| 443 |
/* NOTE: we have only 64K ioports on PC */
|
| 444 |
if (last_addr <= new_addr || new_addr == 0 || |
| 445 |
last_addr >= 0x10000) {
|
| 446 |
new_addr = -1;
|
| 447 |
} |
| 448 |
} else {
|
| 449 |
new_addr = -1;
|
| 450 |
} |
| 451 |
} else {
|
| 452 |
if (cmd & PCI_COMMAND_MEMORY) {
|
| 453 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
| 454 |
config_ofs)); |
| 455 |
/* the ROM slot has a specific enable bit */
|
| 456 |
if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
| 457 |
goto no_mem_map;
|
| 458 |
new_addr = new_addr & ~(r->size - 1);
|
| 459 |
last_addr = new_addr + r->size - 1;
|
| 460 |
/* NOTE: we do not support wrapping */
|
| 461 |
/* XXX: as we cannot support really dynamic
|
| 462 |
mappings, we handle specific values as invalid
|
| 463 |
mappings. */
|
| 464 |
if (last_addr <= new_addr || new_addr == 0 || |
| 465 |
last_addr == -1) {
|
| 466 |
new_addr = -1;
|
| 467 |
} |
| 468 |
} else {
|
| 469 |
no_mem_map:
|
| 470 |
new_addr = -1;
|
| 471 |
} |
| 472 |
} |
| 473 |
/* now do the real mapping */
|
| 474 |
if (new_addr != r->addr) {
|
| 475 |
if (r->addr != -1) { |
| 476 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 477 |
int class;
|
| 478 |
/* NOTE: specific hack for IDE in PC case:
|
| 479 |
only one byte must be mapped. */
|
| 480 |
class = d->config[0x0a] | (d->config[0x0b] << 8); |
| 481 |
if (class == 0x0101 && r->size == 4) { |
| 482 |
isa_unassign_ioport(r->addr + 2, 1); |
| 483 |
} else {
|
| 484 |
isa_unassign_ioport(r->addr, r->size); |
| 485 |
} |
| 486 |
} else {
|
| 487 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
| 488 |
r->size, |
| 489 |
IO_MEM_UNASSIGNED); |
| 490 |
qemu_unregister_coalesced_mmio(r->addr, r->size); |
| 491 |
} |
| 492 |
} |
| 493 |
r->addr = new_addr; |
| 494 |
if (r->addr != -1) { |
| 495 |
r->map_func(d, i, r->addr, r->size, r->type); |
| 496 |
} |
| 497 |
} |
| 498 |
} |
| 499 |
} |
| 500 |
} |
| 501 |
|
| 502 |
uint32_t pci_default_read_config(PCIDevice *d, |
| 503 |
uint32_t address, int len)
|
| 504 |
{
|
| 505 |
uint32_t val; |
| 506 |
|
| 507 |
switch(len) {
|
| 508 |
default:
|
| 509 |
case 4: |
| 510 |
if (address <= 0xfc) { |
| 511 |
val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
| 512 |
break;
|
| 513 |
} |
| 514 |
/* fall through */
|
| 515 |
case 2: |
| 516 |
if (address <= 0xfe) { |
| 517 |
val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
| 518 |
break;
|
| 519 |
} |
| 520 |
/* fall through */
|
| 521 |
case 1: |
| 522 |
val = d->config[address]; |
| 523 |
break;
|
| 524 |
} |
| 525 |
return val;
|
| 526 |
} |
| 527 |
|
| 528 |
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
| 529 |
{
|
| 530 |
uint8_t orig[PCI_CONFIG_SPACE_SIZE]; |
| 531 |
int i;
|
| 532 |
|
| 533 |
/* not efficient, but simple */
|
| 534 |
memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE); |
| 535 |
for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) { |
| 536 |
uint8_t wmask = d->wmask[addr]; |
| 537 |
d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask); |
| 538 |
} |
| 539 |
if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24) |
| 540 |
|| ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND]) |
| 541 |
& (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))) |
| 542 |
pci_update_mappings(d); |
| 543 |
} |
| 544 |
|
| 545 |
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
| 546 |
{
|
| 547 |
PCIBus *s = opaque; |
| 548 |
PCIDevice *pci_dev; |
| 549 |
int config_addr, bus_num;
|
| 550 |
|
| 551 |
#if defined(DEBUG_PCI) && 0 |
| 552 |
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
| 553 |
addr, val, len); |
| 554 |
#endif
|
| 555 |
bus_num = (addr >> 16) & 0xff; |
| 556 |
while (s && s->bus_num != bus_num)
|
| 557 |
s = s->next; |
| 558 |
if (!s)
|
| 559 |
return;
|
| 560 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
| 561 |
if (!pci_dev)
|
| 562 |
return;
|
| 563 |
config_addr = addr & 0xff;
|
| 564 |
#if defined(DEBUG_PCI)
|
| 565 |
printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
| 566 |
pci_dev->name, config_addr, val, len); |
| 567 |
#endif
|
| 568 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
| 569 |
} |
| 570 |
|
| 571 |
uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
| 572 |
{
|
| 573 |
PCIBus *s = opaque; |
| 574 |
PCIDevice *pci_dev; |
| 575 |
int config_addr, bus_num;
|
| 576 |
uint32_t val; |
| 577 |
|
| 578 |
bus_num = (addr >> 16) & 0xff; |
| 579 |
while (s && s->bus_num != bus_num)
|
| 580 |
s= s->next; |
| 581 |
if (!s)
|
| 582 |
goto fail;
|
| 583 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
| 584 |
if (!pci_dev) {
|
| 585 |
fail:
|
| 586 |
switch(len) {
|
| 587 |
case 1: |
| 588 |
val = 0xff;
|
| 589 |
break;
|
| 590 |
case 2: |
| 591 |
val = 0xffff;
|
| 592 |
break;
|
| 593 |
default:
|
| 594 |
case 4: |
| 595 |
val = 0xffffffff;
|
| 596 |
break;
|
| 597 |
} |
| 598 |
goto the_end;
|
| 599 |
} |
| 600 |
config_addr = addr & 0xff;
|
| 601 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
| 602 |
#if defined(DEBUG_PCI)
|
| 603 |
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
| 604 |
pci_dev->name, config_addr, val, len); |
| 605 |
#endif
|
| 606 |
the_end:
|
| 607 |
#if defined(DEBUG_PCI) && 0 |
| 608 |
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
| 609 |
addr, val, len); |
| 610 |
#endif
|
| 611 |
return val;
|
| 612 |
} |
| 613 |
|
| 614 |
/***********************************************************/
|
| 615 |
/* generic PCI irq support */
|
| 616 |
|
| 617 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
| 618 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
| 619 |
{
|
| 620 |
PCIDevice *pci_dev = (PCIDevice *)opaque; |
| 621 |
PCIBus *bus; |
| 622 |
int change;
|
| 623 |
|
| 624 |
change = level - pci_dev->irq_state[irq_num]; |
| 625 |
if (!change)
|
| 626 |
return;
|
| 627 |
|
| 628 |
pci_dev->irq_state[irq_num] = level; |
| 629 |
for (;;) {
|
| 630 |
bus = pci_dev->bus; |
| 631 |
irq_num = bus->map_irq(pci_dev, irq_num); |
| 632 |
if (bus->set_irq)
|
| 633 |
break;
|
| 634 |
pci_dev = bus->parent_dev; |
| 635 |
} |
| 636 |
bus->irq_count[irq_num] += change; |
| 637 |
bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
| 638 |
} |
| 639 |
|
| 640 |
/***********************************************************/
|
| 641 |
/* monitor info on PCI */
|
| 642 |
|
| 643 |
typedef struct { |
| 644 |
uint16_t class; |
| 645 |
const char *desc; |
| 646 |
} pci_class_desc; |
| 647 |
|
| 648 |
static const pci_class_desc pci_class_descriptions[] = |
| 649 |
{
|
| 650 |
{ 0x0100, "SCSI controller"},
|
| 651 |
{ 0x0101, "IDE controller"},
|
| 652 |
{ 0x0102, "Floppy controller"},
|
| 653 |
{ 0x0103, "IPI controller"},
|
| 654 |
{ 0x0104, "RAID controller"},
|
| 655 |
{ 0x0106, "SATA controller"},
|
| 656 |
{ 0x0107, "SAS controller"},
|
| 657 |
{ 0x0180, "Storage controller"},
|
| 658 |
{ 0x0200, "Ethernet controller"},
|
| 659 |
{ 0x0201, "Token Ring controller"},
|
| 660 |
{ 0x0202, "FDDI controller"},
|
| 661 |
{ 0x0203, "ATM controller"},
|
| 662 |
{ 0x0280, "Network controller"},
|
| 663 |
{ 0x0300, "VGA controller"},
|
| 664 |
{ 0x0301, "XGA controller"},
|
| 665 |
{ 0x0302, "3D controller"},
|
| 666 |
{ 0x0380, "Display controller"},
|
| 667 |
{ 0x0400, "Video controller"},
|
| 668 |
{ 0x0401, "Audio controller"},
|
| 669 |
{ 0x0402, "Phone"},
|
| 670 |
{ 0x0480, "Multimedia controller"},
|
| 671 |
{ 0x0500, "RAM controller"},
|
| 672 |
{ 0x0501, "Flash controller"},
|
| 673 |
{ 0x0580, "Memory controller"},
|
| 674 |
{ 0x0600, "Host bridge"},
|
| 675 |
{ 0x0601, "ISA bridge"},
|
| 676 |
{ 0x0602, "EISA bridge"},
|
| 677 |
{ 0x0603, "MC bridge"},
|
| 678 |
{ 0x0604, "PCI bridge"},
|
| 679 |
{ 0x0605, "PCMCIA bridge"},
|
| 680 |
{ 0x0606, "NUBUS bridge"},
|
| 681 |
{ 0x0607, "CARDBUS bridge"},
|
| 682 |
{ 0x0608, "RACEWAY bridge"},
|
| 683 |
{ 0x0680, "Bridge"},
|
| 684 |
{ 0x0c03, "USB controller"},
|
| 685 |
{ 0, NULL}
|
| 686 |
}; |
| 687 |
|
| 688 |
static void pci_info_device(PCIDevice *d) |
| 689 |
{
|
| 690 |
Monitor *mon = cur_mon; |
| 691 |
int i, class;
|
| 692 |
PCIIORegion *r; |
| 693 |
const pci_class_desc *desc;
|
| 694 |
|
| 695 |
monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
|
| 696 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
| 697 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
| 698 |
monitor_printf(mon, " ");
|
| 699 |
desc = pci_class_descriptions; |
| 700 |
while (desc->desc && class != desc->class)
|
| 701 |
desc++; |
| 702 |
if (desc->desc) {
|
| 703 |
monitor_printf(mon, "%s", desc->desc);
|
| 704 |
} else {
|
| 705 |
monitor_printf(mon, "Class %04x", class);
|
| 706 |
} |
| 707 |
monitor_printf(mon, ": PCI device %04x:%04x\n",
|
| 708 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
| 709 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
| 710 |
|
| 711 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
| 712 |
monitor_printf(mon, " IRQ %d.\n",
|
| 713 |
d->config[PCI_INTERRUPT_LINE]); |
| 714 |
} |
| 715 |
if (class == 0x0604) { |
| 716 |
monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
| 717 |
} |
| 718 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
| 719 |
r = &d->io_regions[i]; |
| 720 |
if (r->size != 0) { |
| 721 |
monitor_printf(mon, " BAR%d: ", i);
|
| 722 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 723 |
monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
|
| 724 |
r->addr, r->addr + r->size - 1);
|
| 725 |
} else {
|
| 726 |
monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
|
| 727 |
r->addr, r->addr + r->size - 1);
|
| 728 |
} |
| 729 |
} |
| 730 |
} |
| 731 |
if (class == 0x0604 && d->config[0x19] != 0) { |
| 732 |
pci_for_each_device(d->config[0x19], pci_info_device);
|
| 733 |
} |
| 734 |
} |
| 735 |
|
| 736 |
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
| 737 |
{
|
| 738 |
PCIBus *bus = first_bus; |
| 739 |
PCIDevice *d; |
| 740 |
int devfn;
|
| 741 |
|
| 742 |
while (bus && bus->bus_num != bus_num)
|
| 743 |
bus = bus->next; |
| 744 |
if (bus) {
|
| 745 |
for(devfn = 0; devfn < 256; devfn++) { |
| 746 |
d = bus->devices[devfn]; |
| 747 |
if (d)
|
| 748 |
fn(d); |
| 749 |
} |
| 750 |
} |
| 751 |
} |
| 752 |
|
| 753 |
void pci_info(Monitor *mon)
|
| 754 |
{
|
| 755 |
pci_for_each_device(0, pci_info_device);
|
| 756 |
} |
| 757 |
|
| 758 |
PCIDevice *pci_create(const char *name, const char *devaddr) |
| 759 |
{
|
| 760 |
PCIBus *bus; |
| 761 |
int devfn;
|
| 762 |
DeviceState *dev; |
| 763 |
|
| 764 |
bus = pci_get_bus_devfn(&devfn, devaddr); |
| 765 |
if (!bus) {
|
| 766 |
fprintf(stderr, "Invalid PCI device address %s for device %s\n",
|
| 767 |
devaddr, name); |
| 768 |
exit(1);
|
| 769 |
} |
| 770 |
|
| 771 |
dev = qdev_create(&bus->qbus, name); |
| 772 |
qdev_set_prop_int(dev, "devfn", devfn);
|
| 773 |
return (PCIDevice *)dev;
|
| 774 |
} |
| 775 |
|
| 776 |
static const char * const pci_nic_models[] = { |
| 777 |
"ne2k_pci",
|
| 778 |
"i82551",
|
| 779 |
"i82557b",
|
| 780 |
"i82559er",
|
| 781 |
"rtl8139",
|
| 782 |
"e1000",
|
| 783 |
"pcnet",
|
| 784 |
"virtio",
|
| 785 |
NULL
|
| 786 |
}; |
| 787 |
|
| 788 |
static const char * const pci_nic_names[] = { |
| 789 |
"ne2k_pci",
|
| 790 |
"i82551",
|
| 791 |
"i82557b",
|
| 792 |
"i82559er",
|
| 793 |
"rtl8139",
|
| 794 |
"e1000",
|
| 795 |
"pcnet",
|
| 796 |
"virtio-net-pci",
|
| 797 |
NULL
|
| 798 |
}; |
| 799 |
|
| 800 |
/* Initialize a PCI NIC. */
|
| 801 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
| 802 |
const char *default_devaddr) |
| 803 |
{
|
| 804 |
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
| 805 |
PCIDevice *pci_dev; |
| 806 |
DeviceState *dev; |
| 807 |
int i;
|
| 808 |
|
| 809 |
qemu_check_nic_model_list(nd, pci_nic_models, default_model); |
| 810 |
|
| 811 |
for (i = 0; pci_nic_models[i]; i++) { |
| 812 |
if (strcmp(nd->model, pci_nic_models[i]) == 0) { |
| 813 |
pci_dev = pci_create(pci_nic_names[i], devaddr); |
| 814 |
dev = &pci_dev->qdev; |
| 815 |
qdev_set_netdev(dev, nd); |
| 816 |
qdev_init(dev); |
| 817 |
nd->private = dev; |
| 818 |
return pci_dev;
|
| 819 |
} |
| 820 |
} |
| 821 |
|
| 822 |
return NULL; |
| 823 |
} |
| 824 |
|
| 825 |
typedef struct { |
| 826 |
PCIDevice dev; |
| 827 |
PCIBus *bus; |
| 828 |
} PCIBridge; |
| 829 |
|
| 830 |
static void pci_bridge_write_config(PCIDevice *d, |
| 831 |
uint32_t address, uint32_t val, int len)
|
| 832 |
{
|
| 833 |
PCIBridge *s = (PCIBridge *)d; |
| 834 |
|
| 835 |
pci_default_write_config(d, address, val, len); |
| 836 |
s->bus->bus_num = d->config[PCI_SECONDARY_BUS]; |
| 837 |
} |
| 838 |
|
| 839 |
PCIBus *pci_find_bus(int bus_num)
|
| 840 |
{
|
| 841 |
PCIBus *bus = first_bus; |
| 842 |
|
| 843 |
while (bus && bus->bus_num != bus_num)
|
| 844 |
bus = bus->next; |
| 845 |
|
| 846 |
return bus;
|
| 847 |
} |
| 848 |
|
| 849 |
PCIDevice *pci_find_device(int bus_num, int slot, int function) |
| 850 |
{
|
| 851 |
PCIBus *bus = pci_find_bus(bus_num); |
| 852 |
|
| 853 |
if (!bus)
|
| 854 |
return NULL; |
| 855 |
|
| 856 |
return bus->devices[PCI_DEVFN(slot, function)];
|
| 857 |
} |
| 858 |
|
| 859 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
| 860 |
pci_map_irq_fn map_irq, const char *name) |
| 861 |
{
|
| 862 |
PCIBridge *s; |
| 863 |
s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
|
| 864 |
devfn, NULL, pci_bridge_write_config);
|
| 865 |
|
| 866 |
pci_config_set_vendor_id(s->dev.config, vid); |
| 867 |
pci_config_set_device_id(s->dev.config, did); |
| 868 |
|
| 869 |
s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
| 870 |
s->dev.config[0x05] = 0x00; |
| 871 |
s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
| 872 |
s->dev.config[0x07] = 0x00; // status = fast devsel |
| 873 |
s->dev.config[0x08] = 0x00; // revision |
| 874 |
s->dev.config[0x09] = 0x00; // programming i/f |
| 875 |
pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
| 876 |
s->dev.config[0x0D] = 0x10; // latency_timer |
| 877 |
s->dev.config[PCI_HEADER_TYPE] = |
| 878 |
PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
|
| 879 |
s->dev.config[0x1E] = 0xa0; // secondary status |
| 880 |
|
| 881 |
s->bus = pci_register_secondary_bus(&s->dev, map_irq); |
| 882 |
return s->bus;
|
| 883 |
} |
| 884 |
|
| 885 |
static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
| 886 |
{
|
| 887 |
PCIDevice *pci_dev = (PCIDevice *)qdev; |
| 888 |
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
| 889 |
PCIBus *bus; |
| 890 |
int devfn;
|
| 891 |
|
| 892 |
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
| 893 |
devfn = qdev_get_prop_int(qdev, "devfn", -1); |
| 894 |
pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
| 895 |
info->config_read, info->config_write); |
| 896 |
assert(pci_dev); |
| 897 |
info->init(pci_dev); |
| 898 |
} |
| 899 |
|
| 900 |
void pci_qdev_register(PCIDeviceInfo *info)
|
| 901 |
{
|
| 902 |
info->qdev.init = pci_qdev_init; |
| 903 |
info->qdev.bus_info = &pci_bus_info; |
| 904 |
qdev_register(&info->qdev); |
| 905 |
} |
| 906 |
|
| 907 |
void pci_qdev_register_many(PCIDeviceInfo *info)
|
| 908 |
{
|
| 909 |
while (info->qdev.name) {
|
| 910 |
pci_qdev_register(info); |
| 911 |
info++; |
| 912 |
} |
| 913 |
} |
| 914 |
|
| 915 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
| 916 |
{
|
| 917 |
DeviceState *dev; |
| 918 |
|
| 919 |
dev = qdev_create(&bus->qbus, name); |
| 920 |
qdev_set_prop_int(dev, "devfn", devfn);
|
| 921 |
qdev_init(dev); |
| 922 |
|
| 923 |
return (PCIDevice *)dev;
|
| 924 |
} |
| 925 |
|
| 926 |
static int pci_find_space(PCIDevice *pdev, uint8_t size) |
| 927 |
{
|
| 928 |
int offset = PCI_CONFIG_HEADER_SIZE;
|
| 929 |
int i;
|
| 930 |
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
|
| 931 |
if (pdev->used[i])
|
| 932 |
offset = i + 1;
|
| 933 |
else if (i - offset + 1 == size) |
| 934 |
return offset;
|
| 935 |
return 0; |
| 936 |
} |
| 937 |
|
| 938 |
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
| 939 |
uint8_t *prev_p) |
| 940 |
{
|
| 941 |
uint8_t next, prev; |
| 942 |
|
| 943 |
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
| 944 |
return 0; |
| 945 |
|
| 946 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
| 947 |
prev = next + PCI_CAP_LIST_NEXT) |
| 948 |
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
| 949 |
break;
|
| 950 |
|
| 951 |
if (prev_p)
|
| 952 |
*prev_p = prev; |
| 953 |
return next;
|
| 954 |
} |
| 955 |
|
| 956 |
/* Reserve space and add capability to the linked list in pci config space */
|
| 957 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
| 958 |
{
|
| 959 |
uint8_t offset = pci_find_space(pdev, size); |
| 960 |
uint8_t *config = pdev->config + offset; |
| 961 |
if (!offset)
|
| 962 |
return -ENOSPC;
|
| 963 |
config[PCI_CAP_LIST_ID] = cap_id; |
| 964 |
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
| 965 |
pdev->config[PCI_CAPABILITY_LIST] = offset; |
| 966 |
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
| 967 |
memset(pdev->used + offset, 0xFF, size);
|
| 968 |
/* Make capability read-only by default */
|
| 969 |
memset(pdev->wmask + offset, 0, size);
|
| 970 |
/* Check capability by default */
|
| 971 |
memset(pdev->cmask + offset, 0xFF, size);
|
| 972 |
return offset;
|
| 973 |
} |
| 974 |
|
| 975 |
/* Unlink capability from the pci config space. */
|
| 976 |
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
| 977 |
{
|
| 978 |
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
| 979 |
if (!offset)
|
| 980 |
return;
|
| 981 |
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
| 982 |
/* Make capability writeable again */
|
| 983 |
memset(pdev->wmask + offset, 0xff, size);
|
| 984 |
/* Clear cmask as device-specific registers can't be checked */
|
| 985 |
memset(pdev->cmask + offset, 0, size);
|
| 986 |
memset(pdev->used + offset, 0, size);
|
| 987 |
|
| 988 |
if (!pdev->config[PCI_CAPABILITY_LIST])
|
| 989 |
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
| 990 |
} |
| 991 |
|
| 992 |
/* Reserve space for capability at a known offset (to call after load). */
|
| 993 |
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
|
| 994 |
{
|
| 995 |
memset(pdev->used + offset, 0xff, size);
|
| 996 |
} |
| 997 |
|
| 998 |
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
| 999 |
{
|
| 1000 |
return pci_find_capability_list(pdev, cap_id, NULL); |
| 1001 |
} |
| 1002 |
|
| 1003 |
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) |
| 1004 |
{
|
| 1005 |
PCIDevice *d = (PCIDevice *)dev; |
| 1006 |
const pci_class_desc *desc;
|
| 1007 |
char ctxt[64]; |
| 1008 |
PCIIORegion *r; |
| 1009 |
int i, class;
|
| 1010 |
|
| 1011 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
| 1012 |
desc = pci_class_descriptions; |
| 1013 |
while (desc->desc && class != desc->class)
|
| 1014 |
desc++; |
| 1015 |
if (desc->desc) {
|
| 1016 |
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); |
| 1017 |
} else {
|
| 1018 |
snprintf(ctxt, sizeof(ctxt), "Class %04x", class); |
| 1019 |
} |
| 1020 |
|
| 1021 |
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
| 1022 |
"pci id %04x:%04x (sub %04x:%04x)\n",
|
| 1023 |
indent, "", ctxt,
|
| 1024 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7, |
| 1025 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
| 1026 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))), |
| 1027 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))), |
| 1028 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID)))); |
| 1029 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
| 1030 |
r = &d->io_regions[i]; |
| 1031 |
if (!r->size)
|
| 1032 |
continue;
|
| 1033 |
monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "", |
| 1034 |
i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem", |
| 1035 |
r->addr, r->addr + r->size - 1);
|
| 1036 |
} |
| 1037 |
} |