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1
/*
2
 *  PowerPC emulation for qemu: main translation routines.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20
#include <stdarg.h>
21
#include <stdlib.h>
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#include <stdio.h>
23
#include <string.h>
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#include <inttypes.h>
25

    
26
#include "cpu.h"
27
#include "exec-all.h"
28
#include "disas.h"
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#include "helper.h"
30
#include "tcg-op.h"
31
#include "qemu-common.h"
32

    
33
#define CPU_SINGLE_STEP 0x1
34
#define CPU_BRANCH_STEP 0x2
35
#define GDBSTUB_SINGLE_STEP 0x4
36

    
37
/* Include definitions for instructions classes and implementations flags */
38
//#define DO_SINGLE_STEP
39
//#define PPC_DEBUG_DISAS
40
//#define DEBUG_MEMORY_ACCESSES
41
//#define DO_PPC_STATISTICS
42
//#define OPTIMIZE_FPRF_UPDATE
43

    
44
/*****************************************************************************/
45
/* Code translation helpers                                                  */
46

    
47
static TCGv cpu_env, cpu_T[3];
48

    
49
#include "gen-icount.h"
50

    
51
void ppc_translate_init(void)
52
{
53
    static int done_init = 0;
54
    if (done_init)
55
        return;
56
    cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
57
#if TARGET_LONG_BITS > HOST_LONG_BITS
58
    cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
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                                  TCG_AREG0, offsetof(CPUState, t0), "T0");
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    cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
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                                  TCG_AREG0, offsetof(CPUState, t1), "T1");
62
    cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
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                                  TCG_AREG0, offsetof(CPUState, t2), "T2");
64
#else
65
    cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
66
    cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
67
    cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
68
#endif
69

    
70
    /* register helpers */
71
#undef DEF_HELPER
72
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
73
#include "helper.h"
74

    
75
    done_init = 1;
76
}
77

    
78
static inline void tcg_gen_helper_0_i(void *func, TCGv arg)
79
{
80
    TCGv tmp = tcg_const_i32(arg);
81

    
82
    tcg_gen_helper_0_1(func, tmp);
83
    tcg_temp_free(tmp);
84
}
85

    
86

    
87
#if defined(OPTIMIZE_FPRF_UPDATE)
88
static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
89
static uint16_t **gen_fprf_ptr;
90
#endif
91

    
92
static always_inline void gen_set_T0 (target_ulong val)
93
{
94
#if defined(TARGET_PPC64)
95
    if (val >> 32)
96
        gen_op_set_T0_64(val >> 32, val);
97
    else
98
#endif
99
        gen_op_set_T0(val);
100
}
101

    
102
static always_inline void gen_set_T1 (target_ulong val)
103
{
104
#if defined(TARGET_PPC64)
105
    if (val >> 32)
106
        gen_op_set_T1_64(val >> 32, val);
107
    else
108
#endif
109
        gen_op_set_T1(val);
110
}
111

    
112
#define GEN8(func, NAME)                                                      \
113
static GenOpFunc *NAME ## _table [8] = {                                      \
114
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
115
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
116
};                                                                            \
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static always_inline void func (int n)                                        \
118
{                                                                             \
119
    NAME ## _table[n]();                                                      \
120
}
121

    
122
#define GEN16(func, NAME)                                                     \
123
static GenOpFunc *NAME ## _table [16] = {                                     \
124
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
125
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
126
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
127
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
128
};                                                                            \
129
static always_inline void func (int n)                                        \
130
{                                                                             \
131
    NAME ## _table[n]();                                                      \
132
}
133

    
134
#define GEN32(func, NAME)                                                     \
135
static GenOpFunc *NAME ## _table [32] = {                                     \
136
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
137
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
139
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
140
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
141
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
142
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
143
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
144
};                                                                            \
145
static always_inline void func (int n)                                        \
146
{                                                                             \
147
    NAME ## _table[n]();                                                      \
148
}
149

    
150
/* Condition register moves */
151
GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
152
GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
153
GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
154
#if 0 // Unused
155
GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
156
#endif
157

    
158
/* General purpose registers moves */
159
GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
160
GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
161
GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
162

    
163
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
164
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
165
#if 0 // unused
166
GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
167
#endif
168

    
169
/* floating point registers moves */
170
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
171
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
172
GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
173
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
174
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
175
#if 0 // unused
176
GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
177
#endif
178

    
179
/* internal defines */
180
typedef struct DisasContext {
181
    struct TranslationBlock *tb;
182
    target_ulong nip;
183
    uint32_t opcode;
184
    uint32_t exception;
185
    /* Routine used to access memory */
186
    int mem_idx;
187
    /* Translation flags */
188
#if !defined(CONFIG_USER_ONLY)
189
    int supervisor;
190
#endif
191
#if defined(TARGET_PPC64)
192
    int sf_mode;
193
#endif
194
    int fpu_enabled;
195
    int altivec_enabled;
196
    int spe_enabled;
197
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
198
    int singlestep_enabled;
199
    int dcache_line_size;
200
} DisasContext;
201

    
202
struct opc_handler_t {
203
    /* invalid bits */
204
    uint32_t inval;
205
    /* instruction type */
206
    uint64_t type;
207
    /* handler */
208
    void (*handler)(DisasContext *ctx);
209
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
210
    const unsigned char *oname;
211
#endif
212
#if defined(DO_PPC_STATISTICS)
213
    uint64_t count;
214
#endif
215
};
216

    
217
static always_inline void gen_set_Rc0 (DisasContext *ctx)
218
{
219
#if defined(TARGET_PPC64)
220
    if (ctx->sf_mode)
221
        gen_op_cmpi_64(0);
222
    else
223
#endif
224
        gen_op_cmpi(0);
225
    gen_op_set_Rc0();
226
}
227

    
228
static always_inline void gen_reset_fpstatus (void)
229
{
230
#ifdef CONFIG_SOFTFLOAT
231
    gen_op_reset_fpstatus();
232
#endif
233
}
234

    
235
static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
236
{
237
    if (set_fprf != 0) {
238
        /* This case might be optimized later */
239
#if defined(OPTIMIZE_FPRF_UPDATE)
240
        *gen_fprf_ptr++ = gen_opc_ptr;
241
#endif
242
        gen_op_compute_fprf(1);
243
        if (unlikely(set_rc))
244
            gen_op_store_T0_crf(1);
245
        gen_op_float_check_status();
246
    } else if (unlikely(set_rc)) {
247
        /* We always need to compute fpcc */
248
        gen_op_compute_fprf(0);
249
        gen_op_store_T0_crf(1);
250
        if (set_fprf)
251
            gen_op_float_check_status();
252
    }
253
}
254

    
255
static always_inline void gen_optimize_fprf (void)
256
{
257
#if defined(OPTIMIZE_FPRF_UPDATE)
258
    uint16_t **ptr;
259

    
260
    for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
261
        *ptr = INDEX_op_nop1;
262
    gen_fprf_ptr = gen_fprf_buf;
263
#endif
264
}
265

    
266
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
267
{
268
    TCGv tmp;
269
#if defined(TARGET_PPC64)
270
    if (ctx->sf_mode)
271
        tmp = tcg_const_i64(nip);
272
    else
273
#endif
274
        tmp = tcg_const_i32((uint32_t)nip);
275

    
276
    tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUState, nip));
277
    tcg_temp_free(tmp);
278
}
279

    
280
#define GEN_EXCP(ctx, excp, error)                                            \
281
do {                                                                          \
282
    if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \
283
        gen_update_nip(ctx, (ctx)->nip);                                      \
284
    }                                                                         \
285
    gen_op_raise_exception_err((excp), (error));                              \
286
    ctx->exception = (excp);                                                  \
287
} while (0)
288

    
289
#define GEN_EXCP_INVAL(ctx)                                                   \
290
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
291
         POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
292

    
293
#define GEN_EXCP_PRIVOPC(ctx)                                                 \
294
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
295
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
296

    
297
#define GEN_EXCP_PRIVREG(ctx)                                                 \
298
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
299
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
300

    
301
#define GEN_EXCP_NO_FP(ctx)                                                   \
302
GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
303

    
304
#define GEN_EXCP_NO_AP(ctx)                                                   \
305
GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
306

    
307
#define GEN_EXCP_NO_VR(ctx)                                                   \
308
GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
309

    
310
/* Stop translation */
311
static always_inline void GEN_STOP (DisasContext *ctx)
312
{
313
    gen_update_nip(ctx, ctx->nip);
314
    ctx->exception = POWERPC_EXCP_STOP;
315
}
316

    
317
/* No need to update nip here, as execution flow will change */
318
static always_inline void GEN_SYNC (DisasContext *ctx)
319
{
320
    ctx->exception = POWERPC_EXCP_SYNC;
321
}
322

    
323
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
324
static void gen_##name (DisasContext *ctx);                                   \
325
GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
326
static void gen_##name (DisasContext *ctx)
327

    
328
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
329
static void gen_##name (DisasContext *ctx);                                   \
330
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \
331
static void gen_##name (DisasContext *ctx)
332

    
333
typedef struct opcode_t {
334
    unsigned char opc1, opc2, opc3;
335
#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
336
    unsigned char pad[5];
337
#else
338
    unsigned char pad[1];
339
#endif
340
    opc_handler_t handler;
341
    const unsigned char *oname;
342
} opcode_t;
343

    
344
/*****************************************************************************/
345
/***                           Instruction decoding                        ***/
346
#define EXTRACT_HELPER(name, shift, nb)                                       \
347
static always_inline uint32_t name (uint32_t opcode)                          \
348
{                                                                             \
349
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
350
}
351

    
352
#define EXTRACT_SHELPER(name, shift, nb)                                      \
353
static always_inline int32_t name (uint32_t opcode)                           \
354
{                                                                             \
355
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
356
}
357

    
358
/* Opcode part 1 */
359
EXTRACT_HELPER(opc1, 26, 6);
360
/* Opcode part 2 */
361
EXTRACT_HELPER(opc2, 1, 5);
362
/* Opcode part 3 */
363
EXTRACT_HELPER(opc3, 6, 5);
364
/* Update Cr0 flags */
365
EXTRACT_HELPER(Rc, 0, 1);
366
/* Destination */
367
EXTRACT_HELPER(rD, 21, 5);
368
/* Source */
369
EXTRACT_HELPER(rS, 21, 5);
370
/* First operand */
371
EXTRACT_HELPER(rA, 16, 5);
372
/* Second operand */
373
EXTRACT_HELPER(rB, 11, 5);
374
/* Third operand */
375
EXTRACT_HELPER(rC, 6, 5);
376
/***                               Get CRn                                 ***/
377
EXTRACT_HELPER(crfD, 23, 3);
378
EXTRACT_HELPER(crfS, 18, 3);
379
EXTRACT_HELPER(crbD, 21, 5);
380
EXTRACT_HELPER(crbA, 16, 5);
381
EXTRACT_HELPER(crbB, 11, 5);
382
/* SPR / TBL */
383
EXTRACT_HELPER(_SPR, 11, 10);
384
static always_inline uint32_t SPR (uint32_t opcode)
385
{
386
    uint32_t sprn = _SPR(opcode);
387

    
388
    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
389
}
390
/***                              Get constants                            ***/
391
EXTRACT_HELPER(IMM, 12, 8);
392
/* 16 bits signed immediate value */
393
EXTRACT_SHELPER(SIMM, 0, 16);
394
/* 16 bits unsigned immediate value */
395
EXTRACT_HELPER(UIMM, 0, 16);
396
/* Bit count */
397
EXTRACT_HELPER(NB, 11, 5);
398
/* Shift count */
399
EXTRACT_HELPER(SH, 11, 5);
400
/* Mask start */
401
EXTRACT_HELPER(MB, 6, 5);
402
/* Mask end */
403
EXTRACT_HELPER(ME, 1, 5);
404
/* Trap operand */
405
EXTRACT_HELPER(TO, 21, 5);
406

    
407
EXTRACT_HELPER(CRM, 12, 8);
408
EXTRACT_HELPER(FM, 17, 8);
409
EXTRACT_HELPER(SR, 16, 4);
410
EXTRACT_HELPER(FPIMM, 12, 4);
411

    
412
/***                            Jump target decoding                       ***/
413
/* Displacement */
414
EXTRACT_SHELPER(d, 0, 16);
415
/* Immediate address */
416
static always_inline target_ulong LI (uint32_t opcode)
417
{
418
    return (opcode >> 0) & 0x03FFFFFC;
419
}
420

    
421
static always_inline uint32_t BD (uint32_t opcode)
422
{
423
    return (opcode >> 0) & 0xFFFC;
424
}
425

    
426
EXTRACT_HELPER(BO, 21, 5);
427
EXTRACT_HELPER(BI, 16, 5);
428
/* Absolute/relative address */
429
EXTRACT_HELPER(AA, 1, 1);
430
/* Link */
431
EXTRACT_HELPER(LK, 0, 1);
432

    
433
/* Create a mask between <start> and <end> bits */
434
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
435
{
436
    target_ulong ret;
437

    
438
#if defined(TARGET_PPC64)
439
    if (likely(start == 0)) {
440
        ret = UINT64_MAX << (63 - end);
441
    } else if (likely(end == 63)) {
442
        ret = UINT64_MAX >> start;
443
    }
444
#else
445
    if (likely(start == 0)) {
446
        ret = UINT32_MAX << (31  - end);
447
    } else if (likely(end == 31)) {
448
        ret = UINT32_MAX >> start;
449
    }
450
#endif
451
    else {
452
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
453
            (((target_ulong)(-1ULL) >> (end)) >> 1);
454
        if (unlikely(start > end))
455
            return ~ret;
456
    }
457

    
458
    return ret;
459
}
460

    
461
/*****************************************************************************/
462
/* PowerPC Instructions types definitions                                    */
463
enum {
464
    PPC_NONE           = 0x0000000000000000ULL,
465
    /* PowerPC base instructions set                                         */
466
    PPC_INSNS_BASE     = 0x0000000000000001ULL,
467
    /*   integer operations instructions                                     */
468
#define PPC_INTEGER PPC_INSNS_BASE
469
    /*   flow control instructions                                           */
470
#define PPC_FLOW    PPC_INSNS_BASE
471
    /*   virtual memory instructions                                         */
472
#define PPC_MEM     PPC_INSNS_BASE
473
    /*   ld/st with reservation instructions                                 */
474
#define PPC_RES     PPC_INSNS_BASE
475
    /*   spr/msr access instructions                                         */
476
#define PPC_MISC    PPC_INSNS_BASE
477
    /* Deprecated instruction sets                                           */
478
    /*   Original POWER instruction set                                      */
479
    PPC_POWER          = 0x0000000000000002ULL,
480
    /*   POWER2 instruction set extension                                    */
481
    PPC_POWER2         = 0x0000000000000004ULL,
482
    /*   Power RTC support                                                   */
483
    PPC_POWER_RTC      = 0x0000000000000008ULL,
484
    /*   Power-to-PowerPC bridge (601)                                       */
485
    PPC_POWER_BR       = 0x0000000000000010ULL,
486
    /* 64 bits PowerPC instruction set                                       */
487
    PPC_64B            = 0x0000000000000020ULL,
488
    /*   New 64 bits extensions (PowerPC 2.0x)                               */
489
    PPC_64BX           = 0x0000000000000040ULL,
490
    /*   64 bits hypervisor extensions                                       */
491
    PPC_64H            = 0x0000000000000080ULL,
492
    /*   New wait instruction (PowerPC 2.0x)                                 */
493
    PPC_WAIT           = 0x0000000000000100ULL,
494
    /*   Time base mftb instruction                                          */
495
    PPC_MFTB           = 0x0000000000000200ULL,
496

    
497
    /* Fixed-point unit extensions                                           */
498
    /*   PowerPC 602 specific                                                */
499
    PPC_602_SPEC       = 0x0000000000000400ULL,
500
    /*   isel instruction                                                    */
501
    PPC_ISEL           = 0x0000000000000800ULL,
502
    /*   popcntb instruction                                                 */
503
    PPC_POPCNTB        = 0x0000000000001000ULL,
504
    /*   string load / store                                                 */
505
    PPC_STRING         = 0x0000000000002000ULL,
506

    
507
    /* Floating-point unit extensions                                        */
508
    /*   Optional floating point instructions                                */
509
    PPC_FLOAT          = 0x0000000000010000ULL,
510
    /* New floating-point extensions (PowerPC 2.0x)                          */
511
    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
512
    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
513
    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
514
    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
515
    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
516
    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
517
    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
518

    
519
    /* Vector/SIMD extensions                                                */
520
    /*   Altivec support                                                     */
521
    PPC_ALTIVEC        = 0x0000000001000000ULL,
522
    /*   PowerPC 2.03 SPE extension                                          */
523
    PPC_SPE            = 0x0000000002000000ULL,
524
    /*   PowerPC 2.03 SPE floating-point extension                           */
525
    PPC_SPEFPU         = 0x0000000004000000ULL,
526

    
527
    /* Optional memory control instructions                                  */
528
    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
529
    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
530
    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
531
    /*   sync instruction                                                    */
532
    PPC_MEM_SYNC       = 0x0000000080000000ULL,
533
    /*   eieio instruction                                                   */
534
    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
535

    
536
    /* Cache control instructions                                            */
537
    PPC_CACHE          = 0x0000000200000000ULL,
538
    /*   icbi instruction                                                    */
539
    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
540
    /*   dcbz instruction with fixed cache line size                         */
541
    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
542
    /*   dcbz instruction with tunable cache line size                       */
543
    PPC_CACHE_DCBZT    = 0x0000001000000000ULL,
544
    /*   dcba instruction                                                    */
545
    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
546
    /*   Freescale cache locking instructions                                */
547
    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
548

    
549
    /* MMU related extensions                                                */
550
    /*   external control instructions                                       */
551
    PPC_EXTERN         = 0x0000010000000000ULL,
552
    /*   segment register access instructions                                */
553
    PPC_SEGMENT        = 0x0000020000000000ULL,
554
    /*   PowerPC 6xx TLB management instructions                             */
555
    PPC_6xx_TLB        = 0x0000040000000000ULL,
556
    /* PowerPC 74xx TLB management instructions                              */
557
    PPC_74xx_TLB       = 0x0000080000000000ULL,
558
    /*   PowerPC 40x TLB management instructions                             */
559
    PPC_40x_TLB        = 0x0000100000000000ULL,
560
    /*   segment register access instructions for PowerPC 64 "bridge"        */
561
    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
562
    /*   SLB management                                                      */
563
    PPC_SLBI           = 0x0000400000000000ULL,
564

    
565
    /* Embedded PowerPC dedicated instructions                               */
566
    PPC_WRTEE          = 0x0001000000000000ULL,
567
    /* PowerPC 40x exception model                                           */
568
    PPC_40x_EXCP       = 0x0002000000000000ULL,
569
    /* PowerPC 405 Mac instructions                                          */
570
    PPC_405_MAC        = 0x0004000000000000ULL,
571
    /* PowerPC 440 specific instructions                                     */
572
    PPC_440_SPEC       = 0x0008000000000000ULL,
573
    /* BookE (embedded) PowerPC specification                                */
574
    PPC_BOOKE          = 0x0010000000000000ULL,
575
    /* mfapidi instruction                                                   */
576
    PPC_MFAPIDI        = 0x0020000000000000ULL,
577
    /* tlbiva instruction                                                    */
578
    PPC_TLBIVA         = 0x0040000000000000ULL,
579
    /* tlbivax instruction                                                   */
580
    PPC_TLBIVAX        = 0x0080000000000000ULL,
581
    /* PowerPC 4xx dedicated instructions                                    */
582
    PPC_4xx_COMMON     = 0x0100000000000000ULL,
583
    /* PowerPC 40x ibct instructions                                         */
584
    PPC_40x_ICBT       = 0x0200000000000000ULL,
585
    /* rfmci is not implemented in all BookE PowerPC                         */
586
    PPC_RFMCI          = 0x0400000000000000ULL,
587
    /* rfdi instruction                                                      */
588
    PPC_RFDI           = 0x0800000000000000ULL,
589
    /* DCR accesses                                                          */
590
    PPC_DCR            = 0x1000000000000000ULL,
591
    /* DCR extended accesse                                                  */
592
    PPC_DCRX           = 0x2000000000000000ULL,
593
    /* user-mode DCR access, implemented in PowerPC 460                      */
594
    PPC_DCRUX          = 0x4000000000000000ULL,
595
};
596

    
597
/*****************************************************************************/
598
/* PowerPC instructions table                                                */
599
#if HOST_LONG_BITS == 64
600
#define OPC_ALIGN 8
601
#else
602
#define OPC_ALIGN 4
603
#endif
604
#if defined(__APPLE__)
605
#define OPCODES_SECTION                                                       \
606
    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
607
#else
608
#define OPCODES_SECTION                                                       \
609
    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
610
#endif
611

    
612
#if defined(DO_PPC_STATISTICS)
613
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
614
OPCODES_SECTION opcode_t opc_##name = {                                       \
615
    .opc1 = op1,                                                              \
616
    .opc2 = op2,                                                              \
617
    .opc3 = op3,                                                              \
618
    .pad  = { 0, },                                                           \
619
    .handler = {                                                              \
620
        .inval   = invl,                                                      \
621
        .type = _typ,                                                         \
622
        .handler = &gen_##name,                                               \
623
        .oname = stringify(name),                                             \
624
    },                                                                        \
625
    .oname = stringify(name),                                                 \
626
}
627
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
628
OPCODES_SECTION opcode_t opc_##name = {                                       \
629
    .opc1 = op1,                                                              \
630
    .opc2 = op2,                                                              \
631
    .opc3 = op3,                                                              \
632
    .pad  = { 0, },                                                           \
633
    .handler = {                                                              \
634
        .inval   = invl,                                                      \
635
        .type = _typ,                                                         \
636
        .handler = &gen_##name,                                               \
637
        .oname = onam,                                                        \
638
    },                                                                        \
639
    .oname = onam,                                                            \
640
}
641
#else
642
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
643
OPCODES_SECTION opcode_t opc_##name = {                                       \
644
    .opc1 = op1,                                                              \
645
    .opc2 = op2,                                                              \
646
    .opc3 = op3,                                                              \
647
    .pad  = { 0, },                                                           \
648
    .handler = {                                                              \
649
        .inval   = invl,                                                      \
650
        .type = _typ,                                                         \
651
        .handler = &gen_##name,                                               \
652
    },                                                                        \
653
    .oname = stringify(name),                                                 \
654
}
655
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
656
OPCODES_SECTION opcode_t opc_##name = {                                       \
657
    .opc1 = op1,                                                              \
658
    .opc2 = op2,                                                              \
659
    .opc3 = op3,                                                              \
660
    .pad  = { 0, },                                                           \
661
    .handler = {                                                              \
662
        .inval   = invl,                                                      \
663
        .type = _typ,                                                         \
664
        .handler = &gen_##name,                                               \
665
    },                                                                        \
666
    .oname = onam,                                                            \
667
}
668
#endif
669

    
670
#define GEN_OPCODE_MARK(name)                                                 \
671
OPCODES_SECTION opcode_t opc_##name = {                                       \
672
    .opc1 = 0xFF,                                                             \
673
    .opc2 = 0xFF,                                                             \
674
    .opc3 = 0xFF,                                                             \
675
    .pad  = { 0, },                                                           \
676
    .handler = {                                                              \
677
        .inval   = 0x00000000,                                                \
678
        .type = 0x00,                                                         \
679
        .handler = NULL,                                                      \
680
    },                                                                        \
681
    .oname = stringify(name),                                                 \
682
}
683

    
684
/* Start opcode list */
685
GEN_OPCODE_MARK(start);
686

    
687
/* Invalid instruction */
688
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
689
{
690
    GEN_EXCP_INVAL(ctx);
691
}
692

    
693
static opc_handler_t invalid_handler = {
694
    .inval   = 0xFFFFFFFF,
695
    .type    = PPC_NONE,
696
    .handler = gen_invalid,
697
};
698

    
699
/***                           Integer arithmetic                          ***/
700
#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type)                 \
701
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
702
{                                                                             \
703
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
704
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
705
    gen_op_##name();                                                          \
706
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
707
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
708
        gen_set_Rc0(ctx);                                                     \
709
}
710

    
711
#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type)               \
712
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
713
{                                                                             \
714
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
715
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
716
    gen_op_##name();                                                          \
717
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
718
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
719
        gen_set_Rc0(ctx);                                                     \
720
}
721

    
722
#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                        \
723
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
724
{                                                                             \
725
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
726
    gen_op_##name();                                                          \
727
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
728
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
729
        gen_set_Rc0(ctx);                                                     \
730
}
731
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type)                      \
732
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
733
{                                                                             \
734
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
735
    gen_op_##name();                                                          \
736
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
737
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
738
        gen_set_Rc0(ctx);                                                     \
739
}
740

    
741
/* Two operands arithmetic functions */
742
#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type)                          \
743
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type)                    \
744
__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
745

    
746
/* Two operands arithmetic functions with no overflow allowed */
747
#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type)                          \
748
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
749

    
750
/* One operand arithmetic functions */
751
#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                          \
752
__GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                                \
753
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
754

    
755
#if defined(TARGET_PPC64)
756
#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type)              \
757
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
758
{                                                                             \
759
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
760
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
761
    if (ctx->sf_mode)                                                         \
762
        gen_op_##name##_64();                                                 \
763
    else                                                                      \
764
        gen_op_##name();                                                      \
765
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
766
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
767
        gen_set_Rc0(ctx);                                                     \
768
}
769

    
770
#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type)            \
771
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
772
{                                                                             \
773
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
774
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
775
    if (ctx->sf_mode)                                                         \
776
        gen_op_##name##_64();                                                 \
777
    else                                                                      \
778
        gen_op_##name();                                                      \
779
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
780
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
781
        gen_set_Rc0(ctx);                                                     \
782
}
783

    
784
#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                     \
785
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
786
{                                                                             \
787
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
788
    if (ctx->sf_mode)                                                         \
789
        gen_op_##name##_64();                                                 \
790
    else                                                                      \
791
        gen_op_##name();                                                      \
792
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
793
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
794
        gen_set_Rc0(ctx);                                                     \
795
}
796
#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type)                   \
797
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
798
{                                                                             \
799
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
800
    if (ctx->sf_mode)                                                         \
801
        gen_op_##name##_64();                                                 \
802
    else                                                                      \
803
        gen_op_##name();                                                      \
804
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
805
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
806
        gen_set_Rc0(ctx);                                                     \
807
}
808

    
809
/* Two operands arithmetic functions */
810
#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type)                       \
811
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type)                 \
812
__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
813

    
814
/* Two operands arithmetic functions with no overflow allowed */
815
#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type)                       \
816
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
817

    
818
/* One operand arithmetic functions */
819
#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                       \
820
__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                             \
821
__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
822
#else
823
#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
824
#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
825
#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
826
#endif
827

    
828
/* add    add.    addo    addo.    */
829
static always_inline void gen_op_addo (void)
830
{
831
    gen_op_move_T2_T0();
832
    gen_op_add();
833
    gen_op_check_addo();
834
}
835
#if defined(TARGET_PPC64)
836
#define gen_op_add_64 gen_op_add
837
static always_inline void gen_op_addo_64 (void)
838
{
839
    gen_op_move_T2_T0();
840
    gen_op_add();
841
    gen_op_check_addo_64();
842
}
843
#endif
844
GEN_INT_ARITH2_64 (add,    0x1F, 0x0A, 0x08, PPC_INTEGER);
845
/* addc   addc.   addco   addco.   */
846
static always_inline void gen_op_addc (void)
847
{
848
    gen_op_move_T2_T0();
849
    gen_op_add();
850
    gen_op_check_addc();
851
}
852
static always_inline void gen_op_addco (void)
853
{
854
    gen_op_move_T2_T0();
855
    gen_op_add();
856
    gen_op_check_addc();
857
    gen_op_check_addo();
858
}
859
#if defined(TARGET_PPC64)
860
static always_inline void gen_op_addc_64 (void)
861
{
862
    gen_op_move_T2_T0();
863
    gen_op_add();
864
    gen_op_check_addc_64();
865
}
866
static always_inline void gen_op_addco_64 (void)
867
{
868
    gen_op_move_T2_T0();
869
    gen_op_add();
870
    gen_op_check_addc_64();
871
    gen_op_check_addo_64();
872
}
873
#endif
874
GEN_INT_ARITH2_64 (addc,   0x1F, 0x0A, 0x00, PPC_INTEGER);
875
/* adde   adde.   addeo   addeo.   */
876
static always_inline void gen_op_addeo (void)
877
{
878
    gen_op_move_T2_T0();
879
    gen_op_adde();
880
    gen_op_check_addo();
881
}
882
#if defined(TARGET_PPC64)
883
static always_inline void gen_op_addeo_64 (void)
884
{
885
    gen_op_move_T2_T0();
886
    gen_op_adde_64();
887
    gen_op_check_addo_64();
888
}
889
#endif
890
GEN_INT_ARITH2_64 (adde,   0x1F, 0x0A, 0x04, PPC_INTEGER);
891
/* addme  addme.  addmeo  addmeo.  */
892
static always_inline void gen_op_addme (void)
893
{
894
    gen_op_move_T1_T0();
895
    gen_op_add_me();
896
}
897
#if defined(TARGET_PPC64)
898
static always_inline void gen_op_addme_64 (void)
899
{
900
    gen_op_move_T1_T0();
901
    gen_op_add_me_64();
902
}
903
#endif
904
GEN_INT_ARITH1_64 (addme,  0x1F, 0x0A, 0x07, PPC_INTEGER);
905
/* addze  addze.  addzeo  addzeo.  */
906
static always_inline void gen_op_addze (void)
907
{
908
    gen_op_move_T2_T0();
909
    gen_op_add_ze();
910
    gen_op_check_addc();
911
}
912
static always_inline void gen_op_addzeo (void)
913
{
914
    gen_op_move_T2_T0();
915
    gen_op_add_ze();
916
    gen_op_check_addc();
917
    gen_op_check_addo();
918
}
919
#if defined(TARGET_PPC64)
920
static always_inline void gen_op_addze_64 (void)
921
{
922
    gen_op_move_T2_T0();
923
    gen_op_add_ze();
924
    gen_op_check_addc_64();
925
}
926
static always_inline void gen_op_addzeo_64 (void)
927
{
928
    gen_op_move_T2_T0();
929
    gen_op_add_ze();
930
    gen_op_check_addc_64();
931
    gen_op_check_addo_64();
932
}
933
#endif
934
GEN_INT_ARITH1_64 (addze,  0x1F, 0x0A, 0x06, PPC_INTEGER);
935
/* divw   divw.   divwo   divwo.   */
936
GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F, PPC_INTEGER);
937
/* divwu  divwu.  divwuo  divwuo.  */
938
GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E, PPC_INTEGER);
939
/* mulhw  mulhw.                   */
940
GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02, PPC_INTEGER);
941
/* mulhwu mulhwu.                  */
942
GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
943
/* mullw  mullw.  mullwo  mullwo.  */
944
GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07, PPC_INTEGER);
945
/* neg    neg.    nego    nego.    */
946
GEN_INT_ARITH1_64 (neg,    0x1F, 0x08, 0x03, PPC_INTEGER);
947
/* subf   subf.   subfo   subfo.   */
948
static always_inline void gen_op_subfo (void)
949
{
950
    gen_op_moven_T2_T0();
951
    gen_op_subf();
952
    gen_op_check_addo();
953
}
954
#if defined(TARGET_PPC64)
955
#define gen_op_subf_64 gen_op_subf
956
static always_inline void gen_op_subfo_64 (void)
957
{
958
    gen_op_moven_T2_T0();
959
    gen_op_subf();
960
    gen_op_check_addo_64();
961
}
962
#endif
963
GEN_INT_ARITH2_64 (subf,   0x1F, 0x08, 0x01, PPC_INTEGER);
964
/* subfc  subfc.  subfco  subfco.  */
965
static always_inline void gen_op_subfc (void)
966
{
967
    gen_op_subf();
968
    gen_op_check_subfc();
969
}
970
static always_inline void gen_op_subfco (void)
971
{
972
    gen_op_moven_T2_T0();
973
    gen_op_subf();
974
    gen_op_check_subfc();
975
    gen_op_check_addo();
976
}
977
#if defined(TARGET_PPC64)
978
static always_inline void gen_op_subfc_64 (void)
979
{
980
    gen_op_subf();
981
    gen_op_check_subfc_64();
982
}
983
static always_inline void gen_op_subfco_64 (void)
984
{
985
    gen_op_moven_T2_T0();
986
    gen_op_subf();
987
    gen_op_check_subfc_64();
988
    gen_op_check_addo_64();
989
}
990
#endif
991
GEN_INT_ARITH2_64 (subfc,  0x1F, 0x08, 0x00, PPC_INTEGER);
992
/* subfe  subfe.  subfeo  subfeo.  */
993
static always_inline void gen_op_subfeo (void)
994
{
995
    gen_op_moven_T2_T0();
996
    gen_op_subfe();
997
    gen_op_check_addo();
998
}
999
#if defined(TARGET_PPC64)
1000
#define gen_op_subfe_64 gen_op_subfe
1001
static always_inline void gen_op_subfeo_64 (void)
1002
{
1003
    gen_op_moven_T2_T0();
1004
    gen_op_subfe_64();
1005
    gen_op_check_addo_64();
1006
}
1007
#endif
1008
GEN_INT_ARITH2_64 (subfe,  0x1F, 0x08, 0x04, PPC_INTEGER);
1009
/* subfme subfme. subfmeo subfmeo. */
1010
GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
1011
/* subfze subfze. subfzeo subfzeo. */
1012
GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
1013
/* addi */
1014
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1015
{
1016
    target_long simm = SIMM(ctx->opcode);
1017

    
1018
    if (rA(ctx->opcode) == 0) {
1019
        /* li case */
1020
        gen_set_T0(simm);
1021
    } else {
1022
        gen_op_load_gpr_T0(rA(ctx->opcode));
1023
        if (likely(simm != 0))
1024
            gen_op_addi(simm);
1025
    }
1026
    gen_op_store_T0_gpr(rD(ctx->opcode));
1027
}
1028
/* addic */
1029
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1030
{
1031
    target_long simm = SIMM(ctx->opcode);
1032

    
1033
    gen_op_load_gpr_T0(rA(ctx->opcode));
1034
    if (likely(simm != 0)) {
1035
        gen_op_move_T2_T0();
1036
        gen_op_addi(simm);
1037
#if defined(TARGET_PPC64)
1038
        if (ctx->sf_mode)
1039
            gen_op_check_addc_64();
1040
        else
1041
#endif
1042
            gen_op_check_addc();
1043
    } else {
1044
        gen_op_clear_xer_ca();
1045
    }
1046
    gen_op_store_T0_gpr(rD(ctx->opcode));
1047
}
1048
/* addic. */
1049
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1050
{
1051
    target_long simm = SIMM(ctx->opcode);
1052

    
1053
    gen_op_load_gpr_T0(rA(ctx->opcode));
1054
    if (likely(simm != 0)) {
1055
        gen_op_move_T2_T0();
1056
        gen_op_addi(simm);
1057
#if defined(TARGET_PPC64)
1058
        if (ctx->sf_mode)
1059
            gen_op_check_addc_64();
1060
        else
1061
#endif
1062
            gen_op_check_addc();
1063
    } else {
1064
        gen_op_clear_xer_ca();
1065
    }
1066
    gen_op_store_T0_gpr(rD(ctx->opcode));
1067
    gen_set_Rc0(ctx);
1068
}
1069
/* addis */
1070
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1071
{
1072
    target_long simm = SIMM(ctx->opcode);
1073

    
1074
    if (rA(ctx->opcode) == 0) {
1075
        /* lis case */
1076
        gen_set_T0(simm << 16);
1077
    } else {
1078
        gen_op_load_gpr_T0(rA(ctx->opcode));
1079
        if (likely(simm != 0))
1080
            gen_op_addi(simm << 16);
1081
    }
1082
    gen_op_store_T0_gpr(rD(ctx->opcode));
1083
}
1084
/* mulli */
1085
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1086
{
1087
    gen_op_load_gpr_T0(rA(ctx->opcode));
1088
    gen_op_mulli(SIMM(ctx->opcode));
1089
    gen_op_store_T0_gpr(rD(ctx->opcode));
1090
}
1091
/* subfic */
1092
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1093
{
1094
    gen_op_load_gpr_T0(rA(ctx->opcode));
1095
#if defined(TARGET_PPC64)
1096
    if (ctx->sf_mode)
1097
        gen_op_subfic_64(SIMM(ctx->opcode));
1098
    else
1099
#endif
1100
        gen_op_subfic(SIMM(ctx->opcode));
1101
    gen_op_store_T0_gpr(rD(ctx->opcode));
1102
}
1103

    
1104
#if defined(TARGET_PPC64)
1105
/* mulhd  mulhd.                   */
1106
GEN_INT_ARITHN (mulhd,  0x1F, 0x09, 0x02, PPC_64B);
1107
/* mulhdu mulhdu.                  */
1108
GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
1109
/* mulld  mulld.  mulldo  mulldo.  */
1110
GEN_INT_ARITH2 (mulld,  0x1F, 0x09, 0x07, PPC_64B);
1111
/* divd   divd.   divdo   divdo.   */
1112
GEN_INT_ARITH2 (divd,   0x1F, 0x09, 0x0F, PPC_64B);
1113
/* divdu  divdu.  divduo  divduo.  */
1114
GEN_INT_ARITH2 (divdu,  0x1F, 0x09, 0x0E, PPC_64B);
1115
#endif
1116

    
1117
/***                           Integer comparison                          ***/
1118
#if defined(TARGET_PPC64)
1119
#define GEN_CMP(name, opc, type)                                              \
1120
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1121
{                                                                             \
1122
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1123
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1124
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))                           \
1125
        gen_op_##name##_64();                                                 \
1126
    else                                                                      \
1127
        gen_op_##name();                                                      \
1128
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1129
}
1130
#else
1131
#define GEN_CMP(name, opc, type)                                              \
1132
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1133
{                                                                             \
1134
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1135
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1136
    gen_op_##name();                                                          \
1137
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1138
}
1139
#endif
1140

    
1141
/* cmp */
1142
GEN_CMP(cmp, 0x00, PPC_INTEGER);
1143
/* cmpi */
1144
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1145
{
1146
    gen_op_load_gpr_T0(rA(ctx->opcode));
1147
#if defined(TARGET_PPC64)
1148
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1149
        gen_op_cmpi_64(SIMM(ctx->opcode));
1150
    else
1151
#endif
1152
        gen_op_cmpi(SIMM(ctx->opcode));
1153
    gen_op_store_T0_crf(crfD(ctx->opcode));
1154
}
1155
/* cmpl */
1156
GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1157
/* cmpli */
1158
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1159
{
1160
    gen_op_load_gpr_T0(rA(ctx->opcode));
1161
#if defined(TARGET_PPC64)
1162
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1163
        gen_op_cmpli_64(UIMM(ctx->opcode));
1164
    else
1165
#endif
1166
        gen_op_cmpli(UIMM(ctx->opcode));
1167
    gen_op_store_T0_crf(crfD(ctx->opcode));
1168
}
1169

    
1170
/* isel (PowerPC 2.03 specification) */
1171
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
1172
{
1173
    uint32_t bi = rC(ctx->opcode);
1174
    uint32_t mask;
1175

    
1176
    if (rA(ctx->opcode) == 0) {
1177
        gen_set_T0(0);
1178
    } else {
1179
        gen_op_load_gpr_T1(rA(ctx->opcode));
1180
    }
1181
    gen_op_load_gpr_T2(rB(ctx->opcode));
1182
    mask = 1 << (3 - (bi & 0x03));
1183
    gen_op_load_crf_T0(bi >> 2);
1184
    gen_op_test_true(mask);
1185
    gen_op_isel();
1186
    gen_op_store_T0_gpr(rD(ctx->opcode));
1187
}
1188

    
1189
/***                            Integer logical                            ***/
1190
#define __GEN_LOGICAL2(name, opc2, opc3, type)                                \
1191
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type)                         \
1192
{                                                                             \
1193
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1194
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1195
    gen_op_##name();                                                          \
1196
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1197
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1198
        gen_set_Rc0(ctx);                                                     \
1199
}
1200
#define GEN_LOGICAL2(name, opc, type)                                         \
1201
__GEN_LOGICAL2(name, 0x1C, opc, type)
1202

    
1203
#define GEN_LOGICAL1(name, opc, type)                                         \
1204
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)                          \
1205
{                                                                             \
1206
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1207
    gen_op_##name();                                                          \
1208
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1209
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1210
        gen_set_Rc0(ctx);                                                     \
1211
}
1212

    
1213
/* and & and. */
1214
GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1215
/* andc & andc. */
1216
GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1217
/* andi. */
1218
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1219
{
1220
    gen_op_load_gpr_T0(rS(ctx->opcode));
1221
    gen_op_andi_T0(UIMM(ctx->opcode));
1222
    gen_op_store_T0_gpr(rA(ctx->opcode));
1223
    gen_set_Rc0(ctx);
1224
}
1225
/* andis. */
1226
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1227
{
1228
    gen_op_load_gpr_T0(rS(ctx->opcode));
1229
    gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1230
    gen_op_store_T0_gpr(rA(ctx->opcode));
1231
    gen_set_Rc0(ctx);
1232
}
1233

    
1234
/* cntlzw */
1235
GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1236
/* eqv & eqv. */
1237
GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1238
/* extsb & extsb. */
1239
GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1240
/* extsh & extsh. */
1241
GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1242
/* nand & nand. */
1243
GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1244
/* nor & nor. */
1245
GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1246

    
1247
/* or & or. */
1248
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1249
{
1250
    int rs, ra, rb;
1251

    
1252
    rs = rS(ctx->opcode);
1253
    ra = rA(ctx->opcode);
1254
    rb = rB(ctx->opcode);
1255
    /* Optimisation for mr. ri case */
1256
    if (rs != ra || rs != rb) {
1257
        gen_op_load_gpr_T0(rs);
1258
        if (rs != rb) {
1259
            gen_op_load_gpr_T1(rb);
1260
            gen_op_or();
1261
        }
1262
        gen_op_store_T0_gpr(ra);
1263
        if (unlikely(Rc(ctx->opcode) != 0))
1264
            gen_set_Rc0(ctx);
1265
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1266
        gen_op_load_gpr_T0(rs);
1267
        gen_set_Rc0(ctx);
1268
#if defined(TARGET_PPC64)
1269
    } else {
1270
        switch (rs) {
1271
        case 1:
1272
            /* Set process priority to low */
1273
            gen_op_store_pri(2);
1274
            break;
1275
        case 6:
1276
            /* Set process priority to medium-low */
1277
            gen_op_store_pri(3);
1278
            break;
1279
        case 2:
1280
            /* Set process priority to normal */
1281
            gen_op_store_pri(4);
1282
            break;
1283
#if !defined(CONFIG_USER_ONLY)
1284
        case 31:
1285
            if (ctx->supervisor > 0) {
1286
                /* Set process priority to very low */
1287
                gen_op_store_pri(1);
1288
            }
1289
            break;
1290
        case 5:
1291
            if (ctx->supervisor > 0) {
1292
                /* Set process priority to medium-hight */
1293
                gen_op_store_pri(5);
1294
            }
1295
            break;
1296
        case 3:
1297
            if (ctx->supervisor > 0) {
1298
                /* Set process priority to high */
1299
                gen_op_store_pri(6);
1300
            }
1301
            break;
1302
        case 7:
1303
            if (ctx->supervisor > 1) {
1304
                /* Set process priority to very high */
1305
                gen_op_store_pri(7);
1306
            }
1307
            break;
1308
#endif
1309
        default:
1310
            /* nop */
1311
            break;
1312
        }
1313
#endif
1314
    }
1315
}
1316

    
1317
/* orc & orc. */
1318
GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1319
/* xor & xor. */
1320
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1321
{
1322
    gen_op_load_gpr_T0(rS(ctx->opcode));
1323
    /* Optimisation for "set to zero" case */
1324
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
1325
        gen_op_load_gpr_T1(rB(ctx->opcode));
1326
        gen_op_xor();
1327
    } else {
1328
        tcg_gen_movi_tl(cpu_T[0], 0);
1329
    }
1330
    gen_op_store_T0_gpr(rA(ctx->opcode));
1331
    if (unlikely(Rc(ctx->opcode) != 0))
1332
        gen_set_Rc0(ctx);
1333
}
1334
/* ori */
1335
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1336
{
1337
    target_ulong uimm = UIMM(ctx->opcode);
1338

    
1339
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1340
        /* NOP */
1341
        /* XXX: should handle special NOPs for POWER series */
1342
        return;
1343
    }
1344
    gen_op_load_gpr_T0(rS(ctx->opcode));
1345
    if (likely(uimm != 0))
1346
        gen_op_ori(uimm);
1347
    gen_op_store_T0_gpr(rA(ctx->opcode));
1348
}
1349
/* oris */
1350
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1351
{
1352
    target_ulong uimm = UIMM(ctx->opcode);
1353

    
1354
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1355
        /* NOP */
1356
        return;
1357
    }
1358
    gen_op_load_gpr_T0(rS(ctx->opcode));
1359
    if (likely(uimm != 0))
1360
        gen_op_ori(uimm << 16);
1361
    gen_op_store_T0_gpr(rA(ctx->opcode));
1362
}
1363
/* xori */
1364
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1365
{
1366
    target_ulong uimm = UIMM(ctx->opcode);
1367

    
1368
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1369
        /* NOP */
1370
        return;
1371
    }
1372
    gen_op_load_gpr_T0(rS(ctx->opcode));
1373
    if (likely(uimm != 0))
1374
        gen_op_xori(uimm);
1375
    gen_op_store_T0_gpr(rA(ctx->opcode));
1376
}
1377

    
1378
/* xoris */
1379
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1380
{
1381
    target_ulong uimm = UIMM(ctx->opcode);
1382

    
1383
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1384
        /* NOP */
1385
        return;
1386
    }
1387
    gen_op_load_gpr_T0(rS(ctx->opcode));
1388
    if (likely(uimm != 0))
1389
        gen_op_xori(uimm << 16);
1390
    gen_op_store_T0_gpr(rA(ctx->opcode));
1391
}
1392

    
1393
/* popcntb : PowerPC 2.03 specification */
1394
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1395
{
1396
    gen_op_load_gpr_T0(rS(ctx->opcode));
1397
#if defined(TARGET_PPC64)
1398
    if (ctx->sf_mode)
1399
        tcg_gen_helper_1_1(do_popcntb_64, cpu_T[0], cpu_T[0]);
1400
    else
1401
#endif
1402
        tcg_gen_helper_1_1(do_popcntb, cpu_T[0], cpu_T[0]);
1403
    gen_op_store_T0_gpr(rA(ctx->opcode));
1404
}
1405

    
1406
#if defined(TARGET_PPC64)
1407
/* extsw & extsw. */
1408
GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1409
/* cntlzd */
1410
GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1411
#endif
1412

    
1413
/***                             Integer rotate                            ***/
1414
/* rlwimi & rlwimi. */
1415
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1416
{
1417
    target_ulong mask;
1418
    uint32_t mb, me, sh;
1419

    
1420
    mb = MB(ctx->opcode);
1421
    me = ME(ctx->opcode);
1422
    sh = SH(ctx->opcode);
1423
    if (likely(sh == 0)) {
1424
        if (likely(mb == 0 && me == 31)) {
1425
            gen_op_load_gpr_T0(rS(ctx->opcode));
1426
            goto do_store;
1427
        } else if (likely(mb == 31 && me == 0)) {
1428
            gen_op_load_gpr_T0(rA(ctx->opcode));
1429
            goto do_store;
1430
        }
1431
        gen_op_load_gpr_T0(rS(ctx->opcode));
1432
        gen_op_load_gpr_T1(rA(ctx->opcode));
1433
        goto do_mask;
1434
    }
1435
    gen_op_load_gpr_T0(rS(ctx->opcode));
1436
    gen_op_load_gpr_T1(rA(ctx->opcode));
1437
    gen_op_rotli32_T0(SH(ctx->opcode));
1438
 do_mask:
1439
#if defined(TARGET_PPC64)
1440
    mb += 32;
1441
    me += 32;
1442
#endif
1443
    mask = MASK(mb, me);
1444
    gen_op_andi_T0(mask);
1445
    gen_op_andi_T1(~mask);
1446
    gen_op_or();
1447
 do_store:
1448
    gen_op_store_T0_gpr(rA(ctx->opcode));
1449
    if (unlikely(Rc(ctx->opcode) != 0))
1450
        gen_set_Rc0(ctx);
1451
}
1452
/* rlwinm & rlwinm. */
1453
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1454
{
1455
    uint32_t mb, me, sh;
1456

    
1457
    sh = SH(ctx->opcode);
1458
    mb = MB(ctx->opcode);
1459
    me = ME(ctx->opcode);
1460
    gen_op_load_gpr_T0(rS(ctx->opcode));
1461
    if (likely(sh == 0)) {
1462
        goto do_mask;
1463
    }
1464
    if (likely(mb == 0)) {
1465
        if (likely(me == 31)) {
1466
            gen_op_rotli32_T0(sh);
1467
            goto do_store;
1468
        } else if (likely(me == (31 - sh))) {
1469
            gen_op_sli_T0(sh);
1470
            goto do_store;
1471
        }
1472
    } else if (likely(me == 31)) {
1473
        if (likely(sh == (32 - mb))) {
1474
            gen_op_srli_T0(mb);
1475
            goto do_store;
1476
        }
1477
    }
1478
    gen_op_rotli32_T0(sh);
1479
 do_mask:
1480
#if defined(TARGET_PPC64)
1481
    mb += 32;
1482
    me += 32;
1483
#endif
1484
    gen_op_andi_T0(MASK(mb, me));
1485
 do_store:
1486
    gen_op_store_T0_gpr(rA(ctx->opcode));
1487
    if (unlikely(Rc(ctx->opcode) != 0))
1488
        gen_set_Rc0(ctx);
1489
}
1490
/* rlwnm & rlwnm. */
1491
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1492
{
1493
    uint32_t mb, me;
1494

    
1495
    mb = MB(ctx->opcode);
1496
    me = ME(ctx->opcode);
1497
    gen_op_load_gpr_T0(rS(ctx->opcode));
1498
    gen_op_load_gpr_T1(rB(ctx->opcode));
1499
    gen_op_rotl32_T0_T1();
1500
    if (unlikely(mb != 0 || me != 31)) {
1501
#if defined(TARGET_PPC64)
1502
        mb += 32;
1503
        me += 32;
1504
#endif
1505
        gen_op_andi_T0(MASK(mb, me));
1506
    }
1507
    gen_op_store_T0_gpr(rA(ctx->opcode));
1508
    if (unlikely(Rc(ctx->opcode) != 0))
1509
        gen_set_Rc0(ctx);
1510
}
1511

    
1512
#if defined(TARGET_PPC64)
1513
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1514
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1515
{                                                                             \
1516
    gen_##name(ctx, 0);                                                       \
1517
}                                                                             \
1518
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1519
             PPC_64B)                                                         \
1520
{                                                                             \
1521
    gen_##name(ctx, 1);                                                       \
1522
}
1523
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1524
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1525
{                                                                             \
1526
    gen_##name(ctx, 0, 0);                                                    \
1527
}                                                                             \
1528
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
1529
             PPC_64B)                                                         \
1530
{                                                                             \
1531
    gen_##name(ctx, 0, 1);                                                    \
1532
}                                                                             \
1533
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1534
             PPC_64B)                                                         \
1535
{                                                                             \
1536
    gen_##name(ctx, 1, 0);                                                    \
1537
}                                                                             \
1538
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
1539
             PPC_64B)                                                         \
1540
{                                                                             \
1541
    gen_##name(ctx, 1, 1);                                                    \
1542
}
1543

    
1544
static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1545
{
1546
    if (mask >> 32)
1547
        gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1548
    else
1549
        gen_op_andi_T0(mask);
1550
}
1551

    
1552
static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1553
{
1554
    if (mask >> 32)
1555
        gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1556
    else
1557
        gen_op_andi_T1(mask);
1558
}
1559

    
1560
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1561
                                      uint32_t me, uint32_t sh)
1562
{
1563
    gen_op_load_gpr_T0(rS(ctx->opcode));
1564
    if (likely(sh == 0)) {
1565
        goto do_mask;
1566
    }
1567
    if (likely(mb == 0)) {
1568
        if (likely(me == 63)) {
1569
            gen_op_rotli64_T0(sh);
1570
            goto do_store;
1571
        } else if (likely(me == (63 - sh))) {
1572
            gen_op_sli_T0(sh);
1573
            goto do_store;
1574
        }
1575
    } else if (likely(me == 63)) {
1576
        if (likely(sh == (64 - mb))) {
1577
            gen_op_srli_T0_64(mb);
1578
            goto do_store;
1579
        }
1580
    }
1581
    gen_op_rotli64_T0(sh);
1582
 do_mask:
1583
    gen_andi_T0_64(ctx, MASK(mb, me));
1584
 do_store:
1585
    gen_op_store_T0_gpr(rA(ctx->opcode));
1586
    if (unlikely(Rc(ctx->opcode) != 0))
1587
        gen_set_Rc0(ctx);
1588
}
1589
/* rldicl - rldicl. */
1590
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1591
{
1592
    uint32_t sh, mb;
1593

    
1594
    sh = SH(ctx->opcode) | (shn << 5);
1595
    mb = MB(ctx->opcode) | (mbn << 5);
1596
    gen_rldinm(ctx, mb, 63, sh);
1597
}
1598
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1599
/* rldicr - rldicr. */
1600
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1601
{
1602
    uint32_t sh, me;
1603

    
1604
    sh = SH(ctx->opcode) | (shn << 5);
1605
    me = MB(ctx->opcode) | (men << 5);
1606
    gen_rldinm(ctx, 0, me, sh);
1607
}
1608
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1609
/* rldic - rldic. */
1610
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1611
{
1612
    uint32_t sh, mb;
1613

    
1614
    sh = SH(ctx->opcode) | (shn << 5);
1615
    mb = MB(ctx->opcode) | (mbn << 5);
1616
    gen_rldinm(ctx, mb, 63 - sh, sh);
1617
}
1618
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1619

    
1620
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1621
                                     uint32_t me)
1622
{
1623
    gen_op_load_gpr_T0(rS(ctx->opcode));
1624
    gen_op_load_gpr_T1(rB(ctx->opcode));
1625
    gen_op_rotl64_T0_T1();
1626
    if (unlikely(mb != 0 || me != 63)) {
1627
        gen_andi_T0_64(ctx, MASK(mb, me));
1628
    }
1629
    gen_op_store_T0_gpr(rA(ctx->opcode));
1630
    if (unlikely(Rc(ctx->opcode) != 0))
1631
        gen_set_Rc0(ctx);
1632
}
1633

    
1634
/* rldcl - rldcl. */
1635
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1636
{
1637
    uint32_t mb;
1638

    
1639
    mb = MB(ctx->opcode) | (mbn << 5);
1640
    gen_rldnm(ctx, mb, 63);
1641
}
1642
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1643
/* rldcr - rldcr. */
1644
static always_inline void gen_rldcr (DisasContext *ctx, int men)
1645
{
1646
    uint32_t me;
1647

    
1648
    me = MB(ctx->opcode) | (men << 5);
1649
    gen_rldnm(ctx, 0, me);
1650
}
1651
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1652
/* rldimi - rldimi. */
1653
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1654
{
1655
    uint64_t mask;
1656
    uint32_t sh, mb, me;
1657

    
1658
    sh = SH(ctx->opcode) | (shn << 5);
1659
    mb = MB(ctx->opcode) | (mbn << 5);
1660
    me = 63 - sh;
1661
    if (likely(sh == 0)) {
1662
        if (likely(mb == 0)) {
1663
            gen_op_load_gpr_T0(rS(ctx->opcode));
1664
            goto do_store;
1665
        }
1666
        gen_op_load_gpr_T0(rS(ctx->opcode));
1667
        gen_op_load_gpr_T1(rA(ctx->opcode));
1668
        goto do_mask;
1669
    }
1670
    gen_op_load_gpr_T0(rS(ctx->opcode));
1671
    gen_op_load_gpr_T1(rA(ctx->opcode));
1672
    gen_op_rotli64_T0(sh);
1673
 do_mask:
1674
    mask = MASK(mb, me);
1675
    gen_andi_T0_64(ctx, mask);
1676
    gen_andi_T1_64(ctx, ~mask);
1677
    gen_op_or();
1678
 do_store:
1679
    gen_op_store_T0_gpr(rA(ctx->opcode));
1680
    if (unlikely(Rc(ctx->opcode) != 0))
1681
        gen_set_Rc0(ctx);
1682
}
1683
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1684
#endif
1685

    
1686
/***                             Integer shift                             ***/
1687
/* slw & slw. */
1688
__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1689
/* sraw & sraw. */
1690
__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1691
/* srawi & srawi. */
1692
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1693
{
1694
    int mb, me;
1695
    gen_op_load_gpr_T0(rS(ctx->opcode));
1696
    if (SH(ctx->opcode) != 0) {
1697
        gen_op_move_T1_T0();
1698
        mb = 32 - SH(ctx->opcode);
1699
        me = 31;
1700
#if defined(TARGET_PPC64)
1701
        mb += 32;
1702
        me += 32;
1703
#endif
1704
        gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1705
    }
1706
    gen_op_store_T0_gpr(rA(ctx->opcode));
1707
    if (unlikely(Rc(ctx->opcode) != 0))
1708
        gen_set_Rc0(ctx);
1709
}
1710
/* srw & srw. */
1711
__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1712

    
1713
#if defined(TARGET_PPC64)
1714
/* sld & sld. */
1715
__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1716
/* srad & srad. */
1717
__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1718
/* sradi & sradi. */
1719
static always_inline void gen_sradi (DisasContext *ctx, int n)
1720
{
1721
    uint64_t mask;
1722
    int sh, mb, me;
1723

    
1724
    gen_op_load_gpr_T0(rS(ctx->opcode));
1725
    sh = SH(ctx->opcode) + (n << 5);
1726
    if (sh != 0) {
1727
        gen_op_move_T1_T0();
1728
        mb = 64 - SH(ctx->opcode);
1729
        me = 63;
1730
        mask = MASK(mb, me);
1731
        gen_op_sradi(sh, mask >> 32, mask);
1732
    }
1733
    gen_op_store_T0_gpr(rA(ctx->opcode));
1734
    if (unlikely(Rc(ctx->opcode) != 0))
1735
        gen_set_Rc0(ctx);
1736
}
1737
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1738
{
1739
    gen_sradi(ctx, 0);
1740
}
1741
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1742
{
1743
    gen_sradi(ctx, 1);
1744
}
1745
/* srd & srd. */
1746
__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1747
#endif
1748

    
1749
/***                       Floating-Point arithmetic                       ***/
1750
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
1751
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \
1752
{                                                                             \
1753
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1754
        GEN_EXCP_NO_FP(ctx);                                                  \
1755
        return;                                                               \
1756
    }                                                                         \
1757
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1758
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1759
    gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \
1760
    gen_reset_fpstatus();                                                     \
1761
    gen_op_f##op();                                                           \
1762
    if (isfloat) {                                                            \
1763
        gen_op_frsp();                                                        \
1764
    }                                                                         \
1765
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1766
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1767
}
1768

    
1769
#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
1770
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
1771
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1772

    
1773
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1774
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
1775
{                                                                             \
1776
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1777
        GEN_EXCP_NO_FP(ctx);                                                  \
1778
        return;                                                               \
1779
    }                                                                         \
1780
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1781
    gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \
1782
    gen_reset_fpstatus();                                                     \
1783
    gen_op_f##op();                                                           \
1784
    if (isfloat) {                                                            \
1785
        gen_op_frsp();                                                        \
1786
    }                                                                         \
1787
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1788
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1789
}
1790
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
1791
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
1792
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1793

    
1794
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1795
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
1796
{                                                                             \
1797
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1798
        GEN_EXCP_NO_FP(ctx);                                                  \
1799
        return;                                                               \
1800
    }                                                                         \
1801
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1802
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1803
    gen_reset_fpstatus();                                                     \
1804
    gen_op_f##op();                                                           \
1805
    if (isfloat) {                                                            \
1806
        gen_op_frsp();                                                        \
1807
    }                                                                         \
1808
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1809
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1810
}
1811
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
1812
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
1813
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1814

    
1815
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
1816
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \
1817
{                                                                             \
1818
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1819
        GEN_EXCP_NO_FP(ctx);                                                  \
1820
        return;                                                               \
1821
    }                                                                         \
1822
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1823
    gen_reset_fpstatus();                                                     \
1824
    gen_op_f##name();                                                         \
1825
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1826
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1827
}
1828

    
1829
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
1830
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \
1831
{                                                                             \
1832
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1833
        GEN_EXCP_NO_FP(ctx);                                                  \
1834
        return;                                                               \
1835
    }                                                                         \
1836
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1837
    gen_reset_fpstatus();                                                     \
1838
    gen_op_f##name();                                                         \
1839
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1840
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1841
}
1842

    
1843
/* fadd - fadds */
1844
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1845
/* fdiv - fdivs */
1846
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
1847
/* fmul - fmuls */
1848
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
1849

    
1850
/* fre */
1851
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
1852

    
1853
/* fres */
1854
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
1855

    
1856
/* frsqrte */
1857
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1858

    
1859
/* frsqrtes */
1860
static always_inline void gen_op_frsqrtes (void)
1861
{
1862
    gen_op_frsqrte();
1863
    gen_op_frsp();
1864
}
1865
GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
1866

    
1867
/* fsel */
1868
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
1869
/* fsub - fsubs */
1870
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
1871
/* Optional: */
1872
/* fsqrt */
1873
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1874
{
1875
    if (unlikely(!ctx->fpu_enabled)) {
1876
        GEN_EXCP_NO_FP(ctx);
1877
        return;
1878
    }
1879
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1880
    gen_reset_fpstatus();
1881
    gen_op_fsqrt();
1882
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1883
    gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1884
}
1885

    
1886
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1887
{
1888
    if (unlikely(!ctx->fpu_enabled)) {
1889
        GEN_EXCP_NO_FP(ctx);
1890
        return;
1891
    }
1892
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1893
    gen_reset_fpstatus();
1894
    gen_op_fsqrt();
1895
    gen_op_frsp();
1896
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1897
    gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1898
}
1899

    
1900
/***                     Floating-Point multiply-and-add                   ***/
1901
/* fmadd - fmadds */
1902
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
1903
/* fmsub - fmsubs */
1904
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
1905
/* fnmadd - fnmadds */
1906
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
1907
/* fnmsub - fnmsubs */
1908
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
1909

    
1910
/***                     Floating-Point round & convert                    ***/
1911
/* fctiw */
1912
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
1913
/* fctiwz */
1914
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
1915
/* frsp */
1916
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
1917
#if defined(TARGET_PPC64)
1918
/* fcfid */
1919
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
1920
/* fctid */
1921
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
1922
/* fctidz */
1923
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
1924
#endif
1925

    
1926
/* frin */
1927
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
1928
/* friz */
1929
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
1930
/* frip */
1931
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
1932
/* frim */
1933
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
1934

    
1935
/***                         Floating-Point compare                        ***/
1936
/* fcmpo */
1937
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1938
{
1939
    if (unlikely(!ctx->fpu_enabled)) {
1940
        GEN_EXCP_NO_FP(ctx);
1941
        return;
1942
    }
1943
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1944
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1945
    gen_reset_fpstatus();
1946
    gen_op_fcmpo();
1947
    gen_op_store_T0_crf(crfD(ctx->opcode));
1948
    gen_op_float_check_status();
1949
}
1950

    
1951
/* fcmpu */
1952
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1953
{
1954
    if (unlikely(!ctx->fpu_enabled)) {
1955
        GEN_EXCP_NO_FP(ctx);
1956
        return;
1957
    }
1958
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1959
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1960
    gen_reset_fpstatus();
1961
    gen_op_fcmpu();
1962
    gen_op_store_T0_crf(crfD(ctx->opcode));
1963
    gen_op_float_check_status();
1964
}
1965

    
1966
/***                         Floating-point move                           ***/
1967
/* fabs */
1968
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1969
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
1970

    
1971
/* fmr  - fmr. */
1972
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1973
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1974
{
1975
    if (unlikely(!ctx->fpu_enabled)) {
1976
        GEN_EXCP_NO_FP(ctx);
1977
        return;
1978
    }
1979
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1980
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1981
    gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1982
}
1983

    
1984
/* fnabs */
1985
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1986
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
1987
/* fneg */
1988
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1989
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
1990

    
1991
/***                  Floating-Point status & ctrl register                ***/
1992
/* mcrfs */
1993
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1994
{
1995
    int bfa;
1996

    
1997
    if (unlikely(!ctx->fpu_enabled)) {
1998
        GEN_EXCP_NO_FP(ctx);
1999
        return;
2000
    }
2001
    gen_optimize_fprf();
2002
    bfa = 4 * (7 - crfS(ctx->opcode));
2003
    gen_op_load_fpscr_T0(bfa);
2004
    gen_op_store_T0_crf(crfD(ctx->opcode));
2005
    gen_op_fpscr_resetbit(~(0xF << bfa));
2006
}
2007

    
2008
/* mffs */
2009
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2010
{
2011
    if (unlikely(!ctx->fpu_enabled)) {
2012
        GEN_EXCP_NO_FP(ctx);
2013
        return;
2014
    }
2015
    gen_optimize_fprf();
2016
    gen_reset_fpstatus();
2017
    gen_op_load_fpscr_FT0();
2018
    gen_op_store_FT0_fpr(rD(ctx->opcode));
2019
    gen_compute_fprf(0, Rc(ctx->opcode) != 0);
2020
}
2021

    
2022
/* mtfsb0 */
2023
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2024
{
2025
    uint8_t crb;
2026

    
2027
    if (unlikely(!ctx->fpu_enabled)) {
2028
        GEN_EXCP_NO_FP(ctx);
2029
        return;
2030
    }
2031
    crb = 32 - (crbD(ctx->opcode) >> 2);
2032
    gen_optimize_fprf();
2033
    gen_reset_fpstatus();
2034
    if (likely(crb != 30 && crb != 29))
2035
        gen_op_fpscr_resetbit(~(1 << crb));
2036
    if (unlikely(Rc(ctx->opcode) != 0)) {
2037
        gen_op_load_fpcc();
2038
        gen_op_set_Rc0();
2039
    }
2040
}
2041

    
2042
/* mtfsb1 */
2043
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2044
{
2045
    uint8_t crb;
2046

    
2047
    if (unlikely(!ctx->fpu_enabled)) {
2048
        GEN_EXCP_NO_FP(ctx);
2049
        return;
2050
    }
2051
    crb = 32 - (crbD(ctx->opcode) >> 2);
2052
    gen_optimize_fprf();
2053
    gen_reset_fpstatus();
2054
    /* XXX: we pretend we can only do IEEE floating-point computations */
2055
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2056
        gen_op_fpscr_setbit(crb);
2057
    if (unlikely(Rc(ctx->opcode) != 0)) {
2058
        gen_op_load_fpcc();
2059
        gen_op_set_Rc0();
2060
    }
2061
    /* We can raise a differed exception */
2062
    gen_op_float_check_status();
2063
}
2064

    
2065
/* mtfsf */
2066
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2067
{
2068
    if (unlikely(!ctx->fpu_enabled)) {
2069
        GEN_EXCP_NO_FP(ctx);
2070
        return;
2071
    }
2072
    gen_optimize_fprf();
2073
    gen_op_load_fpr_FT0(rB(ctx->opcode));
2074
    gen_reset_fpstatus();
2075
    gen_op_store_fpscr(FM(ctx->opcode));
2076
    if (unlikely(Rc(ctx->opcode) != 0)) {
2077
        gen_op_load_fpcc();
2078
        gen_op_set_Rc0();
2079
    }
2080
    /* We can raise a differed exception */
2081
    gen_op_float_check_status();
2082
}
2083

    
2084
/* mtfsfi */
2085
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2086
{
2087
    int bf, sh;
2088

    
2089
    if (unlikely(!ctx->fpu_enabled)) {
2090
        GEN_EXCP_NO_FP(ctx);
2091
        return;
2092
    }
2093
    bf = crbD(ctx->opcode) >> 2;
2094
    sh = 7 - bf;
2095
    gen_optimize_fprf();
2096
    gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2097
    gen_reset_fpstatus();
2098
    gen_op_store_fpscr(1 << sh);
2099
    if (unlikely(Rc(ctx->opcode) != 0)) {
2100
        gen_op_load_fpcc();
2101
        gen_op_set_Rc0();
2102
    }
2103
    /* We can raise a differed exception */
2104
    gen_op_float_check_status();
2105
}
2106

    
2107
/***                           Addressing modes                            ***/
2108
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2109
static always_inline void gen_addr_imm_index (DisasContext *ctx,
2110
                                              target_long maskl)
2111
{
2112
    target_long simm = SIMM(ctx->opcode);
2113

    
2114
    simm &= ~maskl;
2115
    if (rA(ctx->opcode) == 0) {
2116
        gen_set_T0(simm);
2117
    } else {
2118
        gen_op_load_gpr_T0(rA(ctx->opcode));
2119
        if (likely(simm != 0))
2120
            gen_op_addi(simm);
2121
    }
2122
#ifdef DEBUG_MEMORY_ACCESSES
2123
    tcg_gen_helper_0_0(do_print_mem_EA);
2124
#endif
2125
}
2126

    
2127
static always_inline void gen_addr_reg_index (DisasContext *ctx)
2128
{
2129
    if (rA(ctx->opcode) == 0) {
2130
        gen_op_load_gpr_T0(rB(ctx->opcode));
2131
    } else {
2132
        gen_op_load_gpr_T0(rA(ctx->opcode));
2133
        gen_op_load_gpr_T1(rB(ctx->opcode));
2134
        gen_op_add();
2135
    }
2136
#ifdef DEBUG_MEMORY_ACCESSES
2137
    tcg_gen_helper_0_0(do_print_mem_EA);
2138
#endif
2139
}
2140

    
2141
static always_inline void gen_addr_register (DisasContext *ctx)
2142
{
2143
    if (rA(ctx->opcode) == 0) {
2144
        tcg_gen_movi_tl(cpu_T[0], 0);
2145
    } else {
2146
        gen_op_load_gpr_T0(rA(ctx->opcode));
2147
    }
2148
#ifdef DEBUG_MEMORY_ACCESSES
2149
    tcg_gen_helper_0_0(do_print_mem_EA);
2150
#endif
2151
}
2152

    
2153
#if defined(TARGET_PPC64)
2154
#define _GEN_MEM_FUNCS(name, mode)                                            \
2155
    &gen_op_##name##_##mode,                                                  \
2156
    &gen_op_##name##_le_##mode,                                               \
2157
    &gen_op_##name##_64_##mode,                                               \
2158
    &gen_op_##name##_le_64_##mode
2159
#else
2160
#define _GEN_MEM_FUNCS(name, mode)                                            \
2161
    &gen_op_##name##_##mode,                                                  \
2162
    &gen_op_##name##_le_##mode
2163
#endif
2164
#if defined(CONFIG_USER_ONLY)
2165
#if defined(TARGET_PPC64)
2166
#define NB_MEM_FUNCS 4
2167
#else
2168
#define NB_MEM_FUNCS 2
2169
#endif
2170
#define GEN_MEM_FUNCS(name)                                                   \
2171
    _GEN_MEM_FUNCS(name, raw)
2172
#else
2173
#if defined(TARGET_PPC64)
2174
#define NB_MEM_FUNCS 12
2175
#else
2176
#define NB_MEM_FUNCS 6
2177
#endif
2178
#define GEN_MEM_FUNCS(name)                                                   \
2179
    _GEN_MEM_FUNCS(name, user),                                               \
2180
    _GEN_MEM_FUNCS(name, kernel),                                             \
2181
    _GEN_MEM_FUNCS(name, hypv)
2182
#endif
2183

    
2184
/***                             Integer load                              ***/
2185
#define op_ldst(name)        (*gen_op_##name[ctx->mem_idx])()
2186
/* Byte access routine are endian safe */
2187
#define gen_op_lbz_le_raw       gen_op_lbz_raw
2188
#define gen_op_lbz_le_user      gen_op_lbz_user
2189
#define gen_op_lbz_le_kernel    gen_op_lbz_kernel
2190
#define gen_op_lbz_le_hypv      gen_op_lbz_hypv
2191
#define gen_op_lbz_le_64_raw    gen_op_lbz_64_raw
2192
#define gen_op_lbz_le_64_user   gen_op_lbz_64_user
2193
#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2194
#define gen_op_lbz_le_64_hypv   gen_op_lbz_64_hypv
2195
#define gen_op_stb_le_raw       gen_op_stb_raw
2196
#define gen_op_stb_le_user      gen_op_stb_user
2197
#define gen_op_stb_le_kernel    gen_op_stb_kernel
2198
#define gen_op_stb_le_hypv      gen_op_stb_hypv
2199
#define gen_op_stb_le_64_raw    gen_op_stb_64_raw
2200
#define gen_op_stb_le_64_user   gen_op_stb_64_user
2201
#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2202
#define gen_op_stb_le_64_hypv   gen_op_stb_64_hypv
2203
#define OP_LD_TABLE(width)                                                    \
2204
static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = {                           \
2205
    GEN_MEM_FUNCS(l##width),                                                  \
2206
};
2207
#define OP_ST_TABLE(width)                                                    \
2208
static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = {                          \
2209
    GEN_MEM_FUNCS(st##width),                                                 \
2210
};
2211

    
2212
#define GEN_LD(width, opc, type)                                              \
2213
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2214
{                                                                             \
2215
    gen_addr_imm_index(ctx, 0);                                               \
2216
    op_ldst(l##width);                                                        \
2217
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2218
}
2219

    
2220
#define GEN_LDU(width, opc, type)                                             \
2221
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2222
{                                                                             \
2223
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2224
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2225
        GEN_EXCP_INVAL(ctx);                                                  \
2226
        return;                                                               \
2227
    }                                                                         \
2228
    if (type == PPC_64B)                                                      \
2229
        gen_addr_imm_index(ctx, 0x03);                                        \
2230
    else                                                                      \
2231
        gen_addr_imm_index(ctx, 0);                                           \
2232
    op_ldst(l##width);                                                        \
2233
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2234
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2235
}
2236

    
2237
#define GEN_LDUX(width, opc2, opc3, type)                                     \
2238
GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                 \
2239
{                                                                             \
2240
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2241
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2242
        GEN_EXCP_INVAL(ctx);                                                  \
2243
        return;                                                               \
2244
    }                                                                         \
2245
    gen_addr_reg_index(ctx);                                                  \
2246
    op_ldst(l##width);                                                        \
2247
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2248
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2249
}
2250

    
2251
#define GEN_LDX(width, opc2, opc3, type)                                      \
2252
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2253
{                                                                             \
2254
    gen_addr_reg_index(ctx);                                                  \
2255
    op_ldst(l##width);                                                        \
2256
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2257
}
2258

    
2259
#define GEN_LDS(width, op, type)                                              \
2260
OP_LD_TABLE(width);                                                           \
2261
GEN_LD(width, op | 0x20, type);                                               \
2262
GEN_LDU(width, op | 0x21, type);                                              \
2263
GEN_LDUX(width, 0x17, op | 0x01, type);                                       \
2264
GEN_LDX(width, 0x17, op | 0x00, type)
2265

    
2266
/* lbz lbzu lbzux lbzx */
2267
GEN_LDS(bz, 0x02, PPC_INTEGER);
2268
/* lha lhau lhaux lhax */
2269
GEN_LDS(ha, 0x0A, PPC_INTEGER);
2270
/* lhz lhzu lhzux lhzx */
2271
GEN_LDS(hz, 0x08, PPC_INTEGER);
2272
/* lwz lwzu lwzux lwzx */
2273
GEN_LDS(wz, 0x00, PPC_INTEGER);
2274
#if defined(TARGET_PPC64)
2275
OP_LD_TABLE(wa);
2276
OP_LD_TABLE(d);
2277
/* lwaux */
2278
GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2279
/* lwax */
2280
GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2281
/* ldux */
2282
GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2283
/* ldx */
2284
GEN_LDX(d, 0x15, 0x00, PPC_64B);
2285
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2286
{
2287
    if (Rc(ctx->opcode)) {
2288
        if (unlikely(rA(ctx->opcode) == 0 ||
2289
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2290
            GEN_EXCP_INVAL(ctx);
2291
            return;
2292
        }
2293
    }
2294
    gen_addr_imm_index(ctx, 0x03);
2295
    if (ctx->opcode & 0x02) {
2296
        /* lwa (lwau is undefined) */
2297
        op_ldst(lwa);
2298
    } else {
2299
        /* ld - ldu */
2300
        op_ldst(ld);
2301
    }
2302
    gen_op_store_T1_gpr(rD(ctx->opcode));
2303
    if (Rc(ctx->opcode))
2304
        gen_op_store_T0_gpr(rA(ctx->opcode));
2305
}
2306
/* lq */
2307
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2308
{
2309
#if defined(CONFIG_USER_ONLY)
2310
    GEN_EXCP_PRIVOPC(ctx);
2311
#else
2312
    int ra, rd;
2313

    
2314
    /* Restore CPU state */
2315
    if (unlikely(ctx->supervisor == 0)) {
2316
        GEN_EXCP_PRIVOPC(ctx);
2317
        return;
2318
    }
2319
    ra = rA(ctx->opcode);
2320
    rd = rD(ctx->opcode);
2321
    if (unlikely((rd & 1) || rd == ra)) {
2322
        GEN_EXCP_INVAL(ctx);
2323
        return;
2324
    }
2325
    if (unlikely(ctx->mem_idx & 1)) {
2326
        /* Little-endian mode is not handled */
2327
        GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2328
        return;
2329
    }
2330
    gen_addr_imm_index(ctx, 0x0F);
2331
    op_ldst(ld);
2332
    gen_op_store_T1_gpr(rd);
2333
    gen_op_addi(8);
2334
    op_ldst(ld);
2335
    gen_op_store_T1_gpr(rd + 1);
2336
#endif
2337
}
2338
#endif
2339

    
2340
/***                              Integer store                            ***/
2341
#define GEN_ST(width, opc, type)                                              \
2342
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
2343
{                                                                             \
2344
    gen_addr_imm_index(ctx, 0);                                               \
2345
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2346
    op_ldst(st##width);                                                       \
2347
}
2348

    
2349
#define GEN_STU(width, opc, type)                                             \
2350
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
2351
{                                                                             \
2352
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2353
        GEN_EXCP_INVAL(ctx);                                                  \
2354
        return;                                                               \
2355
    }                                                                         \
2356
    if (type == PPC_64B)                                                      \
2357
        gen_addr_imm_index(ctx, 0x03);                                        \
2358
    else                                                                      \
2359
        gen_addr_imm_index(ctx, 0);                                           \
2360
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2361
    op_ldst(st##width);                                                       \
2362
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2363
}
2364

    
2365
#define GEN_STUX(width, opc2, opc3, type)                                     \
2366
GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                \
2367
{                                                                             \
2368
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2369
        GEN_EXCP_INVAL(ctx);                                                  \
2370
        return;                                                               \
2371
    }                                                                         \
2372
    gen_addr_reg_index(ctx);                                                  \
2373
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2374
    op_ldst(st##width);                                                       \
2375
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2376
}
2377

    
2378
#define GEN_STX(width, opc2, opc3, type)                                      \
2379
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
2380
{                                                                             \
2381
    gen_addr_reg_index(ctx);                                                  \
2382
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2383
    op_ldst(st##width);                                                       \
2384
}
2385

    
2386
#define GEN_STS(width, op, type)                                              \
2387
OP_ST_TABLE(width);                                                           \
2388
GEN_ST(width, op | 0x20, type);                                               \
2389
GEN_STU(width, op | 0x21, type);                                              \
2390
GEN_STUX(width, 0x17, op | 0x01, type);                                       \
2391
GEN_STX(width, 0x17, op | 0x00, type)
2392

    
2393
/* stb stbu stbux stbx */
2394
GEN_STS(b, 0x06, PPC_INTEGER);
2395
/* sth sthu sthux sthx */
2396
GEN_STS(h, 0x0C, PPC_INTEGER);
2397
/* stw stwu stwux stwx */
2398
GEN_STS(w, 0x04, PPC_INTEGER);
2399
#if defined(TARGET_PPC64)
2400
OP_ST_TABLE(d);
2401
GEN_STUX(d, 0x15, 0x05, PPC_64B);
2402
GEN_STX(d, 0x15, 0x04, PPC_64B);
2403
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2404
{
2405
    int rs;
2406

    
2407
    rs = rS(ctx->opcode);
2408
    if ((ctx->opcode & 0x3) == 0x2) {
2409
#if defined(CONFIG_USER_ONLY)
2410
        GEN_EXCP_PRIVOPC(ctx);
2411
#else
2412
        /* stq */
2413
        if (unlikely(ctx->supervisor == 0)) {
2414
            GEN_EXCP_PRIVOPC(ctx);
2415
            return;
2416
        }
2417
        if (unlikely(rs & 1)) {
2418
            GEN_EXCP_INVAL(ctx);
2419
            return;
2420
        }
2421
        if (unlikely(ctx->mem_idx & 1)) {
2422
            /* Little-endian mode is not handled */
2423
            GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2424
            return;
2425
        }
2426
        gen_addr_imm_index(ctx, 0x03);
2427
        gen_op_load_gpr_T1(rs);
2428
        op_ldst(std);
2429
        gen_op_addi(8);
2430
        gen_op_load_gpr_T1(rs + 1);
2431
        op_ldst(std);
2432
#endif
2433
    } else {
2434
        /* std / stdu */
2435
        if (Rc(ctx->opcode)) {
2436
            if (unlikely(rA(ctx->opcode) == 0)) {
2437
                GEN_EXCP_INVAL(ctx);
2438
                return;
2439
            }
2440
        }
2441
        gen_addr_imm_index(ctx, 0x03);
2442
        gen_op_load_gpr_T1(rs);
2443
        op_ldst(std);
2444
        if (Rc(ctx->opcode))
2445
            gen_op_store_T0_gpr(rA(ctx->opcode));
2446
    }
2447
}
2448
#endif
2449
/***                Integer load and store with byte reverse               ***/
2450
/* lhbrx */
2451
OP_LD_TABLE(hbr);
2452
GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2453
/* lwbrx */
2454
OP_LD_TABLE(wbr);
2455
GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2456
/* sthbrx */
2457
OP_ST_TABLE(hbr);
2458
GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2459
/* stwbrx */
2460
OP_ST_TABLE(wbr);
2461
GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2462

    
2463
/***                    Integer load and store multiple                    ***/
2464
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2465
static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2466
    GEN_MEM_FUNCS(lmw),
2467
};
2468
static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2469
    GEN_MEM_FUNCS(stmw),
2470
};
2471

    
2472
/* lmw */
2473
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2474
{
2475
    /* NIP cannot be restored if the memory exception comes from an helper */
2476
    gen_update_nip(ctx, ctx->nip - 4);
2477
    gen_addr_imm_index(ctx, 0);
2478
    op_ldstm(lmw, rD(ctx->opcode));
2479
}
2480

    
2481
/* stmw */
2482
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2483
{
2484
    /* NIP cannot be restored if the memory exception comes from an helper */
2485
    gen_update_nip(ctx, ctx->nip - 4);
2486
    gen_addr_imm_index(ctx, 0);
2487
    op_ldstm(stmw, rS(ctx->opcode));
2488
}
2489

    
2490
/***                    Integer load and store strings                     ***/
2491
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2492
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2493
/* string load & stores are by definition endian-safe */
2494
#define gen_op_lswi_le_raw       gen_op_lswi_raw
2495
#define gen_op_lswi_le_user      gen_op_lswi_user
2496
#define gen_op_lswi_le_kernel    gen_op_lswi_kernel
2497
#define gen_op_lswi_le_hypv      gen_op_lswi_hypv
2498
#define gen_op_lswi_le_64_raw    gen_op_lswi_raw
2499
#define gen_op_lswi_le_64_user   gen_op_lswi_user
2500
#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2501
#define gen_op_lswi_le_64_hypv   gen_op_lswi_hypv
2502
static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2503
    GEN_MEM_FUNCS(lswi),
2504
};
2505
#define gen_op_lswx_le_raw       gen_op_lswx_raw
2506
#define gen_op_lswx_le_user      gen_op_lswx_user
2507
#define gen_op_lswx_le_kernel    gen_op_lswx_kernel
2508
#define gen_op_lswx_le_hypv      gen_op_lswx_hypv
2509
#define gen_op_lswx_le_64_raw    gen_op_lswx_raw
2510
#define gen_op_lswx_le_64_user   gen_op_lswx_user
2511
#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2512
#define gen_op_lswx_le_64_hypv   gen_op_lswx_hypv
2513
static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2514
    GEN_MEM_FUNCS(lswx),
2515
};
2516
#define gen_op_stsw_le_raw       gen_op_stsw_raw
2517
#define gen_op_stsw_le_user      gen_op_stsw_user
2518
#define gen_op_stsw_le_kernel    gen_op_stsw_kernel
2519
#define gen_op_stsw_le_hypv      gen_op_stsw_hypv
2520
#define gen_op_stsw_le_64_raw    gen_op_stsw_raw
2521
#define gen_op_stsw_le_64_user   gen_op_stsw_user
2522
#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2523
#define gen_op_stsw_le_64_hypv   gen_op_stsw_hypv
2524
static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2525
    GEN_MEM_FUNCS(stsw),
2526
};
2527

    
2528
/* lswi */
2529
/* PowerPC32 specification says we must generate an exception if
2530
 * rA is in the range of registers to be loaded.
2531
 * In an other hand, IBM says this is valid, but rA won't be loaded.
2532
 * For now, I'll follow the spec...
2533
 */
2534
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
2535
{
2536
    int nb = NB(ctx->opcode);
2537
    int start = rD(ctx->opcode);
2538
    int ra = rA(ctx->opcode);
2539
    int nr;
2540

    
2541
    if (nb == 0)
2542
        nb = 32;
2543
    nr = nb / 4;
2544
    if (unlikely(((start + nr) > 32  &&
2545
                  start <= ra && (start + nr - 32) > ra) ||
2546
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2547
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2548
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2549
        return;
2550
    }
2551
    /* NIP cannot be restored if the memory exception comes from an helper */
2552
    gen_update_nip(ctx, ctx->nip - 4);
2553
    gen_addr_register(ctx);
2554
    gen_op_set_T1(nb);
2555
    op_ldsts(lswi, start);
2556
}
2557

    
2558
/* lswx */
2559
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
2560
{
2561
    int ra = rA(ctx->opcode);
2562
    int rb = rB(ctx->opcode);
2563

    
2564
    /* NIP cannot be restored if the memory exception comes from an helper */
2565
    gen_update_nip(ctx, ctx->nip - 4);
2566
    gen_addr_reg_index(ctx);
2567
    if (ra == 0) {
2568
        ra = rb;
2569
    }
2570
    gen_op_load_xer_bc();
2571
    op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2572
}
2573

    
2574
/* stswi */
2575
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
2576
{
2577
    int nb = NB(ctx->opcode);
2578

    
2579
    /* NIP cannot be restored if the memory exception comes from an helper */
2580
    gen_update_nip(ctx, ctx->nip - 4);
2581
    gen_addr_register(ctx);
2582
    if (nb == 0)
2583
        nb = 32;
2584
    gen_op_set_T1(nb);
2585
    op_ldsts(stsw, rS(ctx->opcode));
2586
}
2587

    
2588
/* stswx */
2589
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
2590
{
2591
    /* NIP cannot be restored if the memory exception comes from an helper */
2592
    gen_update_nip(ctx, ctx->nip - 4);
2593
    gen_addr_reg_index(ctx);
2594
    gen_op_load_xer_bc();
2595
    op_ldsts(stsw, rS(ctx->opcode));
2596
}
2597

    
2598
/***                        Memory synchronisation                         ***/
2599
/* eieio */
2600
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2601
{
2602
}
2603

    
2604
/* isync */
2605
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2606
{
2607
    GEN_STOP(ctx);
2608
}
2609

    
2610
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2611
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2612
static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2613
    GEN_MEM_FUNCS(lwarx),
2614
};
2615
static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2616
    GEN_MEM_FUNCS(stwcx),
2617
};
2618

    
2619
/* lwarx */
2620
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2621
{
2622
    /* NIP cannot be restored if the memory exception comes from an helper */
2623
    gen_update_nip(ctx, ctx->nip - 4);
2624
    gen_addr_reg_index(ctx);
2625
    op_lwarx();
2626
    gen_op_store_T1_gpr(rD(ctx->opcode));
2627
}
2628

    
2629
/* stwcx. */
2630
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2631
{
2632
    /* NIP cannot be restored if the memory exception comes from an helper */
2633
    gen_update_nip(ctx, ctx->nip - 4);
2634
    gen_addr_reg_index(ctx);
2635
    gen_op_load_gpr_T1(rS(ctx->opcode));
2636
    op_stwcx();
2637
}
2638

    
2639
#if defined(TARGET_PPC64)
2640
#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2641
#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2642
static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2643
    GEN_MEM_FUNCS(ldarx),
2644
};
2645
static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2646
    GEN_MEM_FUNCS(stdcx),
2647
};
2648

    
2649
/* ldarx */
2650
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2651
{
2652
    /* NIP cannot be restored if the memory exception comes from an helper */
2653
    gen_update_nip(ctx, ctx->nip - 4);
2654
    gen_addr_reg_index(ctx);
2655
    op_ldarx();
2656
    gen_op_store_T1_gpr(rD(ctx->opcode));
2657
}
2658

    
2659
/* stdcx. */
2660
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2661
{
2662
    /* NIP cannot be restored if the memory exception comes from an helper */
2663
    gen_update_nip(ctx, ctx->nip - 4);
2664
    gen_addr_reg_index(ctx);
2665
    gen_op_load_gpr_T1(rS(ctx->opcode));
2666
    op_stdcx();
2667
}
2668
#endif /* defined(TARGET_PPC64) */
2669

    
2670
/* sync */
2671
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2672
{
2673
}
2674

    
2675
/* wait */
2676
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2677
{
2678
    /* Stop translation, as the CPU is supposed to sleep from now */
2679
    gen_op_wait();
2680
    GEN_EXCP(ctx, EXCP_HLT, 1);
2681
}
2682

    
2683
/***                         Floating-point load                           ***/
2684
#define GEN_LDF(width, opc, type)                                             \
2685
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2686
{                                                                             \
2687
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2688
        GEN_EXCP_NO_FP(ctx);                                                  \
2689
        return;                                                               \
2690
    }                                                                         \
2691
    gen_addr_imm_index(ctx, 0);                                               \
2692
    op_ldst(l##width);                                                        \
2693
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2694
}
2695

    
2696
#define GEN_LDUF(width, opc, type)                                            \
2697
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2698
{                                                                             \
2699
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2700
        GEN_EXCP_NO_FP(ctx);                                                  \
2701
        return;                                                               \
2702
    }                                                                         \
2703
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2704
        GEN_EXCP_INVAL(ctx);                                                  \
2705
        return;                                                               \
2706
    }                                                                         \
2707
    gen_addr_imm_index(ctx, 0);                                               \
2708
    op_ldst(l##width);                                                        \
2709
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2710
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2711
}
2712

    
2713
#define GEN_LDUXF(width, opc, type)                                           \
2714
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                  \
2715
{                                                                             \
2716
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2717
        GEN_EXCP_NO_FP(ctx);                                                  \
2718
        return;                                                               \
2719
    }                                                                         \
2720
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2721
        GEN_EXCP_INVAL(ctx);                                                  \
2722
        return;                                                               \
2723
    }                                                                         \
2724
    gen_addr_reg_index(ctx);                                                  \
2725
    op_ldst(l##width);                                                        \
2726
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2727
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2728
}
2729

    
2730
#define GEN_LDXF(width, opc2, opc3, type)                                     \
2731
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2732
{                                                                             \
2733
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2734
        GEN_EXCP_NO_FP(ctx);                                                  \
2735
        return;                                                               \
2736
    }                                                                         \
2737
    gen_addr_reg_index(ctx);                                                  \
2738
    op_ldst(l##width);                                                        \
2739
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2740
}
2741

    
2742
#define GEN_LDFS(width, op, type)                                             \
2743
OP_LD_TABLE(width);                                                           \
2744
GEN_LDF(width, op | 0x20, type);                                              \
2745
GEN_LDUF(width, op | 0x21, type);                                             \
2746
GEN_LDUXF(width, op | 0x01, type);                                            \
2747
GEN_LDXF(width, 0x17, op | 0x00, type)
2748

    
2749
/* lfd lfdu lfdux lfdx */
2750
GEN_LDFS(fd, 0x12, PPC_FLOAT);
2751
/* lfs lfsu lfsux lfsx */
2752
GEN_LDFS(fs, 0x10, PPC_FLOAT);
2753

    
2754
/***                         Floating-point store                          ***/
2755
#define GEN_STF(width, opc, type)                                             \
2756
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
2757
{                                                                             \
2758
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2759
        GEN_EXCP_NO_FP(ctx);                                                  \
2760
        return;                                                               \
2761
    }                                                                         \
2762
    gen_addr_imm_index(ctx, 0);                                               \
2763
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2764
    op_ldst(st##width);                                                       \
2765
}
2766

    
2767
#define GEN_STUF(width, opc, type)                                            \
2768
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
2769
{                                                                             \
2770
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2771
        GEN_EXCP_NO_FP(ctx);                                                  \
2772
        return;                                                               \
2773
    }                                                                         \
2774
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2775
        GEN_EXCP_INVAL(ctx);                                                  \
2776
        return;                                                               \
2777
    }                                                                         \
2778
    gen_addr_imm_index(ctx, 0);                                               \
2779
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2780
    op_ldst(st##width);                                                       \
2781
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2782
}
2783

    
2784
#define GEN_STUXF(width, opc, type)                                           \
2785
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                 \
2786
{                                                                             \
2787
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2788
        GEN_EXCP_NO_FP(ctx);                                                  \
2789
        return;                                                               \
2790
    }                                                                         \
2791
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2792
        GEN_EXCP_INVAL(ctx);                                                  \
2793
        return;                                                               \
2794
    }                                                                         \
2795
    gen_addr_reg_index(ctx);                                                  \
2796
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2797
    op_ldst(st##width);                                                       \
2798
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2799
}
2800

    
2801
#define GEN_STXF(width, opc2, opc3, type)                                     \
2802
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
2803
{                                                                             \
2804
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2805
        GEN_EXCP_NO_FP(ctx);                                                  \
2806
        return;                                                               \
2807
    }                                                                         \
2808
    gen_addr_reg_index(ctx);                                                  \
2809
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2810
    op_ldst(st##width);                                                       \
2811
}
2812

    
2813
#define GEN_STFS(width, op, type)                                             \
2814
OP_ST_TABLE(width);                                                           \
2815
GEN_STF(width, op | 0x20, type);                                              \
2816
GEN_STUF(width, op | 0x21, type);                                             \
2817
GEN_STUXF(width, op | 0x01, type);                                            \
2818
GEN_STXF(width, 0x17, op | 0x00, type)
2819

    
2820
/* stfd stfdu stfdux stfdx */
2821
GEN_STFS(fd, 0x16, PPC_FLOAT);
2822
/* stfs stfsu stfsux stfsx */
2823
GEN_STFS(fs, 0x14, PPC_FLOAT);
2824

    
2825
/* Optional: */
2826
/* stfiwx */
2827
OP_ST_TABLE(fiw);
2828
GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
2829

    
2830
/***                                Branch                                 ***/
2831
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2832
                                       target_ulong dest)
2833
{
2834
    TranslationBlock *tb;
2835
    tb = ctx->tb;
2836
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2837
        likely(!ctx->singlestep_enabled)) {
2838
        tcg_gen_goto_tb(n);
2839
        gen_set_T1(dest);
2840
#if defined(TARGET_PPC64)
2841
        if (ctx->sf_mode)
2842
            gen_op_b_T1_64();
2843
        else
2844
#endif
2845
            gen_op_b_T1();
2846
        tcg_gen_exit_tb((long)tb + n);
2847
    } else {
2848
        gen_set_T1(dest);
2849
#if defined(TARGET_PPC64)
2850
        if (ctx->sf_mode)
2851
            gen_op_b_T1_64();
2852
        else
2853
#endif
2854
            gen_op_b_T1();
2855
        if (unlikely(ctx->singlestep_enabled)) {
2856
            if ((ctx->singlestep_enabled &
2857
                 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
2858
                ctx->exception == POWERPC_EXCP_BRANCH) {
2859
                target_ulong tmp = ctx->nip;
2860
                ctx->nip = dest;
2861
                GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
2862
                ctx->nip = tmp;
2863
            }
2864
            if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
2865
                gen_update_nip(ctx, dest);
2866
                gen_op_debug();
2867
            }
2868
        }
2869
        tcg_gen_exit_tb(0);
2870
    }
2871
}
2872

    
2873
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
2874
{
2875
#if defined(TARGET_PPC64)
2876
    if (ctx->sf_mode != 0 && (nip >> 32))
2877
        gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2878
    else
2879
#endif
2880
        gen_op_setlr(ctx->nip);
2881
}
2882

    
2883
/* b ba bl bla */
2884
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2885
{
2886
    target_ulong li, target;
2887

    
2888
    ctx->exception = POWERPC_EXCP_BRANCH;
2889
    /* sign extend LI */
2890
#if defined(TARGET_PPC64)
2891
    if (ctx->sf_mode)
2892
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
2893
    else
2894
#endif
2895
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
2896
    if (likely(AA(ctx->opcode) == 0))
2897
        target = ctx->nip + li - 4;
2898
    else
2899
        target = li;
2900
#if defined(TARGET_PPC64)
2901
    if (!ctx->sf_mode)
2902
        target = (uint32_t)target;
2903
#endif
2904
    if (LK(ctx->opcode))
2905
        gen_setlr(ctx, ctx->nip);
2906
    gen_goto_tb(ctx, 0, target);
2907
}
2908

    
2909
#define BCOND_IM  0
2910
#define BCOND_LR  1
2911
#define BCOND_CTR 2
2912

    
2913
static always_inline void gen_bcond (DisasContext *ctx, int type)
2914
{
2915
    target_ulong target = 0;
2916
    target_ulong li;
2917
    uint32_t bo = BO(ctx->opcode);
2918
    uint32_t bi = BI(ctx->opcode);
2919
    uint32_t mask;
2920

    
2921
    ctx->exception = POWERPC_EXCP_BRANCH;
2922
    if ((bo & 0x4) == 0)
2923
        gen_op_dec_ctr();
2924
    switch(type) {
2925
    case BCOND_IM:
2926
        li = (target_long)((int16_t)(BD(ctx->opcode)));
2927
        if (likely(AA(ctx->opcode) == 0)) {
2928
            target = ctx->nip + li - 4;
2929
        } else {
2930
            target = li;
2931
        }
2932
#if defined(TARGET_PPC64)
2933
        if (!ctx->sf_mode)
2934
            target = (uint32_t)target;
2935
#endif
2936
        break;
2937
    case BCOND_CTR:
2938
        gen_op_movl_T1_ctr();
2939
        break;
2940
    default:
2941
    case BCOND_LR:
2942
        gen_op_movl_T1_lr();
2943
        break;
2944
    }
2945
    if (LK(ctx->opcode))
2946
        gen_setlr(ctx, ctx->nip);
2947
    if (bo & 0x10) {
2948
        /* No CR condition */
2949
        switch (bo & 0x6) {
2950
        case 0:
2951
#if defined(TARGET_PPC64)
2952
            if (ctx->sf_mode)
2953
                gen_op_test_ctr_64();
2954
            else
2955
#endif
2956
                gen_op_test_ctr();
2957
            break;
2958
        case 2:
2959
#if defined(TARGET_PPC64)
2960
            if (ctx->sf_mode)
2961
                gen_op_test_ctrz_64();
2962
            else
2963
#endif
2964
                gen_op_test_ctrz();
2965
            break;
2966
        default:
2967
        case 4:
2968
        case 6:
2969
            if (type == BCOND_IM) {
2970
                gen_goto_tb(ctx, 0, target);
2971
                return;
2972
            } else {
2973
#if defined(TARGET_PPC64)
2974
                if (ctx->sf_mode)
2975
                    gen_op_b_T1_64();
2976
                else
2977
#endif
2978
                    gen_op_b_T1();
2979
                goto no_test;
2980
            }
2981
            break;
2982
        }
2983
    } else {
2984
        mask = 1 << (3 - (bi & 0x03));
2985
        gen_op_load_crf_T0(bi >> 2);
2986
        if (bo & 0x8) {
2987
            switch (bo & 0x6) {
2988
            case 0:
2989
#if defined(TARGET_PPC64)
2990
                if (ctx->sf_mode)
2991
                    gen_op_test_ctr_true_64(mask);
2992
                else
2993
#endif
2994
                    gen_op_test_ctr_true(mask);
2995
                break;
2996
            case 2:
2997
#if defined(TARGET_PPC64)
2998
                if (ctx->sf_mode)
2999
                    gen_op_test_ctrz_true_64(mask);
3000
                else
3001
#endif
3002
                    gen_op_test_ctrz_true(mask);
3003
                break;
3004
            default:
3005
            case 4:
3006
            case 6:
3007
                gen_op_test_true(mask);
3008
                break;
3009
            }
3010
        } else {
3011
            switch (bo & 0x6) {
3012
            case 0:
3013
#if defined(TARGET_PPC64)
3014
                if (ctx->sf_mode)
3015
                    gen_op_test_ctr_false_64(mask);
3016
                else
3017
#endif
3018
                    gen_op_test_ctr_false(mask);
3019
                break;
3020
            case 2:
3021
#if defined(TARGET_PPC64)
3022
                if (ctx->sf_mode)
3023
                    gen_op_test_ctrz_false_64(mask);
3024
                else
3025
#endif
3026
                    gen_op_test_ctrz_false(mask);
3027
                break;
3028
            default:
3029
            case 4:
3030
            case 6:
3031
                gen_op_test_false(mask);
3032
                break;
3033
            }
3034
        }
3035
    }
3036
    if (type == BCOND_IM) {
3037
        int l1 = gen_new_label();
3038
        gen_op_jz_T0(l1);
3039
        gen_goto_tb(ctx, 0, target);
3040
        gen_set_label(l1);
3041
        gen_goto_tb(ctx, 1, ctx->nip);
3042
    } else {
3043
#if defined(TARGET_PPC64)
3044
        if (ctx->sf_mode)
3045
            gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3046
        else
3047
#endif
3048
            gen_op_btest_T1(ctx->nip);
3049
    no_test:
3050
        if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3051
            gen_update_nip(ctx, ctx->nip);
3052
            gen_op_debug();
3053
        }
3054
        tcg_gen_exit_tb(0);
3055
    }
3056
}
3057

    
3058
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3059
{
3060
    gen_bcond(ctx, BCOND_IM);
3061
}
3062

    
3063
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3064
{
3065
    gen_bcond(ctx, BCOND_CTR);
3066
}
3067

    
3068
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3069
{
3070
    gen_bcond(ctx, BCOND_LR);
3071
}
3072

    
3073
/***                      Condition register logical                       ***/
3074
#define GEN_CRLOGIC(op, opc)                                                  \
3075
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
3076
{                                                                             \
3077
    uint8_t bitmask;                                                          \
3078
    int sh;                                                                   \
3079
    gen_op_load_crf_T0(crbA(ctx->opcode) >> 2);                               \
3080
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3081
    if (sh > 0)                                                               \
3082
        gen_op_srli_T0(sh);                                                   \
3083
    else if (sh < 0)                                                          \
3084
        gen_op_sli_T0(-sh);                                                   \
3085
    gen_op_load_crf_T1(crbB(ctx->opcode) >> 2);                               \
3086
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3087
    if (sh > 0)                                                               \
3088
        gen_op_srli_T1(sh);                                                   \
3089
    else if (sh < 0)                                                          \
3090
        gen_op_sli_T1(-sh);                                                   \
3091
    gen_op_##op();                                                            \
3092
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3093
    gen_op_andi_T0(bitmask);                                                  \
3094
    gen_op_load_crf_T1(crbD(ctx->opcode) >> 2);                               \
3095
    gen_op_andi_T1(~bitmask);                                                 \
3096
    gen_op_or();                                                              \
3097
    gen_op_store_T0_crf(crbD(ctx->opcode) >> 2);                              \
3098
}
3099

    
3100
/* crand */
3101
GEN_CRLOGIC(and, 0x08);
3102
/* crandc */
3103
GEN_CRLOGIC(andc, 0x04);
3104
/* creqv */
3105
GEN_CRLOGIC(eqv, 0x09);
3106
/* crnand */
3107
GEN_CRLOGIC(nand, 0x07);
3108
/* crnor */
3109
GEN_CRLOGIC(nor, 0x01);
3110
/* cror */
3111
GEN_CRLOGIC(or, 0x0E);
3112
/* crorc */
3113
GEN_CRLOGIC(orc, 0x0D);
3114
/* crxor */
3115
GEN_CRLOGIC(xor, 0x06);
3116
/* mcrf */
3117
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3118
{
3119
    gen_op_load_crf_T0(crfS(ctx->opcode));
3120
    gen_op_store_T0_crf(crfD(ctx->opcode));
3121
}
3122

    
3123
/***                           System linkage                              ***/
3124
/* rfi (supervisor only) */
3125
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3126
{
3127
#if defined(CONFIG_USER_ONLY)
3128
    GEN_EXCP_PRIVOPC(ctx);
3129
#else
3130
    /* Restore CPU state */
3131
    if (unlikely(!ctx->supervisor)) {
3132
        GEN_EXCP_PRIVOPC(ctx);
3133
        return;
3134
    }
3135
    gen_op_rfi();
3136
    GEN_SYNC(ctx);
3137
#endif
3138
}
3139

    
3140
#if defined(TARGET_PPC64)
3141
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3142
{
3143
#if defined(CONFIG_USER_ONLY)
3144
    GEN_EXCP_PRIVOPC(ctx);
3145
#else
3146
    /* Restore CPU state */
3147
    if (unlikely(!ctx->supervisor)) {
3148
        GEN_EXCP_PRIVOPC(ctx);
3149
        return;
3150
    }
3151
    gen_op_rfid();
3152
    GEN_SYNC(ctx);
3153
#endif
3154
}
3155

    
3156
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3157
{
3158
#if defined(CONFIG_USER_ONLY)
3159
    GEN_EXCP_PRIVOPC(ctx);
3160
#else
3161
    /* Restore CPU state */
3162
    if (unlikely(ctx->supervisor <= 1)) {
3163
        GEN_EXCP_PRIVOPC(ctx);
3164
        return;
3165
    }
3166
    gen_op_hrfid();
3167
    GEN_SYNC(ctx);
3168
#endif
3169
}
3170
#endif
3171

    
3172
/* sc */
3173
#if defined(CONFIG_USER_ONLY)
3174
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3175
#else
3176
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3177
#endif
3178
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3179
{
3180
    uint32_t lev;
3181

    
3182
    lev = (ctx->opcode >> 5) & 0x7F;
3183
    GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3184
}
3185

    
3186
/***                                Trap                                   ***/
3187
/* tw */
3188
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3189
{
3190
    gen_op_load_gpr_T0(rA(ctx->opcode));
3191
    gen_op_load_gpr_T1(rB(ctx->opcode));
3192
    /* Update the nip since this might generate a trap exception */
3193
    gen_update_nip(ctx, ctx->nip);
3194
    gen_op_tw(TO(ctx->opcode));
3195
}
3196

    
3197
/* twi */
3198
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3199
{
3200
    gen_op_load_gpr_T0(rA(ctx->opcode));
3201
    gen_set_T1(SIMM(ctx->opcode));
3202
    /* Update the nip since this might generate a trap exception */
3203
    gen_update_nip(ctx, ctx->nip);
3204
    gen_op_tw(TO(ctx->opcode));
3205
}
3206

    
3207
#if defined(TARGET_PPC64)
3208
/* td */
3209
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3210
{
3211
    gen_op_load_gpr_T0(rA(ctx->opcode));
3212
    gen_op_load_gpr_T1(rB(ctx->opcode));
3213
    /* Update the nip since this might generate a trap exception */
3214
    gen_update_nip(ctx, ctx->nip);
3215
    gen_op_td(TO(ctx->opcode));
3216
}
3217

    
3218
/* tdi */
3219
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3220
{
3221
    gen_op_load_gpr_T0(rA(ctx->opcode));
3222
    gen_set_T1(SIMM(ctx->opcode));
3223
    /* Update the nip since this might generate a trap exception */
3224
    gen_update_nip(ctx, ctx->nip);
3225
    gen_op_td(TO(ctx->opcode));
3226
}
3227
#endif
3228

    
3229
/***                          Processor control                            ***/
3230
/* mcrxr */
3231
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3232
{
3233
    gen_op_load_xer_cr();
3234
    gen_op_store_T0_crf(crfD(ctx->opcode));
3235
    gen_op_clear_xer_ov();
3236
    gen_op_clear_xer_ca();
3237
}
3238

    
3239
/* mfcr */
3240
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3241
{
3242
    uint32_t crm, crn;
3243

    
3244
    if (likely(ctx->opcode & 0x00100000)) {
3245
        crm = CRM(ctx->opcode);
3246
        if (likely((crm ^ (crm - 1)) == 0)) {
3247
            crn = ffs(crm);
3248
            tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUState, crf[7 - crn]));
3249
        }
3250
    } else {
3251
        tcg_gen_helper_1_0(do_load_cr, cpu_T[0]);
3252
    }
3253
    gen_op_store_T0_gpr(rD(ctx->opcode));
3254
}
3255

    
3256
/* mfmsr */
3257
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3258
{
3259
#if defined(CONFIG_USER_ONLY)
3260
    GEN_EXCP_PRIVREG(ctx);
3261
#else
3262
    if (unlikely(!ctx->supervisor)) {
3263
        GEN_EXCP_PRIVREG(ctx);
3264
        return;
3265
    }
3266
    tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, msr));
3267
    gen_op_store_T0_gpr(rD(ctx->opcode));
3268
#endif
3269
}
3270

    
3271
#if 1
3272
#define SPR_NOACCESS ((void *)(-1UL))
3273
#else
3274
static void spr_noaccess (void *opaque, int sprn)
3275
{
3276
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3277
    printf("ERROR: try to access SPR %d !\n", sprn);
3278
}
3279
#define SPR_NOACCESS (&spr_noaccess)
3280
#endif
3281

    
3282
/* mfspr */
3283
static always_inline void gen_op_mfspr (DisasContext *ctx)
3284
{
3285
    void (*read_cb)(void *opaque, int sprn);
3286
    uint32_t sprn = SPR(ctx->opcode);
3287

    
3288
#if !defined(CONFIG_USER_ONLY)
3289
    if (ctx->supervisor == 2)
3290
        read_cb = ctx->spr_cb[sprn].hea_read;
3291
    else if (ctx->supervisor)
3292
        read_cb = ctx->spr_cb[sprn].oea_read;
3293
    else
3294
#endif
3295
        read_cb = ctx->spr_cb[sprn].uea_read;
3296
    if (likely(read_cb != NULL)) {
3297
        if (likely(read_cb != SPR_NOACCESS)) {
3298
            (*read_cb)(ctx, sprn);
3299
            gen_op_store_T0_gpr(rD(ctx->opcode));
3300
        } else {
3301
            /* Privilege exception */
3302
            /* This is a hack to avoid warnings when running Linux:
3303
             * this OS breaks the PowerPC virtualisation model,
3304
             * allowing userland application to read the PVR
3305
             */
3306
            if (sprn != SPR_PVR) {
3307
                if (loglevel != 0) {
3308
                    fprintf(logfile, "Trying to read privileged spr %d %03x at "
3309
                            ADDRX "\n", sprn, sprn, ctx->nip);
3310
                }
3311
                printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3312
                       sprn, sprn, ctx->nip);
3313
            }
3314
            GEN_EXCP_PRIVREG(ctx);
3315
        }
3316
    } else {
3317
        /* Not defined */
3318
        if (loglevel != 0) {
3319
            fprintf(logfile, "Trying to read invalid spr %d %03x at "
3320
                    ADDRX "\n", sprn, sprn, ctx->nip);
3321
        }
3322
        printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3323
               sprn, sprn, ctx->nip);
3324
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3325
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3326
    }
3327
}
3328

    
3329
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3330
{
3331
    gen_op_mfspr(ctx);
3332
}
3333

    
3334
/* mftb */
3335
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3336
{
3337
    gen_op_mfspr(ctx);
3338
}
3339

    
3340
/* mtcrf */
3341
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3342
{
3343
    uint32_t crm, crn;
3344

    
3345
    gen_op_load_gpr_T0(rS(ctx->opcode));
3346
    crm = CRM(ctx->opcode);
3347
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3348
        crn = ffs(crm);
3349
        gen_op_srli_T0(crn * 4);
3350
        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xF);
3351
        tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUState, crf[7 - crn]));
3352
    } else {
3353
        tcg_gen_helper_0_i(do_store_cr, crm);
3354
    }
3355
}
3356

    
3357
/* mtmsr */
3358
#if defined(TARGET_PPC64)
3359
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3360
{
3361
#if defined(CONFIG_USER_ONLY)
3362
    GEN_EXCP_PRIVREG(ctx);
3363
#else
3364
    if (unlikely(!ctx->supervisor)) {
3365
        GEN_EXCP_PRIVREG(ctx);
3366
        return;
3367
    }
3368
    gen_op_load_gpr_T0(rS(ctx->opcode));
3369
    if (ctx->opcode & 0x00010000) {
3370
        /* Special form that does not need any synchronisation */
3371
        gen_op_update_riee();
3372
    } else {
3373
        /* XXX: we need to update nip before the store
3374
         *      if we enter power saving mode, we will exit the loop
3375
         *      directly from ppc_store_msr
3376
         */
3377
        gen_update_nip(ctx, ctx->nip);
3378
        tcg_gen_helper_0_1(do_store_msr, cpu_T[0]);
3379
        /* Must stop the translation as machine state (may have) changed */
3380
        /* Note that mtmsr is not always defined as context-synchronizing */
3381
        ctx->exception = POWERPC_EXCP_STOP;
3382
    }
3383
#endif
3384
}
3385
#endif
3386

    
3387
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3388
{
3389
#if defined(CONFIG_USER_ONLY)
3390
    GEN_EXCP_PRIVREG(ctx);
3391
#else
3392
    if (unlikely(!ctx->supervisor)) {
3393
        GEN_EXCP_PRIVREG(ctx);
3394
        return;
3395
    }
3396
    gen_op_load_gpr_T0(rS(ctx->opcode));
3397
    if (ctx->opcode & 0x00010000) {
3398
        /* Special form that does not need any synchronisation */
3399
        gen_op_update_riee();
3400
    } else {
3401
        /* XXX: we need to update nip before the store
3402
         *      if we enter power saving mode, we will exit the loop
3403
         *      directly from ppc_store_msr
3404
         */
3405
        gen_update_nip(ctx, ctx->nip);
3406
#if defined(TARGET_PPC64)
3407
        if (!ctx->sf_mode)
3408
            tcg_gen_helper_0_1(do_store_msr_32, cpu_T[0]);
3409
        else
3410
#endif
3411
            tcg_gen_helper_0_1(do_store_msr, cpu_T[0]);
3412
        /* Must stop the translation as machine state (may have) changed */
3413
        /* Note that mtmsrd is not always defined as context-synchronizing */
3414
        ctx->exception = POWERPC_EXCP_STOP;
3415
    }
3416
#endif
3417
}
3418

    
3419
/* mtspr */
3420
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3421
{
3422
    void (*write_cb)(void *opaque, int sprn);
3423
    uint32_t sprn = SPR(ctx->opcode);
3424

    
3425
#if !defined(CONFIG_USER_ONLY)
3426
    if (ctx->supervisor == 2)
3427
        write_cb = ctx->spr_cb[sprn].hea_write;
3428
    else if (ctx->supervisor)
3429
        write_cb = ctx->spr_cb[sprn].oea_write;
3430
    else
3431
#endif
3432
        write_cb = ctx->spr_cb[sprn].uea_write;
3433
    if (likely(write_cb != NULL)) {
3434
        if (likely(write_cb != SPR_NOACCESS)) {
3435
            gen_op_load_gpr_T0(rS(ctx->opcode));
3436
            (*write_cb)(ctx, sprn);
3437
        } else {
3438
            /* Privilege exception */
3439
            if (loglevel != 0) {
3440
                fprintf(logfile, "Trying to write privileged spr %d %03x at "
3441
                        ADDRX "\n", sprn, sprn, ctx->nip);
3442
            }
3443
            printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3444
                   sprn, sprn, ctx->nip);
3445
            GEN_EXCP_PRIVREG(ctx);
3446
        }
3447
    } else {
3448
        /* Not defined */
3449
        if (loglevel != 0) {
3450
            fprintf(logfile, "Trying to write invalid spr %d %03x at "
3451
                    ADDRX "\n", sprn, sprn, ctx->nip);
3452
        }
3453
        printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3454
               sprn, sprn, ctx->nip);
3455
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3456
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3457
    }
3458
}
3459

    
3460
/***                         Cache management                              ***/
3461
/* dcbf */
3462
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3463
{
3464
    /* XXX: specification says this is treated as a load by the MMU */
3465
    gen_addr_reg_index(ctx);
3466
    op_ldst(lbz);
3467
}
3468

    
3469
/* dcbi (Supervisor only) */
3470
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3471
{
3472
#if defined(CONFIG_USER_ONLY)
3473
    GEN_EXCP_PRIVOPC(ctx);
3474
#else
3475
    if (unlikely(!ctx->supervisor)) {
3476
        GEN_EXCP_PRIVOPC(ctx);
3477
        return;
3478
    }
3479
    gen_addr_reg_index(ctx);
3480
    /* XXX: specification says this should be treated as a store by the MMU */
3481
    op_ldst(lbz);
3482
    op_ldst(stb);
3483
#endif
3484
}
3485

    
3486
/* dcdst */
3487
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3488
{
3489
    /* XXX: specification say this is treated as a load by the MMU */
3490
    gen_addr_reg_index(ctx);
3491
    op_ldst(lbz);
3492
}
3493

    
3494
/* dcbt */
3495
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3496
{
3497
    /* interpreted as no-op */
3498
    /* XXX: specification say this is treated as a load by the MMU
3499
     *      but does not generate any exception
3500
     */
3501
}
3502

    
3503
/* dcbtst */
3504
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3505
{
3506
    /* interpreted as no-op */
3507
    /* XXX: specification say this is treated as a load by the MMU
3508
     *      but does not generate any exception
3509
     */
3510
}
3511

    
3512
/* dcbz */
3513
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3514
static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3515
    /* 32 bytes cache line size */
3516
    {
3517
#define gen_op_dcbz_l32_le_raw        gen_op_dcbz_l32_raw
3518
#define gen_op_dcbz_l32_le_user       gen_op_dcbz_l32_user
3519
#define gen_op_dcbz_l32_le_kernel     gen_op_dcbz_l32_kernel
3520
#define gen_op_dcbz_l32_le_hypv       gen_op_dcbz_l32_hypv
3521
#define gen_op_dcbz_l32_le_64_raw     gen_op_dcbz_l32_64_raw
3522
#define gen_op_dcbz_l32_le_64_user    gen_op_dcbz_l32_64_user
3523
#define gen_op_dcbz_l32_le_64_kernel  gen_op_dcbz_l32_64_kernel
3524
#define gen_op_dcbz_l32_le_64_hypv    gen_op_dcbz_l32_64_hypv
3525
        GEN_MEM_FUNCS(dcbz_l32),
3526
    },
3527
    /* 64 bytes cache line size */
3528
    {
3529
#define gen_op_dcbz_l64_le_raw        gen_op_dcbz_l64_raw
3530
#define gen_op_dcbz_l64_le_user       gen_op_dcbz_l64_user
3531
#define gen_op_dcbz_l64_le_kernel     gen_op_dcbz_l64_kernel
3532
#define gen_op_dcbz_l64_le_hypv       gen_op_dcbz_l64_hypv
3533
#define gen_op_dcbz_l64_le_64_raw     gen_op_dcbz_l64_64_raw
3534
#define gen_op_dcbz_l64_le_64_user    gen_op_dcbz_l64_64_user
3535
#define gen_op_dcbz_l64_le_64_kernel  gen_op_dcbz_l64_64_kernel
3536
#define gen_op_dcbz_l64_le_64_hypv    gen_op_dcbz_l64_64_hypv
3537
        GEN_MEM_FUNCS(dcbz_l64),
3538
    },
3539
    /* 128 bytes cache line size */
3540
    {
3541
#define gen_op_dcbz_l128_le_raw       gen_op_dcbz_l128_raw
3542
#define gen_op_dcbz_l128_le_user      gen_op_dcbz_l128_user
3543
#define gen_op_dcbz_l128_le_kernel    gen_op_dcbz_l128_kernel
3544
#define gen_op_dcbz_l128_le_hypv      gen_op_dcbz_l128_hypv
3545
#define gen_op_dcbz_l128_le_64_raw    gen_op_dcbz_l128_64_raw
3546
#define gen_op_dcbz_l128_le_64_user   gen_op_dcbz_l128_64_user
3547
#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3548
#define gen_op_dcbz_l128_le_64_hypv   gen_op_dcbz_l128_64_hypv
3549
        GEN_MEM_FUNCS(dcbz_l128),
3550
    },
3551
    /* tunable cache line size */
3552
    {
3553
#define gen_op_dcbz_le_raw            gen_op_dcbz_raw
3554
#define gen_op_dcbz_le_user           gen_op_dcbz_user
3555
#define gen_op_dcbz_le_kernel         gen_op_dcbz_kernel
3556
#define gen_op_dcbz_le_hypv           gen_op_dcbz_hypv
3557
#define gen_op_dcbz_le_64_raw         gen_op_dcbz_64_raw
3558
#define gen_op_dcbz_le_64_user        gen_op_dcbz_64_user
3559
#define gen_op_dcbz_le_64_kernel      gen_op_dcbz_64_kernel
3560
#define gen_op_dcbz_le_64_hypv        gen_op_dcbz_64_hypv
3561
        GEN_MEM_FUNCS(dcbz),
3562
    },
3563
};
3564

    
3565
static always_inline void handler_dcbz (DisasContext *ctx,
3566
                                        int dcache_line_size)
3567
{
3568
    int n;
3569

    
3570
    switch (dcache_line_size) {
3571
    case 32:
3572
        n = 0;
3573
        break;
3574
    case 64:
3575
        n = 1;
3576
        break;
3577
    case 128:
3578
        n = 2;
3579
        break;
3580
    default:
3581
        n = 3;
3582
        break;
3583
    }
3584
    op_dcbz(n);
3585
}
3586

    
3587
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3588
{
3589
    gen_addr_reg_index(ctx);
3590
    handler_dcbz(ctx, ctx->dcache_line_size);
3591
    gen_op_check_reservation();
3592
}
3593

    
3594
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3595
{
3596
    gen_addr_reg_index(ctx);
3597
    if (ctx->opcode & 0x00200000)
3598
        handler_dcbz(ctx, ctx->dcache_line_size);
3599
    else
3600
        handler_dcbz(ctx, -1);
3601
    gen_op_check_reservation();
3602
}
3603

    
3604
/* icbi */
3605
#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3606
#define gen_op_icbi_le_raw       gen_op_icbi_raw
3607
#define gen_op_icbi_le_user      gen_op_icbi_user
3608
#define gen_op_icbi_le_kernel    gen_op_icbi_kernel
3609
#define gen_op_icbi_le_hypv      gen_op_icbi_hypv
3610
#define gen_op_icbi_le_64_raw    gen_op_icbi_64_raw
3611
#define gen_op_icbi_le_64_user   gen_op_icbi_64_user
3612
#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3613
#define gen_op_icbi_le_64_hypv   gen_op_icbi_64_hypv
3614
static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3615
    GEN_MEM_FUNCS(icbi),
3616
};
3617

    
3618
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
3619
{
3620
    /* NIP cannot be restored if the memory exception comes from an helper */
3621
    gen_update_nip(ctx, ctx->nip - 4);
3622
    gen_addr_reg_index(ctx);
3623
    op_icbi();
3624
}
3625

    
3626
/* Optional: */
3627
/* dcba */
3628
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3629
{
3630
    /* interpreted as no-op */
3631
    /* XXX: specification say this is treated as a store by the MMU
3632
     *      but does not generate any exception
3633
     */
3634
}
3635

    
3636
/***                    Segment register manipulation                      ***/
3637
/* Supervisor only: */
3638
/* mfsr */
3639
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3640
{
3641
#if defined(CONFIG_USER_ONLY)
3642
    GEN_EXCP_PRIVREG(ctx);
3643
#else
3644
    if (unlikely(!ctx->supervisor)) {
3645
        GEN_EXCP_PRIVREG(ctx);
3646
        return;
3647
    }
3648
    gen_op_set_T1(SR(ctx->opcode));
3649
    gen_op_load_sr();
3650
    gen_op_store_T0_gpr(rD(ctx->opcode));
3651
#endif
3652
}
3653

    
3654
/* mfsrin */
3655
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
3656
{
3657
#if defined(CONFIG_USER_ONLY)
3658
    GEN_EXCP_PRIVREG(ctx);
3659
#else
3660
    if (unlikely(!ctx->supervisor)) {
3661
        GEN_EXCP_PRIVREG(ctx);
3662
        return;
3663
    }
3664
    gen_op_load_gpr_T1(rB(ctx->opcode));
3665
    gen_op_srli_T1(28);
3666
    gen_op_load_sr();
3667
    gen_op_store_T0_gpr(rD(ctx->opcode));
3668
#endif
3669
}
3670

    
3671
/* mtsr */
3672
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
3673
{
3674
#if defined(CONFIG_USER_ONLY)
3675
    GEN_EXCP_PRIVREG(ctx);
3676
#else
3677
    if (unlikely(!ctx->supervisor)) {
3678
        GEN_EXCP_PRIVREG(ctx);
3679
        return;
3680
    }
3681
    gen_op_load_gpr_T0(rS(ctx->opcode));
3682
    gen_op_set_T1(SR(ctx->opcode));
3683
    gen_op_store_sr();
3684
#endif
3685
}
3686

    
3687
/* mtsrin */
3688
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
3689
{
3690
#if defined(CONFIG_USER_ONLY)
3691
    GEN_EXCP_PRIVREG(ctx);
3692
#else
3693
    if (unlikely(!ctx->supervisor)) {
3694
        GEN_EXCP_PRIVREG(ctx);
3695
        return;
3696
    }
3697
    gen_op_load_gpr_T0(rS(ctx->opcode));
3698
    gen_op_load_gpr_T1(rB(ctx->opcode));
3699
    gen_op_srli_T1(28);
3700
    gen_op_store_sr();
3701
#endif
3702
}
3703

    
3704
#if defined(TARGET_PPC64)
3705
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3706
/* mfsr */
3707
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
3708
{
3709
#if defined(CONFIG_USER_ONLY)
3710
    GEN_EXCP_PRIVREG(ctx);
3711
#else
3712
    if (unlikely(!ctx->supervisor)) {
3713
        GEN_EXCP_PRIVREG(ctx);
3714
        return;
3715
    }
3716
    gen_op_set_T1(SR(ctx->opcode));
3717
    gen_op_load_slb();
3718
    gen_op_store_T0_gpr(rD(ctx->opcode));
3719
#endif
3720
}
3721

    
3722
/* mfsrin */
3723
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3724
             PPC_SEGMENT_64B)
3725
{
3726
#if defined(CONFIG_USER_ONLY)
3727
    GEN_EXCP_PRIVREG(ctx);
3728
#else
3729
    if (unlikely(!ctx->supervisor)) {
3730
        GEN_EXCP_PRIVREG(ctx);
3731
        return;
3732
    }
3733
    gen_op_load_gpr_T1(rB(ctx->opcode));
3734
    gen_op_srli_T1(28);
3735
    gen_op_load_slb();
3736
    gen_op_store_T0_gpr(rD(ctx->opcode));
3737
#endif
3738
}
3739

    
3740
/* mtsr */
3741
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
3742
{
3743
#if defined(CONFIG_USER_ONLY)
3744
    GEN_EXCP_PRIVREG(ctx);
3745
#else
3746
    if (unlikely(!ctx->supervisor)) {
3747
        GEN_EXCP_PRIVREG(ctx);
3748
        return;
3749
    }
3750
    gen_op_load_gpr_T0(rS(ctx->opcode));
3751
    gen_op_set_T1(SR(ctx->opcode));
3752
    gen_op_store_slb();
3753
#endif
3754
}
3755

    
3756
/* mtsrin */
3757
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3758
             PPC_SEGMENT_64B)
3759
{
3760
#if defined(CONFIG_USER_ONLY)
3761
    GEN_EXCP_PRIVREG(ctx);
3762
#else
3763
    if (unlikely(!ctx->supervisor)) {
3764
        GEN_EXCP_PRIVREG(ctx);
3765
        return;
3766
    }
3767
    gen_op_load_gpr_T0(rS(ctx->opcode));
3768
    gen_op_load_gpr_T1(rB(ctx->opcode));
3769
    gen_op_srli_T1(28);
3770
    gen_op_store_slb();
3771
#endif
3772
}
3773
#endif /* defined(TARGET_PPC64) */
3774

    
3775
/***                      Lookaside buffer management                      ***/
3776
/* Optional & supervisor only: */
3777
/* tlbia */
3778
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
3779
{
3780
#if defined(CONFIG_USER_ONLY)
3781
    GEN_EXCP_PRIVOPC(ctx);
3782
#else
3783
    if (unlikely(!ctx->supervisor)) {
3784
        GEN_EXCP_PRIVOPC(ctx);
3785
        return;
3786
    }
3787
    gen_op_tlbia();
3788
#endif
3789
}
3790

    
3791
/* tlbie */
3792
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
3793
{
3794
#if defined(CONFIG_USER_ONLY)
3795
    GEN_EXCP_PRIVOPC(ctx);
3796
#else
3797
    if (unlikely(!ctx->supervisor)) {
3798
        GEN_EXCP_PRIVOPC(ctx);
3799
        return;
3800
    }
3801
    gen_op_load_gpr_T0(rB(ctx->opcode));
3802
#if defined(TARGET_PPC64)
3803
    if (ctx->sf_mode)
3804
        gen_op_tlbie_64();
3805
    else
3806
#endif
3807
        gen_op_tlbie();
3808
#endif
3809
}
3810

    
3811
/* tlbsync */
3812
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
3813
{
3814
#if defined(CONFIG_USER_ONLY)
3815
    GEN_EXCP_PRIVOPC(ctx);
3816
#else
3817
    if (unlikely(!ctx->supervisor)) {
3818
        GEN_EXCP_PRIVOPC(ctx);
3819
        return;
3820
    }
3821
    /* This has no effect: it should ensure that all previous
3822
     * tlbie have completed
3823
     */
3824
    GEN_STOP(ctx);
3825
#endif
3826
}
3827

    
3828
#if defined(TARGET_PPC64)
3829
/* slbia */
3830
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
3831
{
3832
#if defined(CONFIG_USER_ONLY)
3833
    GEN_EXCP_PRIVOPC(ctx);
3834
#else
3835
    if (unlikely(!ctx->supervisor)) {
3836
        GEN_EXCP_PRIVOPC(ctx);
3837
        return;
3838
    }
3839
    gen_op_slbia();
3840
#endif
3841
}
3842

    
3843
/* slbie */
3844
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3845
{
3846
#if defined(CONFIG_USER_ONLY)
3847
    GEN_EXCP_PRIVOPC(ctx);
3848
#else
3849
    if (unlikely(!ctx->supervisor)) {
3850
        GEN_EXCP_PRIVOPC(ctx);
3851
        return;
3852
    }
3853
    gen_op_load_gpr_T0(rB(ctx->opcode));
3854
    gen_op_slbie();
3855
#endif
3856
}
3857
#endif
3858

    
3859
/***                              External control                         ***/
3860
/* Optional: */
3861
#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3862
#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
3863
static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
3864
    GEN_MEM_FUNCS(eciwx),
3865
};
3866
static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
3867
    GEN_MEM_FUNCS(ecowx),
3868
};
3869

    
3870
/* eciwx */
3871
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
3872
{
3873
    /* Should check EAR[E] & alignment ! */
3874
    gen_addr_reg_index(ctx);
3875
    op_eciwx();
3876
    gen_op_store_T0_gpr(rD(ctx->opcode));
3877
}
3878

    
3879
/* ecowx */
3880
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3881
{
3882
    /* Should check EAR[E] & alignment ! */
3883
    gen_addr_reg_index(ctx);
3884
    gen_op_load_gpr_T1(rS(ctx->opcode));
3885
    op_ecowx();
3886
}
3887

    
3888
/* PowerPC 601 specific instructions */
3889
/* abs - abs. */
3890
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3891
{
3892
    gen_op_load_gpr_T0(rA(ctx->opcode));
3893
    gen_op_POWER_abs();
3894
    gen_op_store_T0_gpr(rD(ctx->opcode));
3895
    if (unlikely(Rc(ctx->opcode) != 0))
3896
        gen_set_Rc0(ctx);
3897
}
3898

    
3899
/* abso - abso. */
3900
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3901
{
3902
    gen_op_load_gpr_T0(rA(ctx->opcode));
3903
    gen_op_POWER_abso();
3904
    gen_op_store_T0_gpr(rD(ctx->opcode));
3905
    if (unlikely(Rc(ctx->opcode) != 0))
3906
        gen_set_Rc0(ctx);
3907
}
3908

    
3909
/* clcs */
3910
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
3911
{
3912
    gen_op_load_gpr_T0(rA(ctx->opcode));
3913
    gen_op_POWER_clcs();
3914
    /* Rc=1 sets CR0 to an undefined state */
3915
    gen_op_store_T0_gpr(rD(ctx->opcode));
3916
}
3917

    
3918
/* div - div. */
3919
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3920
{
3921
    gen_op_load_gpr_T0(rA(ctx->opcode));
3922
    gen_op_load_gpr_T1(rB(ctx->opcode));
3923
    gen_op_POWER_div();
3924
    gen_op_store_T0_gpr(rD(ctx->opcode));
3925
    if (unlikely(Rc(ctx->opcode) != 0))
3926
        gen_set_Rc0(ctx);
3927
}
3928

    
3929
/* divo - divo. */
3930
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3931
{
3932
    gen_op_load_gpr_T0(rA(ctx->opcode));
3933
    gen_op_load_gpr_T1(rB(ctx->opcode));
3934
    gen_op_POWER_divo();
3935
    gen_op_store_T0_gpr(rD(ctx->opcode));
3936
    if (unlikely(Rc(ctx->opcode) != 0))
3937
        gen_set_Rc0(ctx);
3938
}
3939

    
3940
/* divs - divs. */
3941
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3942
{
3943
    gen_op_load_gpr_T0(rA(ctx->opcode));
3944
    gen_op_load_gpr_T1(rB(ctx->opcode));
3945
    gen_op_POWER_divs();
3946
    gen_op_store_T0_gpr(rD(ctx->opcode));
3947
    if (unlikely(Rc(ctx->opcode) != 0))
3948
        gen_set_Rc0(ctx);
3949
}
3950

    
3951
/* divso - divso. */
3952
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3953
{
3954
    gen_op_load_gpr_T0(rA(ctx->opcode));
3955
    gen_op_load_gpr_T1(rB(ctx->opcode));
3956
    gen_op_POWER_divso();
3957
    gen_op_store_T0_gpr(rD(ctx->opcode));
3958
    if (unlikely(Rc(ctx->opcode) != 0))
3959
        gen_set_Rc0(ctx);
3960
}
3961

    
3962
/* doz - doz. */
3963
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3964
{
3965
    gen_op_load_gpr_T0(rA(ctx->opcode));
3966
    gen_op_load_gpr_T1(rB(ctx->opcode));
3967
    gen_op_POWER_doz();
3968
    gen_op_store_T0_gpr(rD(ctx->opcode));
3969
    if (unlikely(Rc(ctx->opcode) != 0))
3970
        gen_set_Rc0(ctx);
3971
}
3972

    
3973
/* dozo - dozo. */
3974
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3975
{
3976
    gen_op_load_gpr_T0(rA(ctx->opcode));
3977
    gen_op_load_gpr_T1(rB(ctx->opcode));
3978
    gen_op_POWER_dozo();
3979
    gen_op_store_T0_gpr(rD(ctx->opcode));
3980
    if (unlikely(Rc(ctx->opcode) != 0))
3981
        gen_set_Rc0(ctx);
3982
}
3983

    
3984
/* dozi */
3985
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
3986
{
3987
    gen_op_load_gpr_T0(rA(ctx->opcode));
3988
    gen_op_set_T1(SIMM(ctx->opcode));
3989
    gen_op_POWER_doz();
3990
    gen_op_store_T0_gpr(rD(ctx->opcode));
3991
}
3992

    
3993
/* As lscbx load from memory byte after byte, it's always endian safe.
3994
 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3995
 */
3996
#define op_POWER_lscbx(start, ra, rb)                                         \
3997
(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
3998
#define gen_op_POWER_lscbx_64_raw       gen_op_POWER_lscbx_raw
3999
#define gen_op_POWER_lscbx_64_user      gen_op_POWER_lscbx_user
4000
#define gen_op_POWER_lscbx_64_kernel    gen_op_POWER_lscbx_kernel
4001
#define gen_op_POWER_lscbx_64_hypv      gen_op_POWER_lscbx_hypv
4002
#define gen_op_POWER_lscbx_le_raw       gen_op_POWER_lscbx_raw
4003
#define gen_op_POWER_lscbx_le_user      gen_op_POWER_lscbx_user
4004
#define gen_op_POWER_lscbx_le_kernel    gen_op_POWER_lscbx_kernel
4005
#define gen_op_POWER_lscbx_le_hypv      gen_op_POWER_lscbx_hypv
4006
#define gen_op_POWER_lscbx_le_64_raw    gen_op_POWER_lscbx_raw
4007
#define gen_op_POWER_lscbx_le_64_user   gen_op_POWER_lscbx_user
4008
#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4009
#define gen_op_POWER_lscbx_le_64_hypv   gen_op_POWER_lscbx_hypv
4010
static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4011
    GEN_MEM_FUNCS(POWER_lscbx),
4012
};
4013

    
4014
/* lscbx - lscbx. */
4015
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4016
{
4017
    int ra = rA(ctx->opcode);
4018
    int rb = rB(ctx->opcode);
4019

    
4020
    gen_addr_reg_index(ctx);
4021
    if (ra == 0) {
4022
        ra = rb;
4023
    }
4024
    /* NIP cannot be restored if the memory exception comes from an helper */
4025
    gen_update_nip(ctx, ctx->nip - 4);
4026
    gen_op_load_xer_bc();
4027
    gen_op_load_xer_cmp();
4028
    op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4029
    gen_op_store_xer_bc();
4030
    if (unlikely(Rc(ctx->opcode) != 0))
4031
        gen_set_Rc0(ctx);
4032
}
4033

    
4034
/* maskg - maskg. */
4035
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4036
{
4037
    gen_op_load_gpr_T0(rS(ctx->opcode));
4038
    gen_op_load_gpr_T1(rB(ctx->opcode));
4039
    gen_op_POWER_maskg();
4040
    gen_op_store_T0_gpr(rA(ctx->opcode));
4041
    if (unlikely(Rc(ctx->opcode) != 0))
4042
        gen_set_Rc0(ctx);
4043
}
4044

    
4045
/* maskir - maskir. */
4046
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4047
{
4048
    gen_op_load_gpr_T0(rA(ctx->opcode));
4049
    gen_op_load_gpr_T1(rS(ctx->opcode));
4050
    gen_op_load_gpr_T2(rB(ctx->opcode));
4051
    gen_op_POWER_maskir();
4052
    gen_op_store_T0_gpr(rA(ctx->opcode));
4053
    if (unlikely(Rc(ctx->opcode) != 0))
4054
        gen_set_Rc0(ctx);
4055
}
4056

    
4057
/* mul - mul. */
4058
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4059
{
4060
    gen_op_load_gpr_T0(rA(ctx->opcode));
4061
    gen_op_load_gpr_T1(rB(ctx->opcode));
4062
    gen_op_POWER_mul();
4063
    gen_op_store_T0_gpr(rD(ctx->opcode));
4064
    if (unlikely(Rc(ctx->opcode) != 0))
4065
        gen_set_Rc0(ctx);
4066
}
4067

    
4068
/* mulo - mulo. */
4069
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4070
{
4071
    gen_op_load_gpr_T0(rA(ctx->opcode));
4072
    gen_op_load_gpr_T1(rB(ctx->opcode));
4073
    gen_op_POWER_mulo();
4074
    gen_op_store_T0_gpr(rD(ctx->opcode));
4075
    if (unlikely(Rc(ctx->opcode) != 0))
4076
        gen_set_Rc0(ctx);
4077
}
4078

    
4079
/* nabs - nabs. */
4080
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4081
{
4082
    gen_op_load_gpr_T0(rA(ctx->opcode));
4083
    gen_op_POWER_nabs();
4084
    gen_op_store_T0_gpr(rD(ctx->opcode));
4085
    if (unlikely(Rc(ctx->opcode) != 0))
4086
        gen_set_Rc0(ctx);
4087
}
4088

    
4089
/* nabso - nabso. */
4090
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4091
{
4092
    gen_op_load_gpr_T0(rA(ctx->opcode));
4093
    gen_op_POWER_nabso();
4094
    gen_op_store_T0_gpr(rD(ctx->opcode));
4095
    if (unlikely(Rc(ctx->opcode) != 0))
4096
        gen_set_Rc0(ctx);
4097
}
4098

    
4099
/* rlmi - rlmi. */
4100
GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4101
{
4102
    uint32_t mb, me;
4103

    
4104
    mb = MB(ctx->opcode);
4105
    me = ME(ctx->opcode);
4106
    gen_op_load_gpr_T0(rS(ctx->opcode));
4107
    gen_op_load_gpr_T1(rA(ctx->opcode));
4108
    gen_op_load_gpr_T2(rB(ctx->opcode));
4109
    gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4110
    gen_op_store_T0_gpr(rA(ctx->opcode));
4111
    if (unlikely(Rc(ctx->opcode) != 0))
4112
        gen_set_Rc0(ctx);
4113
}
4114

    
4115
/* rrib - rrib. */
4116
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4117
{
4118
    gen_op_load_gpr_T0(rS(ctx->opcode));
4119
    gen_op_load_gpr_T1(rA(ctx->opcode));
4120
    gen_op_load_gpr_T2(rB(ctx->opcode));
4121
    gen_op_POWER_rrib();
4122
    gen_op_store_T0_gpr(rA(ctx->opcode));
4123
    if (unlikely(Rc(ctx->opcode) != 0))
4124
        gen_set_Rc0(ctx);
4125
}
4126

    
4127
/* sle - sle. */
4128
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4129
{
4130
    gen_op_load_gpr_T0(rS(ctx->opcode));
4131
    gen_op_load_gpr_T1(rB(ctx->opcode));
4132
    gen_op_POWER_sle();
4133
    gen_op_store_T0_gpr(rA(ctx->opcode));
4134
    if (unlikely(Rc(ctx->opcode) != 0))
4135
        gen_set_Rc0(ctx);
4136
}
4137

    
4138
/* sleq - sleq. */
4139
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4140
{
4141
    gen_op_load_gpr_T0(rS(ctx->opcode));
4142
    gen_op_load_gpr_T1(rB(ctx->opcode));
4143
    gen_op_POWER_sleq();
4144
    gen_op_store_T0_gpr(rA(ctx->opcode));
4145
    if (unlikely(Rc(ctx->opcode) != 0))
4146
        gen_set_Rc0(ctx);
4147
}
4148

    
4149
/* sliq - sliq. */
4150
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4151
{
4152
    gen_op_load_gpr_T0(rS(ctx->opcode));
4153
    gen_op_set_T1(SH(ctx->opcode));
4154
    gen_op_POWER_sle();
4155
    gen_op_store_T0_gpr(rA(ctx->opcode));
4156
    if (unlikely(Rc(ctx->opcode) != 0))
4157
        gen_set_Rc0(ctx);
4158
}
4159

    
4160
/* slliq - slliq. */
4161
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4162
{
4163
    gen_op_load_gpr_T0(rS(ctx->opcode));
4164
    gen_op_set_T1(SH(ctx->opcode));
4165
    gen_op_POWER_sleq();
4166
    gen_op_store_T0_gpr(rA(ctx->opcode));
4167
    if (unlikely(Rc(ctx->opcode) != 0))
4168
        gen_set_Rc0(ctx);
4169
}
4170

    
4171
/* sllq - sllq. */
4172
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4173
{
4174
    gen_op_load_gpr_T0(rS(ctx->opcode));
4175
    gen_op_load_gpr_T1(rB(ctx->opcode));
4176
    gen_op_POWER_sllq();
4177
    gen_op_store_T0_gpr(rA(ctx->opcode));
4178
    if (unlikely(Rc(ctx->opcode) != 0))
4179
        gen_set_Rc0(ctx);
4180
}
4181

    
4182
/* slq - slq. */
4183
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4184
{
4185
    gen_op_load_gpr_T0(rS(ctx->opcode));
4186
    gen_op_load_gpr_T1(rB(ctx->opcode));
4187
    gen_op_POWER_slq();
4188
    gen_op_store_T0_gpr(rA(ctx->opcode));
4189
    if (unlikely(Rc(ctx->opcode) != 0))
4190
        gen_set_Rc0(ctx);
4191
}
4192

    
4193
/* sraiq - sraiq. */
4194
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4195
{
4196
    gen_op_load_gpr_T0(rS(ctx->opcode));
4197
    gen_op_set_T1(SH(ctx->opcode));
4198
    gen_op_POWER_sraq();
4199
    gen_op_store_T0_gpr(rA(ctx->opcode));
4200
    if (unlikely(Rc(ctx->opcode) != 0))
4201
        gen_set_Rc0(ctx);
4202
}
4203

    
4204
/* sraq - sraq. */
4205
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4206
{
4207
    gen_op_load_gpr_T0(rS(ctx->opcode));
4208
    gen_op_load_gpr_T1(rB(ctx->opcode));
4209
    gen_op_POWER_sraq();
4210
    gen_op_store_T0_gpr(rA(ctx->opcode));
4211
    if (unlikely(Rc(ctx->opcode) != 0))
4212
        gen_set_Rc0(ctx);
4213
}
4214

    
4215
/* sre - sre. */
4216
GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4217
{
4218
    gen_op_load_gpr_T0(rS(ctx->opcode));
4219
    gen_op_load_gpr_T1(rB(ctx->opcode));
4220
    gen_op_POWER_sre();
4221
    gen_op_store_T0_gpr(rA(ctx->opcode));
4222
    if (unlikely(Rc(ctx->opcode) != 0))
4223
        gen_set_Rc0(ctx);
4224
}
4225

    
4226
/* srea - srea. */
4227
GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4228
{
4229
    gen_op_load_gpr_T0(rS(ctx->opcode));
4230
    gen_op_load_gpr_T1(rB(ctx->opcode));
4231
    gen_op_POWER_srea();
4232
    gen_op_store_T0_gpr(rA(ctx->opcode));
4233
    if (unlikely(Rc(ctx->opcode) != 0))
4234
        gen_set_Rc0(ctx);
4235
}
4236

    
4237
/* sreq */
4238
GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4239
{
4240
    gen_op_load_gpr_T0(rS(ctx->opcode));
4241
    gen_op_load_gpr_T1(rB(ctx->opcode));
4242
    gen_op_POWER_sreq();
4243
    gen_op_store_T0_gpr(rA(ctx->opcode));
4244
    if (unlikely(Rc(ctx->opcode) != 0))
4245
        gen_set_Rc0(ctx);
4246
}
4247

    
4248
/* sriq */
4249
GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4250
{
4251
    gen_op_load_gpr_T0(rS(ctx->opcode));
4252
    gen_op_set_T1(SH(ctx->opcode));
4253
    gen_op_POWER_srq();
4254
    gen_op_store_T0_gpr(rA(ctx->opcode));
4255
    if (unlikely(Rc(ctx->opcode) != 0))
4256
        gen_set_Rc0(ctx);
4257
}
4258

    
4259
/* srliq */
4260
GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4261
{
4262
    gen_op_load_gpr_T0(rS(ctx->opcode));
4263
    gen_op_load_gpr_T1(rB(ctx->opcode));
4264
    gen_op_set_T1(SH(ctx->opcode));
4265
    gen_op_POWER_srlq();
4266
    gen_op_store_T0_gpr(rA(ctx->opcode));
4267
    if (unlikely(Rc(ctx->opcode) != 0))
4268
        gen_set_Rc0(ctx);
4269
}
4270

    
4271
/* srlq */
4272
GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4273
{
4274
    gen_op_load_gpr_T0(rS(ctx->opcode));
4275
    gen_op_load_gpr_T1(rB(ctx->opcode));
4276
    gen_op_POWER_srlq();
4277
    gen_op_store_T0_gpr(rA(ctx->opcode));
4278
    if (unlikely(Rc(ctx->opcode) != 0))
4279
        gen_set_Rc0(ctx);
4280
}
4281

    
4282
/* srq */
4283
GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4284
{
4285
    gen_op_load_gpr_T0(rS(ctx->opcode));
4286
    gen_op_load_gpr_T1(rB(ctx->opcode));
4287
    gen_op_POWER_srq();
4288
    gen_op_store_T0_gpr(rA(ctx->opcode));
4289
    if (unlikely(Rc(ctx->opcode) != 0))
4290
        gen_set_Rc0(ctx);
4291
}
4292

    
4293
/* PowerPC 602 specific instructions */
4294
/* dsa  */
4295
GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4296
{
4297
    /* XXX: TODO */
4298
    GEN_EXCP_INVAL(ctx);
4299
}
4300

    
4301
/* esa */
4302
GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4303
{
4304
    /* XXX: TODO */
4305
    GEN_EXCP_INVAL(ctx);
4306
}
4307

    
4308
/* mfrom */
4309
GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4310
{
4311
#if defined(CONFIG_USER_ONLY)
4312
    GEN_EXCP_PRIVOPC(ctx);
4313
#else
4314
    if (unlikely(!ctx->supervisor)) {
4315
        GEN_EXCP_PRIVOPC(ctx);
4316
        return;
4317
    }
4318
    gen_op_load_gpr_T0(rA(ctx->opcode));
4319
    gen_op_602_mfrom();
4320
    gen_op_store_T0_gpr(rD(ctx->opcode));
4321
#endif
4322
}
4323

    
4324
/* 602 - 603 - G2 TLB management */
4325
/* tlbld */
4326
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4327
{
4328
#if defined(CONFIG_USER_ONLY)
4329
    GEN_EXCP_PRIVOPC(ctx);
4330
#else
4331
    if (unlikely(!ctx->supervisor)) {
4332
        GEN_EXCP_PRIVOPC(ctx);
4333
        return;
4334
    }
4335
    gen_op_load_gpr_T0(rB(ctx->opcode));
4336
    gen_op_6xx_tlbld();
4337
#endif
4338
}
4339

    
4340
/* tlbli */
4341
GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4342
{
4343
#if defined(CONFIG_USER_ONLY)
4344
    GEN_EXCP_PRIVOPC(ctx);
4345
#else
4346
    if (unlikely(!ctx->supervisor)) {
4347
        GEN_EXCP_PRIVOPC(ctx);
4348
        return;
4349
    }
4350
    gen_op_load_gpr_T0(rB(ctx->opcode));
4351
    gen_op_6xx_tlbli();
4352
#endif
4353
}
4354

    
4355
/* 74xx TLB management */
4356
/* tlbld */
4357
GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4358
{
4359
#if defined(CONFIG_USER_ONLY)
4360
    GEN_EXCP_PRIVOPC(ctx);
4361
#else
4362
    if (unlikely(!ctx->supervisor)) {
4363
        GEN_EXCP_PRIVOPC(ctx);
4364
        return;
4365
    }
4366
    gen_op_load_gpr_T0(rB(ctx->opcode));
4367
    gen_op_74xx_tlbld();
4368
#endif
4369
}
4370

    
4371
/* tlbli */
4372
GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4373
{
4374
#if defined(CONFIG_USER_ONLY)
4375
    GEN_EXCP_PRIVOPC(ctx);
4376
#else
4377
    if (unlikely(!ctx->supervisor)) {
4378
        GEN_EXCP_PRIVOPC(ctx);
4379
        return;
4380
    }
4381
    gen_op_load_gpr_T0(rB(ctx->opcode));
4382
    gen_op_74xx_tlbli();
4383
#endif
4384
}
4385

    
4386
/* POWER instructions not in PowerPC 601 */
4387
/* clf */
4388
GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4389
{
4390
    /* Cache line flush: implemented as no-op */
4391
}
4392

    
4393
/* cli */
4394
GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4395
{
4396
    /* Cache line invalidate: privileged and treated as no-op */
4397
#if defined(CONFIG_USER_ONLY)
4398
    GEN_EXCP_PRIVOPC(ctx);
4399
#else
4400
    if (unlikely(!ctx->supervisor)) {
4401
        GEN_EXCP_PRIVOPC(ctx);
4402
        return;
4403
    }
4404
#endif
4405
}
4406

    
4407
/* dclst */
4408
GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4409
{
4410
    /* Data cache line store: treated as no-op */
4411
}
4412

    
4413
GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4414
{
4415
#if defined(CONFIG_USER_ONLY)
4416
    GEN_EXCP_PRIVOPC(ctx);
4417
#else
4418
    if (unlikely(!ctx->supervisor)) {
4419
        GEN_EXCP_PRIVOPC(ctx);
4420
        return;
4421
    }
4422
    int ra = rA(ctx->opcode);
4423
    int rd = rD(ctx->opcode);
4424

    
4425
    gen_addr_reg_index(ctx);
4426
    gen_op_POWER_mfsri();
4427
    gen_op_store_T0_gpr(rd);
4428
    if (ra != 0 && ra != rd)
4429
        gen_op_store_T1_gpr(ra);
4430
#endif
4431
}
4432

    
4433
GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4434
{
4435
#if defined(CONFIG_USER_ONLY)
4436
    GEN_EXCP_PRIVOPC(ctx);
4437
#else
4438
    if (unlikely(!ctx->supervisor)) {
4439
        GEN_EXCP_PRIVOPC(ctx);
4440
        return;
4441
    }
4442
    gen_addr_reg_index(ctx);
4443
    gen_op_POWER_rac();
4444
    gen_op_store_T0_gpr(rD(ctx->opcode));
4445
#endif
4446
}
4447

    
4448
GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4449
{
4450
#if defined(CONFIG_USER_ONLY)
4451
    GEN_EXCP_PRIVOPC(ctx);
4452
#else
4453
    if (unlikely(!ctx->supervisor)) {
4454
        GEN_EXCP_PRIVOPC(ctx);
4455
        return;
4456
    }
4457
    gen_op_POWER_rfsvc();
4458
    GEN_SYNC(ctx);
4459
#endif
4460
}
4461

    
4462
/* svc is not implemented for now */
4463

    
4464
/* POWER2 specific instructions */
4465
/* Quad manipulation (load/store two floats at a time) */
4466
/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
4467
#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4468
#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4469
#define gen_op_POWER2_lfq_64_raw        gen_op_POWER2_lfq_raw
4470
#define gen_op_POWER2_lfq_64_user       gen_op_POWER2_lfq_user
4471
#define gen_op_POWER2_lfq_64_kernel     gen_op_POWER2_lfq_kernel
4472
#define gen_op_POWER2_lfq_64_hypv       gen_op_POWER2_lfq_hypv
4473
#define gen_op_POWER2_lfq_le_64_raw     gen_op_POWER2_lfq_le_raw
4474
#define gen_op_POWER2_lfq_le_64_user    gen_op_POWER2_lfq_le_user
4475
#define gen_op_POWER2_lfq_le_64_kernel  gen_op_POWER2_lfq_le_kernel
4476
#define gen_op_POWER2_lfq_le_64_hypv    gen_op_POWER2_lfq_le_hypv
4477
#define gen_op_POWER2_stfq_64_raw       gen_op_POWER2_stfq_raw
4478
#define gen_op_POWER2_stfq_64_user      gen_op_POWER2_stfq_user
4479
#define gen_op_POWER2_stfq_64_kernel    gen_op_POWER2_stfq_kernel
4480
#define gen_op_POWER2_stfq_64_hypv      gen_op_POWER2_stfq_hypv
4481
#define gen_op_POWER2_stfq_le_64_raw    gen_op_POWER2_stfq_le_raw
4482
#define gen_op_POWER2_stfq_le_64_user   gen_op_POWER2_stfq_le_user
4483
#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4484
#define gen_op_POWER2_stfq_le_64_hypv   gen_op_POWER2_stfq_le_hypv
4485
static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4486
    GEN_MEM_FUNCS(POWER2_lfq),
4487
};
4488
static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4489
    GEN_MEM_FUNCS(POWER2_stfq),
4490
};
4491

    
4492
/* lfq */
4493
GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4494
{
4495
    /* NIP cannot be restored if the memory exception comes from an helper */
4496
    gen_update_nip(ctx, ctx->nip - 4);
4497
    gen_addr_imm_index(ctx, 0);
4498
    op_POWER2_lfq();
4499
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4500
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4501
}
4502

    
4503
/* lfqu */
4504
GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4505
{
4506
    int ra = rA(ctx->opcode);
4507

    
4508
    /* NIP cannot be restored if the memory exception comes from an helper */
4509
    gen_update_nip(ctx, ctx->nip - 4);
4510
    gen_addr_imm_index(ctx, 0);
4511
    op_POWER2_lfq();
4512
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4513
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4514
    if (ra != 0)
4515
        gen_op_store_T0_gpr(ra);
4516
}
4517

    
4518
/* lfqux */
4519
GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4520
{
4521
    int ra = rA(ctx->opcode);
4522

    
4523
    /* NIP cannot be restored if the memory exception comes from an helper */
4524
    gen_update_nip(ctx, ctx->nip - 4);
4525
    gen_addr_reg_index(ctx);
4526
    op_POWER2_lfq();
4527
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4528
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4529
    if (ra != 0)
4530
        gen_op_store_T0_gpr(ra);
4531
}
4532

    
4533
/* lfqx */
4534
GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4535
{
4536
    /* NIP cannot be restored if the memory exception comes from an helper */
4537
    gen_update_nip(ctx, ctx->nip - 4);
4538
    gen_addr_reg_index(ctx);
4539
    op_POWER2_lfq();
4540
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4541
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4542
}
4543

    
4544
/* stfq */
4545
GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4546
{
4547
    /* NIP cannot be restored if the memory exception comes from an helper */
4548
    gen_update_nip(ctx, ctx->nip - 4);
4549
    gen_addr_imm_index(ctx, 0);
4550
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4551
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4552
    op_POWER2_stfq();
4553
}
4554

    
4555
/* stfqu */
4556
GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4557
{
4558
    int ra = rA(ctx->opcode);
4559

    
4560
    /* NIP cannot be restored if the memory exception comes from an helper */
4561
    gen_update_nip(ctx, ctx->nip - 4);
4562
    gen_addr_imm_index(ctx, 0);
4563
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4564
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4565
    op_POWER2_stfq();
4566
    if (ra != 0)
4567
        gen_op_store_T0_gpr(ra);
4568
}
4569

    
4570
/* stfqux */
4571
GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4572
{
4573
    int ra = rA(ctx->opcode);
4574

    
4575
    /* NIP cannot be restored if the memory exception comes from an helper */
4576
    gen_update_nip(ctx, ctx->nip - 4);
4577
    gen_addr_reg_index(ctx);
4578
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4579
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4580
    op_POWER2_stfq();
4581
    if (ra != 0)
4582
        gen_op_store_T0_gpr(ra);
4583
}
4584

    
4585
/* stfqx */
4586
GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4587
{
4588
    /* NIP cannot be restored if the memory exception comes from an helper */
4589
    gen_update_nip(ctx, ctx->nip - 4);
4590
    gen_addr_reg_index(ctx);
4591
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4592
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4593
    op_POWER2_stfq();
4594
}
4595

    
4596
/* BookE specific instructions */
4597
/* XXX: not implemented on 440 ? */
4598
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
4599
{
4600
    /* XXX: TODO */
4601
    GEN_EXCP_INVAL(ctx);
4602
}
4603

    
4604
/* XXX: not implemented on 440 ? */
4605
GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
4606
{
4607
#if defined(CONFIG_USER_ONLY)
4608
    GEN_EXCP_PRIVOPC(ctx);
4609
#else
4610
    if (unlikely(!ctx->supervisor)) {
4611
        GEN_EXCP_PRIVOPC(ctx);
4612
        return;
4613
    }
4614
    gen_addr_reg_index(ctx);
4615
    /* Use the same micro-ops as for tlbie */
4616
#if defined(TARGET_PPC64)
4617
    if (ctx->sf_mode)
4618
        gen_op_tlbie_64();
4619
    else
4620
#endif
4621
        gen_op_tlbie();
4622
#endif
4623
}
4624

    
4625
/* All 405 MAC instructions are translated here */
4626
static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4627
                                                int opc2, int opc3,
4628
                                                int ra, int rb, int rt, int Rc)
4629
{
4630
    gen_op_load_gpr_T0(ra);
4631
    gen_op_load_gpr_T1(rb);
4632
    switch (opc3 & 0x0D) {
4633
    case 0x05:
4634
        /* macchw    - macchw.    - macchwo   - macchwo.   */
4635
        /* macchws   - macchws.   - macchwso  - macchwso.  */
4636
        /* nmacchw   - nmacchw.   - nmacchwo  - nmacchwo.  */
4637
        /* nmacchws  - nmacchws.  - nmacchwso - nmacchwso. */
4638
        /* mulchw - mulchw. */
4639
        gen_op_405_mulchw();
4640
        break;
4641
    case 0x04:
4642
        /* macchwu   - macchwu.   - macchwuo  - macchwuo.  */
4643
        /* macchwsu  - macchwsu.  - macchwsuo - macchwsuo. */
4644
        /* mulchwu - mulchwu. */
4645
        gen_op_405_mulchwu();
4646
        break;
4647
    case 0x01:
4648
        /* machhw    - machhw.    - machhwo   - machhwo.   */
4649
        /* machhws   - machhws.   - machhwso  - machhwso.  */
4650
        /* nmachhw   - nmachhw.   - nmachhwo  - nmachhwo.  */
4651
        /* nmachhws  - nmachhws.  - nmachhwso - nmachhwso. */
4652
        /* mulhhw - mulhhw. */
4653
        gen_op_405_mulhhw();
4654
        break;
4655
    case 0x00:
4656
        /* machhwu   - machhwu.   - machhwuo  - machhwuo.  */
4657
        /* machhwsu  - machhwsu.  - machhwsuo - machhwsuo. */
4658
        /* mulhhwu - mulhhwu. */
4659
        gen_op_405_mulhhwu();
4660
        break;
4661
    case 0x0D:
4662
        /* maclhw    - maclhw.    - maclhwo   - maclhwo.   */
4663
        /* maclhws   - maclhws.   - maclhwso  - maclhwso.  */
4664
        /* nmaclhw   - nmaclhw.   - nmaclhwo  - nmaclhwo.  */
4665
        /* nmaclhws  - nmaclhws.  - nmaclhwso - nmaclhwso. */
4666
        /* mullhw - mullhw. */
4667
        gen_op_405_mullhw();
4668
        break;
4669
    case 0x0C:
4670
        /* maclhwu   - maclhwu.   - maclhwuo  - maclhwuo.  */
4671
        /* maclhwsu  - maclhwsu.  - maclhwsuo - maclhwsuo. */
4672
        /* mullhwu - mullhwu. */
4673
        gen_op_405_mullhwu();
4674
        break;
4675
    }
4676
    if (opc2 & 0x02) {
4677
        /* nmultiply-and-accumulate (0x0E) */
4678
        gen_op_neg();
4679
    }
4680
    if (opc2 & 0x04) {
4681
        /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4682
        gen_op_load_gpr_T2(rt);
4683
        gen_op_move_T1_T0();
4684
        gen_op_405_add_T0_T2();
4685
    }
4686
    if (opc3 & 0x10) {
4687
        /* Check overflow */
4688
        if (opc3 & 0x01)
4689
            gen_op_check_addo();
4690
        else
4691
            gen_op_405_check_ovu();
4692
    }
4693
    if (opc3 & 0x02) {
4694
        /* Saturate */
4695
        if (opc3 & 0x01)
4696
            gen_op_405_check_sat();
4697
        else
4698
            gen_op_405_check_satu();
4699
    }
4700
    gen_op_store_T0_gpr(rt);
4701
    if (unlikely(Rc) != 0) {
4702
        /* Update Rc0 */
4703
        gen_set_Rc0(ctx);
4704
    }
4705
}
4706

    
4707
#define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
4708
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)                  \
4709
{                                                                             \
4710
    gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode),   \
4711
                         rD(ctx->opcode), Rc(ctx->opcode));                   \
4712
}
4713

    
4714
/* macchw    - macchw.    */
4715
GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
4716
/* macchwo   - macchwo.   */
4717
GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
4718
/* macchws   - macchws.   */
4719
GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
4720
/* macchwso  - macchwso.  */
4721
GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
4722
/* macchwsu  - macchwsu.  */
4723
GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
4724
/* macchwsuo - macchwsuo. */
4725
GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
4726
/* macchwu   - macchwu.   */
4727
GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
4728
/* macchwuo  - macchwuo.  */
4729
GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
4730
/* machhw    - machhw.    */
4731
GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
4732
/* machhwo   - machhwo.   */
4733
GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
4734
/* machhws   - machhws.   */
4735
GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
4736
/* machhwso  - machhwso.  */
4737
GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
4738
/* machhwsu  - machhwsu.  */
4739
GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
4740
/* machhwsuo - machhwsuo. */
4741
GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
4742
/* machhwu   - machhwu.   */
4743
GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
4744
/* machhwuo  - machhwuo.  */
4745
GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
4746
/* maclhw    - maclhw.    */
4747
GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
4748
/* maclhwo   - maclhwo.   */
4749
GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
4750
/* maclhws   - maclhws.   */
4751
GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
4752
/* maclhwso  - maclhwso.  */
4753
GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
4754
/* maclhwu   - maclhwu.   */
4755
GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
4756
/* maclhwuo  - maclhwuo.  */
4757
GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
4758
/* maclhwsu  - maclhwsu.  */
4759
GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
4760
/* maclhwsuo - maclhwsuo. */
4761
GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
4762
/* nmacchw   - nmacchw.   */
4763
GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
4764
/* nmacchwo  - nmacchwo.  */
4765
GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
4766
/* nmacchws  - nmacchws.  */
4767
GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
4768
/* nmacchwso - nmacchwso. */
4769
GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
4770
/* nmachhw   - nmachhw.   */
4771
GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
4772
/* nmachhwo  - nmachhwo.  */
4773
GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
4774
/* nmachhws  - nmachhws.  */
4775
GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
4776
/* nmachhwso - nmachhwso. */
4777
GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
4778
/* nmaclhw   - nmaclhw.   */
4779
GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
4780
/* nmaclhwo  - nmaclhwo.  */
4781
GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
4782
/* nmaclhws  - nmaclhws.  */
4783
GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
4784
/* nmaclhwso - nmaclhwso. */
4785
GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
4786

    
4787
/* mulchw  - mulchw.  */
4788
GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
4789
/* mulchwu - mulchwu. */
4790
GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
4791
/* mulhhw  - mulhhw.  */
4792
GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
4793
/* mulhhwu - mulhhwu. */
4794
GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
4795
/* mullhw  - mullhw.  */
4796
GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
4797
/* mullhwu - mullhwu. */
4798
GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
4799

    
4800
/* mfdcr */
4801
GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
4802
{
4803
#if defined(CONFIG_USER_ONLY)
4804
    GEN_EXCP_PRIVREG(ctx);
4805
#else
4806
    uint32_t dcrn = SPR(ctx->opcode);
4807

    
4808
    if (unlikely(!ctx->supervisor)) {
4809
        GEN_EXCP_PRIVREG(ctx);
4810
        return;
4811
    }
4812
    gen_op_set_T0(dcrn);
4813
    gen_op_load_dcr();
4814
    gen_op_store_T0_gpr(rD(ctx->opcode));
4815
#endif
4816
}
4817

    
4818
/* mtdcr */
4819
GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
4820
{
4821
#if defined(CONFIG_USER_ONLY)
4822
    GEN_EXCP_PRIVREG(ctx);
4823
#else
4824
    uint32_t dcrn = SPR(ctx->opcode);
4825

    
4826
    if (unlikely(!ctx->supervisor)) {
4827
        GEN_EXCP_PRIVREG(ctx);
4828
        return;
4829
    }
4830
    gen_op_set_T0(dcrn);
4831
    gen_op_load_gpr_T1(rS(ctx->opcode));
4832
    gen_op_store_dcr();
4833
#endif
4834
}
4835

    
4836
/* mfdcrx */
4837
/* XXX: not implemented on 440 ? */
4838
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
4839
{
4840
#if defined(CONFIG_USER_ONLY)
4841
    GEN_EXCP_PRIVREG(ctx);
4842
#else
4843
    if (unlikely(!ctx->supervisor)) {
4844
        GEN_EXCP_PRIVREG(ctx);
4845
        return;
4846
    }
4847
    gen_op_load_gpr_T0(rA(ctx->opcode));
4848
    gen_op_load_dcr();
4849
    gen_op_store_T0_gpr(rD(ctx->opcode));
4850
    /* Note: Rc update flag set leads to undefined state of Rc0 */
4851
#endif
4852
}
4853

    
4854
/* mtdcrx */
4855
/* XXX: not implemented on 440 ? */
4856
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
4857
{
4858
#if defined(CONFIG_USER_ONLY)
4859
    GEN_EXCP_PRIVREG(ctx);
4860
#else
4861
    if (unlikely(!ctx->supervisor)) {
4862
        GEN_EXCP_PRIVREG(ctx);
4863
        return;
4864
    }
4865
    gen_op_load_gpr_T0(rA(ctx->opcode));
4866
    gen_op_load_gpr_T1(rS(ctx->opcode));
4867
    gen_op_store_dcr();
4868
    /* Note: Rc update flag set leads to undefined state of Rc0 */
4869
#endif
4870
}
4871

    
4872
/* mfdcrux (PPC 460) : user-mode access to DCR */
4873
GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
4874
{
4875
    gen_op_load_gpr_T0(rA(ctx->opcode));
4876
    gen_op_load_dcr();
4877
    gen_op_store_T0_gpr(rD(ctx->opcode));
4878
    /* Note: Rc update flag set leads to undefined state of Rc0 */
4879
}
4880

    
4881
/* mtdcrux (PPC 460) : user-mode access to DCR */
4882
GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
4883
{
4884
    gen_op_load_gpr_T0(rA(ctx->opcode));
4885
    gen_op_load_gpr_T1(rS(ctx->opcode));
4886
    gen_op_store_dcr();
4887
    /* Note: Rc update flag set leads to undefined state of Rc0 */
4888
}
4889

    
4890
/* dccci */
4891
GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4892
{
4893
#if defined(CONFIG_USER_ONLY)
4894
    GEN_EXCP_PRIVOPC(ctx);
4895
#else
4896
    if (unlikely(!ctx->supervisor)) {
4897
        GEN_EXCP_PRIVOPC(ctx);
4898
        return;
4899
    }
4900
    /* interpreted as no-op */
4901