Statistics
| Branch: | Revision:

root / translate-all.c @ 623e265c

History | View | Annotate | Download (7.8 kB)

1 d19893da bellard
/*
2 d19893da bellard
 *  Host code generation
3 5fafdf24 ths
 *
4 d19893da bellard
 *  Copyright (c) 2003 Fabrice Bellard
5 d19893da bellard
 *
6 d19893da bellard
 * This library is free software; you can redistribute it and/or
7 d19893da bellard
 * modify it under the terms of the GNU Lesser General Public
8 d19893da bellard
 * License as published by the Free Software Foundation; either
9 d19893da bellard
 * version 2 of the License, or (at your option) any later version.
10 d19893da bellard
 *
11 d19893da bellard
 * This library is distributed in the hope that it will be useful,
12 d19893da bellard
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 d19893da bellard
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 d19893da bellard
 * Lesser General Public License for more details.
15 d19893da bellard
 *
16 d19893da bellard
 * You should have received a copy of the GNU Lesser General Public
17 d19893da bellard
 * License along with this library; if not, write to the Free Software
18 d19893da bellard
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19 d19893da bellard
 */
20 d19893da bellard
#include <stdarg.h>
21 d19893da bellard
#include <stdlib.h>
22 d19893da bellard
#include <stdio.h>
23 d19893da bellard
#include <string.h>
24 d19893da bellard
#include <inttypes.h>
25 d19893da bellard
26 d19893da bellard
#include "config.h"
27 2054396a bellard
28 af5ad107 bellard
#define NO_CPU_IO_DEFS
29 d3eead2e bellard
#include "cpu.h"
30 d3eead2e bellard
#include "exec-all.h"
31 d19893da bellard
#include "disas.h"
32 57fec1fe bellard
#include "tcg.h"
33 d19893da bellard
34 57fec1fe bellard
/* code generation context */
35 57fec1fe bellard
TCGContext tcg_ctx;
36 d19893da bellard
37 d19893da bellard
uint16_t gen_opc_buf[OPC_BUF_SIZE];
38 57fec1fe bellard
TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
39 c4687878 bellard
40 c4687878 bellard
target_ulong gen_opc_pc[OPC_BUF_SIZE];
41 d19893da bellard
uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
42 f76af4b3 bellard
#if defined(TARGET_I386)
43 f76af4b3 bellard
uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
44 e95c8d51 bellard
#elif defined(TARGET_SPARC)
45 c4687878 bellard
target_ulong gen_opc_npc[OPC_BUF_SIZE];
46 c3278b7b bellard
target_ulong gen_opc_jump_pc[2];
47 823029f9 ths
#elif defined(TARGET_MIPS) || defined(TARGET_SH4)
48 30d6cb84 bellard
uint32_t gen_opc_hflags[OPC_BUF_SIZE];
49 f76af4b3 bellard
#endif
50 d19893da bellard
51 58fe2f10 bellard
int code_copy_enabled = 1;
52 58fe2f10 bellard
53 57fec1fe bellard
#ifdef CONFIG_PROFILER
54 57fec1fe bellard
int64_t dyngen_tb_count1;
55 57fec1fe bellard
int64_t dyngen_tb_count;
56 57fec1fe bellard
int64_t dyngen_op_count;
57 57fec1fe bellard
int64_t dyngen_old_op_count;
58 57fec1fe bellard
int64_t dyngen_tcg_del_op_count;
59 57fec1fe bellard
int dyngen_op_count_max;
60 57fec1fe bellard
int64_t dyngen_code_in_len;
61 57fec1fe bellard
int64_t dyngen_code_out_len;
62 57fec1fe bellard
int64_t dyngen_interm_time;
63 57fec1fe bellard
int64_t dyngen_code_time;
64 57fec1fe bellard
int64_t dyngen_restore_count;
65 57fec1fe bellard
int64_t dyngen_restore_time;
66 d19893da bellard
#endif
67 d19893da bellard
68 57fec1fe bellard
/* XXX: suppress that */
69 d07bde88 blueswir1
unsigned long code_gen_max_block_size(void)
70 d07bde88 blueswir1
{
71 d07bde88 blueswir1
    static unsigned long max;
72 d07bde88 blueswir1
73 d07bde88 blueswir1
    if (max == 0) {
74 d07bde88 blueswir1
#define DEF(s, n, copy_size) max = copy_size > max? copy_size : max;
75 57fec1fe bellard
#include "tcg-opc.h"
76 d07bde88 blueswir1
#undef DEF
77 d07bde88 blueswir1
        max *= OPC_MAX_SIZE;
78 d07bde88 blueswir1
    }
79 d07bde88 blueswir1
80 d07bde88 blueswir1
    return max;
81 d07bde88 blueswir1
}
82 d07bde88 blueswir1
83 57fec1fe bellard
void cpu_gen_init(void)
84 57fec1fe bellard
{
85 57fec1fe bellard
    tcg_context_init(&tcg_ctx); 
86 57fec1fe bellard
    tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf),
87 57fec1fe bellard
                  128 * sizeof(long));
88 57fec1fe bellard
}
89 57fec1fe bellard
90 d19893da bellard
/* return non zero if the very first instruction is invalid so that
91 5fafdf24 ths
   the virtual CPU can trigger an exception.
92 d19893da bellard

93 d19893da bellard
   '*gen_code_size_ptr' contains the size of the generated code (host
94 d19893da bellard
   code).
95 d19893da bellard
*/
96 d07bde88 blueswir1
int cpu_gen_code(CPUState *env, TranslationBlock *tb, int *gen_code_size_ptr)
97 d19893da bellard
{
98 57fec1fe bellard
    TCGContext *s = &tcg_ctx;
99 d19893da bellard
    uint8_t *gen_code_buf;
100 d19893da bellard
    int gen_code_size;
101 57fec1fe bellard
#ifdef CONFIG_PROFILER
102 57fec1fe bellard
    int64_t ti;
103 57fec1fe bellard
#endif
104 57fec1fe bellard
105 57fec1fe bellard
#ifdef CONFIG_PROFILER
106 57fec1fe bellard
    dyngen_tb_count1++; /* includes aborted translations because of
107 57fec1fe bellard
                           exceptions */
108 57fec1fe bellard
    ti = profile_getclock();
109 57fec1fe bellard
#endif
110 57fec1fe bellard
    tcg_func_start(s);
111 d19893da bellard
112 ec6338ba bellard
    if (gen_intermediate_code(env, tb) < 0)
113 ec6338ba bellard
        return -1;
114 ec6338ba bellard
    
115 ec6338ba bellard
    /* generate machine code */
116 57fec1fe bellard
    gen_code_buf = tb->tc_ptr;
117 ec6338ba bellard
    tb->tb_next_offset[0] = 0xffff;
118 ec6338ba bellard
    tb->tb_next_offset[1] = 0xffff;
119 57fec1fe bellard
    s->tb_next_offset = tb->tb_next_offset;
120 4cbb86e1 bellard
#ifdef USE_DIRECT_JUMP
121 57fec1fe bellard
    s->tb_jmp_offset = tb->tb_jmp_offset;
122 57fec1fe bellard
    s->tb_next = NULL;
123 ec6338ba bellard
    /* the following two entries are optional (only used for string ops) */
124 57fec1fe bellard
    /* XXX: not used ? */
125 ec6338ba bellard
    tb->tb_jmp_offset[2] = 0xffff;
126 ec6338ba bellard
    tb->tb_jmp_offset[3] = 0xffff;
127 d19893da bellard
#else
128 57fec1fe bellard
    s->tb_jmp_offset = NULL;
129 57fec1fe bellard
    s->tb_next = tb->tb_next;
130 d19893da bellard
#endif
131 57fec1fe bellard
132 57fec1fe bellard
#ifdef CONFIG_PROFILER
133 57fec1fe bellard
    dyngen_tb_count++;
134 57fec1fe bellard
    dyngen_interm_time += profile_getclock() - ti;
135 57fec1fe bellard
    dyngen_code_time -= profile_getclock();
136 57fec1fe bellard
#endif
137 57fec1fe bellard
    gen_code_size = dyngen_code(s, gen_code_buf);
138 d19893da bellard
    *gen_code_size_ptr = gen_code_size;
139 57fec1fe bellard
#ifdef CONFIG_PROFILER
140 57fec1fe bellard
    dyngen_code_time += profile_getclock();
141 57fec1fe bellard
    dyngen_code_in_len += tb->size;
142 57fec1fe bellard
    dyngen_code_out_len += gen_code_size;
143 57fec1fe bellard
#endif
144 57fec1fe bellard
145 d19893da bellard
#ifdef DEBUG_DISAS
146 f193c797 bellard
    if (loglevel & CPU_LOG_TB_OUT_ASM) {
147 d19893da bellard
        fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
148 c4687878 bellard
        disas(logfile, tb->tc_ptr, *gen_code_size_ptr);
149 d19893da bellard
        fprintf(logfile, "\n");
150 d19893da bellard
        fflush(logfile);
151 d19893da bellard
    }
152 d19893da bellard
#endif
153 d19893da bellard
    return 0;
154 d19893da bellard
}
155 d19893da bellard
156 5fafdf24 ths
/* The cpu state corresponding to 'searched_pc' is restored.
157 d19893da bellard
 */
158 5fafdf24 ths
int cpu_restore_state(TranslationBlock *tb,
159 58fe2f10 bellard
                      CPUState *env, unsigned long searched_pc,
160 58fe2f10 bellard
                      void *puc)
161 d19893da bellard
{
162 57fec1fe bellard
    TCGContext *s = &tcg_ctx;
163 57fec1fe bellard
    int j;
164 d19893da bellard
    unsigned long tc_ptr;
165 57fec1fe bellard
#ifdef CONFIG_PROFILER
166 57fec1fe bellard
    int64_t ti;
167 57fec1fe bellard
#endif
168 57fec1fe bellard
169 57fec1fe bellard
#ifdef CONFIG_PROFILER
170 57fec1fe bellard
    ti = profile_getclock();
171 57fec1fe bellard
#endif
172 57fec1fe bellard
    tcg_func_start(s);
173 d19893da bellard
174 4c3a88a2 bellard
    if (gen_intermediate_code_pc(env, tb) < 0)
175 d19893da bellard
        return -1;
176 3b46e624 ths
177 d19893da bellard
    /* find opc index corresponding to search_pc */
178 d19893da bellard
    tc_ptr = (unsigned long)tb->tc_ptr;
179 d19893da bellard
    if (searched_pc < tc_ptr)
180 d19893da bellard
        return -1;
181 57fec1fe bellard
182 57fec1fe bellard
    s->tb_next_offset = tb->tb_next_offset;
183 57fec1fe bellard
#ifdef USE_DIRECT_JUMP
184 57fec1fe bellard
    s->tb_jmp_offset = tb->tb_jmp_offset;
185 57fec1fe bellard
    s->tb_next = NULL;
186 57fec1fe bellard
#else
187 57fec1fe bellard
    s->tb_jmp_offset = NULL;
188 57fec1fe bellard
    s->tb_next = tb->tb_next;
189 57fec1fe bellard
#endif
190 623e265c pbrook
    j = dyngen_code_search_pc(s, (uint8_t *)tc_ptr, searched_pc - tc_ptr);
191 57fec1fe bellard
    if (j < 0)
192 57fec1fe bellard
        return -1;
193 d19893da bellard
    /* now find start of instruction before */
194 d19893da bellard
    while (gen_opc_instr_start[j] == 0)
195 d19893da bellard
        j--;
196 f76af4b3 bellard
#if defined(TARGET_I386)
197 f76af4b3 bellard
    {
198 f76af4b3 bellard
        int cc_op;
199 3c1cf9fa bellard
#ifdef DEBUG_DISAS
200 f193c797 bellard
        if (loglevel & CPU_LOG_TB_OP) {
201 3c1cf9fa bellard
            int i;
202 6e0374f6 bellard
            fprintf(logfile, "RESTORE:\n");
203 3c1cf9fa bellard
            for(i=0;i<=j; i++) {
204 3c1cf9fa bellard
                if (gen_opc_instr_start[i]) {
205 c4687878 bellard
                    fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
206 3c1cf9fa bellard
                }
207 3c1cf9fa bellard
            }
208 5fafdf24 ths
            fprintf(logfile, "spc=0x%08lx j=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
209 5fafdf24 ths
                    searched_pc, j, gen_opc_pc[j] - tb->cs_base,
210 c4687878 bellard
                    (uint32_t)tb->cs_base);
211 3c1cf9fa bellard
        }
212 3c1cf9fa bellard
#endif
213 f76af4b3 bellard
        env->eip = gen_opc_pc[j] - tb->cs_base;
214 f76af4b3 bellard
        cc_op = gen_opc_cc_op[j];
215 f76af4b3 bellard
        if (cc_op != CC_OP_DYNAMIC)
216 f76af4b3 bellard
            env->cc_op = cc_op;
217 f76af4b3 bellard
    }
218 f76af4b3 bellard
#elif defined(TARGET_ARM)
219 f76af4b3 bellard
    env->regs[15] = gen_opc_pc[j];
220 d3eead2e bellard
#elif defined(TARGET_SPARC)
221 c3278b7b bellard
    {
222 c3278b7b bellard
        target_ulong npc;
223 c3278b7b bellard
        env->pc = gen_opc_pc[j];
224 c3278b7b bellard
        npc = gen_opc_npc[j];
225 c3278b7b bellard
        if (npc == 1) {
226 c3278b7b bellard
            /* dynamic NPC: already stored */
227 c3278b7b bellard
        } else if (npc == 2) {
228 745cacc7 bellard
            target_ulong t2 = (target_ulong)(unsigned long)puc;
229 c3278b7b bellard
            /* jump PC: use T2 and the jump targets of the translation */
230 5fafdf24 ths
            if (t2)
231 c3278b7b bellard
                env->npc = gen_opc_jump_pc[0];
232 c3278b7b bellard
            else
233 c3278b7b bellard
                env->npc = gen_opc_jump_pc[1];
234 c3278b7b bellard
        } else {
235 c3278b7b bellard
            env->npc = npc;
236 c3278b7b bellard
        }
237 c3278b7b bellard
    }
238 6dca2016 bellard
#elif defined(TARGET_PPC)
239 af5ad107 bellard
    {
240 57fec1fe bellard
        int type, c;
241 af5ad107 bellard
        /* for PPC, we need to look at the micro operation to get the
242 af5ad107 bellard
           access type */
243 af5ad107 bellard
        env->nip = gen_opc_pc[j];
244 57fec1fe bellard
        c = gen_opc_buf[j];
245 af5ad107 bellard
        switch(c) {
246 af5ad107 bellard
#if defined(CONFIG_USER_ONLY)
247 af5ad107 bellard
#define CASE3(op)\
248 af5ad107 bellard
        case INDEX_op_ ## op ## _raw
249 af5ad107 bellard
#else
250 af5ad107 bellard
#define CASE3(op)\
251 af5ad107 bellard
        case INDEX_op_ ## op ## _user:\
252 7863667f j_mayer
        case INDEX_op_ ## op ## _kernel:\
253 7863667f j_mayer
        case INDEX_op_ ## op ## _hypv
254 af5ad107 bellard
#endif
255 3b46e624 ths
256 af5ad107 bellard
        CASE3(stfd):
257 af5ad107 bellard
        CASE3(stfs):
258 af5ad107 bellard
        CASE3(lfd):
259 af5ad107 bellard
        CASE3(lfs):
260 af5ad107 bellard
            type = ACCESS_FLOAT;
261 af5ad107 bellard
            break;
262 a541f297 bellard
        CASE3(lwarx):
263 a541f297 bellard
            type = ACCESS_RES;
264 a541f297 bellard
            break;
265 af5ad107 bellard
        CASE3(stwcx):
266 af5ad107 bellard
            type = ACCESS_RES;
267 af5ad107 bellard
            break;
268 af5ad107 bellard
        CASE3(eciwx):
269 af5ad107 bellard
        CASE3(ecowx):
270 af5ad107 bellard
            type = ACCESS_EXT;
271 af5ad107 bellard
            break;
272 af5ad107 bellard
        default:
273 af5ad107 bellard
            type = ACCESS_INT;
274 af5ad107 bellard
            break;
275 af5ad107 bellard
        }
276 af5ad107 bellard
        env->access_type = type;
277 af5ad107 bellard
    }
278 e6e5906b pbrook
#elif defined(TARGET_M68K)
279 e6e5906b pbrook
    env->pc = gen_opc_pc[j];
280 6af0bf9c bellard
#elif defined(TARGET_MIPS)
281 ead9360e ths
    env->PC[env->current_tc] = gen_opc_pc[j];
282 30d6cb84 bellard
    env->hflags &= ~MIPS_HFLAG_BMASK;
283 30d6cb84 bellard
    env->hflags |= gen_opc_hflags[j];
284 eddf68a6 j_mayer
#elif defined(TARGET_ALPHA)
285 eddf68a6 j_mayer
    env->pc = gen_opc_pc[j];
286 823029f9 ths
#elif defined(TARGET_SH4)
287 823029f9 ths
    env->pc = gen_opc_pc[j];
288 823029f9 ths
    env->flags = gen_opc_hflags[j];
289 f76af4b3 bellard
#endif
290 57fec1fe bellard
291 57fec1fe bellard
#ifdef CONFIG_PROFILER
292 57fec1fe bellard
    dyngen_restore_time += profile_getclock() - ti;
293 57fec1fe bellard
    dyngen_restore_count++;
294 57fec1fe bellard
#endif
295 d19893da bellard
    return 0;
296 d19893da bellard
}