root / target-mips / op_helper.c @ 6276c767
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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 2d0e944d | ths | #include <stdlib.h> |
21 | 6af0bf9c | bellard | #include "exec.h" |
22 | 6af0bf9c | bellard | |
23 | 05f778c8 | ths | #include "host-utils.h" |
24 | 05f778c8 | ths | |
25 | 4ad40f36 | bellard | #define GETPC() (__builtin_return_address(0)) |
26 | 4ad40f36 | bellard | |
27 | 6af0bf9c | bellard | /*****************************************************************************/
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28 | 6af0bf9c | bellard | /* Exceptions processing helpers */
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29 | 6af0bf9c | bellard | |
30 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
31 | 6af0bf9c | bellard | { |
32 | 6af0bf9c | bellard | #if 1 |
33 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
34 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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35 | 6af0bf9c | bellard | #endif
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36 | 6af0bf9c | bellard | env->exception_index = exception; |
37 | 6af0bf9c | bellard | env->error_code = error_code; |
38 | 6af0bf9c | bellard | T0 = 0;
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39 | 6af0bf9c | bellard | cpu_loop_exit(); |
40 | 6af0bf9c | bellard | } |
41 | 6af0bf9c | bellard | |
42 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
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43 | 6af0bf9c | bellard | { |
44 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
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45 | 6af0bf9c | bellard | } |
46 | 6af0bf9c | bellard | |
47 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
48 | 4ad40f36 | bellard | { |
49 | 4ad40f36 | bellard | TranslationBlock *tb; |
50 | 4ad40f36 | bellard | unsigned long pc = (unsigned long) pc_ptr; |
51 | 4ad40f36 | bellard | |
52 | 4ad40f36 | bellard | tb = tb_find_pc (pc); |
53 | 4ad40f36 | bellard | cpu_restore_state (tb, env, pc, NULL);
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54 | 4ad40f36 | bellard | } |
55 | 4ad40f36 | bellard | |
56 | e397ee33 | ths | void do_raise_exception_direct_err (uint32_t exception, int error_code) |
57 | 4ad40f36 | bellard | { |
58 | 4ad40f36 | bellard | do_restore_state (GETPC ()); |
59 | e397ee33 | ths | do_raise_exception_err (exception, error_code); |
60 | e397ee33 | ths | } |
61 | e397ee33 | ths | |
62 | e397ee33 | ths | void do_raise_exception_direct (uint32_t exception)
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63 | e397ee33 | ths | { |
64 | e397ee33 | ths | do_raise_exception_direct_err (exception, 0);
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65 | 4ad40f36 | bellard | } |
66 | 4ad40f36 | bellard | |
67 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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68 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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69 | c570fd16 | ths | /* Those might call libgcc functions. */
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70 | c570fd16 | ths | void do_dsll (void) |
71 | c570fd16 | ths | { |
72 | c570fd16 | ths | T0 = T0 << T1; |
73 | c570fd16 | ths | } |
74 | c570fd16 | ths | |
75 | c570fd16 | ths | void do_dsll32 (void) |
76 | c570fd16 | ths | { |
77 | c570fd16 | ths | T0 = T0 << (T1 + 32);
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78 | c570fd16 | ths | } |
79 | c570fd16 | ths | |
80 | c570fd16 | ths | void do_dsra (void) |
81 | c570fd16 | ths | { |
82 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
83 | c570fd16 | ths | } |
84 | c570fd16 | ths | |
85 | c570fd16 | ths | void do_dsra32 (void) |
86 | c570fd16 | ths | { |
87 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
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88 | c570fd16 | ths | } |
89 | c570fd16 | ths | |
90 | c570fd16 | ths | void do_dsrl (void) |
91 | c570fd16 | ths | { |
92 | c570fd16 | ths | T0 = T0 >> T1; |
93 | c570fd16 | ths | } |
94 | c570fd16 | ths | |
95 | c570fd16 | ths | void do_dsrl32 (void) |
96 | c570fd16 | ths | { |
97 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
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98 | c570fd16 | ths | } |
99 | c570fd16 | ths | |
100 | c570fd16 | ths | void do_drotr (void) |
101 | c570fd16 | ths | { |
102 | c570fd16 | ths | target_ulong tmp; |
103 | c570fd16 | ths | |
104 | c570fd16 | ths | if (T1) {
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105 | c570fd16 | ths | tmp = T0 << (0x40 - T1);
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106 | c570fd16 | ths | T0 = (T0 >> T1) | tmp; |
107 | 5a63bcb2 | ths | } |
108 | c570fd16 | ths | } |
109 | c570fd16 | ths | |
110 | c570fd16 | ths | void do_drotr32 (void) |
111 | c570fd16 | ths | { |
112 | c570fd16 | ths | target_ulong tmp; |
113 | c570fd16 | ths | |
114 | c570fd16 | ths | if (T1) {
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115 | c570fd16 | ths | tmp = T0 << (0x40 - (32 + T1)); |
116 | c570fd16 | ths | T0 = (T0 >> (32 + T1)) | tmp;
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117 | 5a63bcb2 | ths | } |
118 | c570fd16 | ths | } |
119 | c570fd16 | ths | |
120 | c570fd16 | ths | void do_dsllv (void) |
121 | c570fd16 | ths | { |
122 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
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123 | c570fd16 | ths | } |
124 | c570fd16 | ths | |
125 | c570fd16 | ths | void do_dsrav (void) |
126 | c570fd16 | ths | { |
127 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
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128 | c570fd16 | ths | } |
129 | c570fd16 | ths | |
130 | c570fd16 | ths | void do_dsrlv (void) |
131 | c570fd16 | ths | { |
132 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
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133 | c570fd16 | ths | } |
134 | c570fd16 | ths | |
135 | c570fd16 | ths | void do_drotrv (void) |
136 | c570fd16 | ths | { |
137 | c570fd16 | ths | target_ulong tmp; |
138 | c570fd16 | ths | |
139 | c570fd16 | ths | T0 &= 0x3F;
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140 | c570fd16 | ths | if (T0) {
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141 | c570fd16 | ths | tmp = T1 << (0x40 - T0);
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142 | c570fd16 | ths | T0 = (T1 >> T0) | tmp; |
143 | c570fd16 | ths | } else
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144 | c570fd16 | ths | T0 = T1; |
145 | c570fd16 | ths | } |
146 | 05f778c8 | ths | |
147 | 05f778c8 | ths | void do_dclo (void) |
148 | 05f778c8 | ths | { |
149 | 05f778c8 | ths | T0 = clo64(T0); |
150 | 05f778c8 | ths | } |
151 | 05f778c8 | ths | |
152 | 05f778c8 | ths | void do_dclz (void) |
153 | 05f778c8 | ths | { |
154 | 05f778c8 | ths | T0 = clz64(T0); |
155 | 05f778c8 | ths | } |
156 | 05f778c8 | ths | |
157 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
158 | 540635ba | ths | #endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ |
159 | c570fd16 | ths | |
160 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
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161 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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162 | aa343735 | ths | static always_inline uint64_t get_HILO (void) |
163 | 6af0bf9c | bellard | { |
164 | ead9360e | ths | return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc]; |
165 | 6af0bf9c | bellard | } |
166 | 6af0bf9c | bellard | |
167 | aa343735 | ths | static always_inline void set_HILO (uint64_t HILO) |
168 | 6af0bf9c | bellard | { |
169 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)HILO;
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170 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
171 | 6af0bf9c | bellard | } |
172 | 6af0bf9c | bellard | |
173 | 6af0bf9c | bellard | void do_mult (void) |
174 | 6af0bf9c | bellard | { |
175 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
176 | 6af0bf9c | bellard | } |
177 | 6af0bf9c | bellard | |
178 | 6af0bf9c | bellard | void do_multu (void) |
179 | 6af0bf9c | bellard | { |
180 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
181 | 6af0bf9c | bellard | } |
182 | 6af0bf9c | bellard | |
183 | 6af0bf9c | bellard | void do_madd (void) |
184 | 6af0bf9c | bellard | { |
185 | 6af0bf9c | bellard | int64_t tmp; |
186 | 6af0bf9c | bellard | |
187 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
188 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
189 | 6af0bf9c | bellard | } |
190 | 6af0bf9c | bellard | |
191 | 6af0bf9c | bellard | void do_maddu (void) |
192 | 6af0bf9c | bellard | { |
193 | 6af0bf9c | bellard | uint64_t tmp; |
194 | 6af0bf9c | bellard | |
195 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
196 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
197 | 6af0bf9c | bellard | } |
198 | 6af0bf9c | bellard | |
199 | 6af0bf9c | bellard | void do_msub (void) |
200 | 6af0bf9c | bellard | { |
201 | 6af0bf9c | bellard | int64_t tmp; |
202 | 6af0bf9c | bellard | |
203 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
204 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
205 | 6af0bf9c | bellard | } |
206 | 6af0bf9c | bellard | |
207 | 6af0bf9c | bellard | void do_msubu (void) |
208 | 6af0bf9c | bellard | { |
209 | 6af0bf9c | bellard | uint64_t tmp; |
210 | 6af0bf9c | bellard | |
211 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
212 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
213 | 6af0bf9c | bellard | } |
214 | 6af0bf9c | bellard | #endif
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215 | 6af0bf9c | bellard | |
216 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
217 | 80c27194 | ths | void do_div (void) |
218 | 80c27194 | ths | { |
219 | 80c27194 | ths | /* 64bit datatypes because we may see overflow/underflow. */
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220 | 80c27194 | ths | if (T1 != 0) { |
221 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
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222 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
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223 | 80c27194 | ths | } |
224 | 80c27194 | ths | } |
225 | 80c27194 | ths | #endif
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226 | 80c27194 | ths | |
227 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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228 | c570fd16 | ths | void do_ddiv (void) |
229 | c570fd16 | ths | { |
230 | c570fd16 | ths | if (T1 != 0) { |
231 | 2d0e944d | ths | lldiv_t res = lldiv((int64_t)T0, (int64_t)T1); |
232 | ead9360e | ths | env->LO[0][env->current_tc] = res.quot;
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233 | ead9360e | ths | env->HI[0][env->current_tc] = res.rem;
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234 | c570fd16 | ths | } |
235 | c570fd16 | ths | } |
236 | c570fd16 | ths | |
237 | 12a4b2aa | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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238 | c570fd16 | ths | void do_ddivu (void) |
239 | c570fd16 | ths | { |
240 | c570fd16 | ths | if (T1 != 0) { |
241 | ead9360e | ths | env->LO[0][env->current_tc] = T0 / T1;
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242 | ead9360e | ths | env->HI[0][env->current_tc] = T0 % T1;
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243 | c570fd16 | ths | } |
244 | c570fd16 | ths | } |
245 | c570fd16 | ths | #endif
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246 | 540635ba | ths | #endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ |
247 | c570fd16 | ths | |
248 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
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249 | 873eb012 | ths | void do_mfc0_random (void) |
250 | 048f6b4d | bellard | { |
251 | 873eb012 | ths | cpu_abort(env, "mfc0 random\n");
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252 | 048f6b4d | bellard | } |
253 | 873eb012 | ths | |
254 | 873eb012 | ths | void do_mfc0_count (void) |
255 | 873eb012 | ths | { |
256 | 873eb012 | ths | cpu_abort(env, "mfc0 count\n");
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257 | 873eb012 | ths | } |
258 | 873eb012 | ths | |
259 | 8c0fdd85 | ths | void cpu_mips_store_count(CPUState *env, uint32_t value)
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260 | 048f6b4d | bellard | { |
261 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 count\n");
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262 | 8c0fdd85 | ths | } |
263 | 8c0fdd85 | ths | |
264 | 8c0fdd85 | ths | void cpu_mips_store_compare(CPUState *env, uint32_t value)
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265 | 8c0fdd85 | ths | { |
266 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 compare\n");
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267 | 8c0fdd85 | ths | } |
268 | 8c0fdd85 | ths | |
269 | 42532189 | ths | void cpu_mips_start_count(CPUState *env)
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270 | 42532189 | ths | { |
271 | 42532189 | ths | cpu_abort(env, "start count\n");
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272 | 42532189 | ths | } |
273 | 42532189 | ths | |
274 | 42532189 | ths | void cpu_mips_stop_count(CPUState *env)
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275 | 42532189 | ths | { |
276 | 42532189 | ths | cpu_abort(env, "stop count\n");
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277 | 42532189 | ths | } |
278 | 42532189 | ths | |
279 | 4de9b249 | ths | void cpu_mips_update_irq(CPUState *env)
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280 | 4de9b249 | ths | { |
281 | 4de9b249 | ths | cpu_abort(env, "mtc0 status / mtc0 cause\n");
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282 | 4de9b249 | ths | } |
283 | 4de9b249 | ths | |
284 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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285 | 8c0fdd85 | ths | { |
286 | 7a387fff | ths | cpu_abort(env, "mtc0 status debug\n");
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287 | 8c0fdd85 | ths | } |
288 | 8c0fdd85 | ths | |
289 | 7a387fff | ths | void do_mtc0_status_irqraise_debug (void) |
290 | 8c0fdd85 | ths | { |
291 | 7a387fff | ths | cpu_abort(env, "mtc0 status irqraise debug\n");
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292 | 048f6b4d | bellard | } |
293 | 048f6b4d | bellard | |
294 | 8c0fdd85 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
295 | 8c0fdd85 | ths | { |
296 | 8c0fdd85 | ths | cpu_abort(env, "mips_tlb_flush\n");
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297 | 8c0fdd85 | ths | } |
298 | 8c0fdd85 | ths | |
299 | 048f6b4d | bellard | #else
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300 | 048f6b4d | bellard | |
301 | 6af0bf9c | bellard | /* CP0 helpers */
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302 | 873eb012 | ths | void do_mfc0_random (void) |
303 | 6af0bf9c | bellard | { |
304 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_random(env); |
305 | 873eb012 | ths | } |
306 | 6af0bf9c | bellard | |
307 | 873eb012 | ths | void do_mfc0_count (void) |
308 | 873eb012 | ths | { |
309 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_count(env); |
310 | 6af0bf9c | bellard | } |
311 | 6af0bf9c | bellard | |
312 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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313 | 6af0bf9c | bellard | { |
314 | f41c52f1 | ths | fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
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315 | f41c52f1 | ths | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
316 | f41c52f1 | ths | val, val & env->CP0_Cause & CP0Ca_IP_mask, |
317 | f41c52f1 | ths | env->CP0_Cause); |
318 | 623a930e | ths | switch (env->hflags & MIPS_HFLAG_KSU) {
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319 | 623a930e | ths | case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break; |
320 | 623a930e | ths | case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break; |
321 | 623a930e | ths | case MIPS_HFLAG_KM: fputs("\n", logfile); break; |
322 | 623a930e | ths | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
323 | 623a930e | ths | } |
324 | 8c0fdd85 | ths | } |
325 | 8c0fdd85 | ths | |
326 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void) |
327 | 8c0fdd85 | ths | { |
328 | 8c0fdd85 | ths | fprintf(logfile, "Raise pending IRQs\n");
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329 | 6af0bf9c | bellard | } |
330 | 6af0bf9c | bellard | |
331 | 6ea83fed | bellard | void fpu_handle_exception(void) |
332 | 6ea83fed | bellard | { |
333 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
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334 | ead9360e | ths | int flags = get_float_exception_flags(&env->fpu->fp_status);
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335 | 6ea83fed | bellard | unsigned int cpuflags = 0, enable, cause = 0; |
336 | 6ea83fed | bellard | |
337 | ead9360e | ths | enable = GET_FP_ENABLE(env->fpu->fcr31); |
338 | 6ea83fed | bellard | |
339 | 3b46e624 | ths | /* determine current flags */
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340 | 6ea83fed | bellard | if (flags & float_flag_invalid) {
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341 | 6ea83fed | bellard | cpuflags |= FP_INVALID; |
342 | 6ea83fed | bellard | cause |= FP_INVALID & enable; |
343 | 6ea83fed | bellard | } |
344 | 6ea83fed | bellard | if (flags & float_flag_divbyzero) {
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345 | 3b46e624 | ths | cpuflags |= FP_DIV0; |
346 | 6ea83fed | bellard | cause |= FP_DIV0 & enable; |
347 | 6ea83fed | bellard | } |
348 | 6ea83fed | bellard | if (flags & float_flag_overflow) {
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349 | 3b46e624 | ths | cpuflags |= FP_OVERFLOW; |
350 | 6ea83fed | bellard | cause |= FP_OVERFLOW & enable; |
351 | 6ea83fed | bellard | } |
352 | 6ea83fed | bellard | if (flags & float_flag_underflow) {
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353 | 3b46e624 | ths | cpuflags |= FP_UNDERFLOW; |
354 | 6ea83fed | bellard | cause |= FP_UNDERFLOW & enable; |
355 | 6ea83fed | bellard | } |
356 | 6ea83fed | bellard | if (flags & float_flag_inexact) {
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357 | 5fafdf24 | ths | cpuflags |= FP_INEXACT; |
358 | 6ea83fed | bellard | cause |= FP_INEXACT & enable; |
359 | 6ea83fed | bellard | } |
360 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, cpuflags); |
361 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, cause); |
362 | 6ea83fed | bellard | #else
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363 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, 0);
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364 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, 0);
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365 | 6ea83fed | bellard | #endif
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366 | 6ea83fed | bellard | } |
367 | 6ea83fed | bellard | |
368 | 6af0bf9c | bellard | /* TLB management */
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369 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
370 | 814b9a47 | ths | { |
371 | 814b9a47 | ths | /* Flush qemu's TLB and discard all shadowed entries. */
|
372 | 814b9a47 | ths | tlb_flush (env, flush_global); |
373 | ead9360e | ths | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
374 | 814b9a47 | ths | } |
375 | 814b9a47 | ths | |
376 | 29929e34 | ths | static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
377 | 814b9a47 | ths | { |
378 | 814b9a47 | ths | /* Discard entries from env->tlb[first] onwards. */
|
379 | ead9360e | ths | while (env->tlb->tlb_in_use > first) {
|
380 | ead9360e | ths | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
|
381 | 814b9a47 | ths | } |
382 | 814b9a47 | ths | } |
383 | 814b9a47 | ths | |
384 | 29929e34 | ths | static void r4k_fill_tlb (int idx) |
385 | 6af0bf9c | bellard | { |
386 | 29929e34 | ths | r4k_tlb_t *tlb; |
387 | 6af0bf9c | bellard | |
388 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
389 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
390 | f2e9ebef | ths | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
391 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
392 | e034e2c3 | ths | tlb->VPN &= env->SEGMask; |
393 | 100ce988 | ths | #endif
|
394 | 98c1b82b | pbrook | tlb->ASID = env->CP0_EntryHi & 0xFF;
|
395 | 3b1c8be4 | ths | tlb->PageMask = env->CP0_PageMask; |
396 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
397 | 98c1b82b | pbrook | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
398 | 98c1b82b | pbrook | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
399 | 98c1b82b | pbrook | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
400 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
401 | 98c1b82b | pbrook | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
402 | 98c1b82b | pbrook | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
403 | 98c1b82b | pbrook | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
404 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
405 | 6af0bf9c | bellard | } |
406 | 6af0bf9c | bellard | |
407 | 29929e34 | ths | void r4k_do_tlbwi (void) |
408 | 6af0bf9c | bellard | { |
409 | 814b9a47 | ths | /* Discard cached TLB entries. We could avoid doing this if the
|
410 | 814b9a47 | ths | tlbwi is just upgrading access permissions on the current entry;
|
411 | 814b9a47 | ths | that might be a further win. */
|
412 | ead9360e | ths | r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
413 | 814b9a47 | ths | |
414 | ead9360e | ths | r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
|
415 | ead9360e | ths | r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb); |
416 | 6af0bf9c | bellard | } |
417 | 6af0bf9c | bellard | |
418 | 29929e34 | ths | void r4k_do_tlbwr (void) |
419 | 6af0bf9c | bellard | { |
420 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
|
421 | 6af0bf9c | bellard | |
422 | 29929e34 | ths | r4k_invalidate_tlb(env, r, 1);
|
423 | 29929e34 | ths | r4k_fill_tlb(r); |
424 | 6af0bf9c | bellard | } |
425 | 6af0bf9c | bellard | |
426 | 29929e34 | ths | void r4k_do_tlbp (void) |
427 | 6af0bf9c | bellard | { |
428 | 29929e34 | ths | r4k_tlb_t *tlb; |
429 | f2e9ebef | ths | target_ulong mask; |
430 | 6af0bf9c | bellard | target_ulong tag; |
431 | f2e9ebef | ths | target_ulong VPN; |
432 | 6af0bf9c | bellard | uint8_t ASID; |
433 | 6af0bf9c | bellard | int i;
|
434 | 6af0bf9c | bellard | |
435 | 3d9fb9fe | bellard | ASID = env->CP0_EntryHi & 0xFF;
|
436 | ead9360e | ths | for (i = 0; i < env->tlb->nb_tlb; i++) { |
437 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
438 | f2e9ebef | ths | /* 1k pages are not supported. */
|
439 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
440 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
441 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
442 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
|
443 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
444 | 6af0bf9c | bellard | /* TLB match */
|
445 | 9c2149c8 | ths | env->CP0_Index = i; |
446 | 6af0bf9c | bellard | break;
|
447 | 6af0bf9c | bellard | } |
448 | 6af0bf9c | bellard | } |
449 | ead9360e | ths | if (i == env->tlb->nb_tlb) {
|
450 | 814b9a47 | ths | /* No match. Discard any shadow entries, if any of them match. */
|
451 | ead9360e | ths | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
452 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
453 | f2e9ebef | ths | /* 1k pages are not supported. */
|
454 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
455 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
456 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
457 | 814b9a47 | ths | /* Check ASID, virtual page number & size */
|
458 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
459 | 29929e34 | ths | r4k_mips_tlb_flush_extra (env, i); |
460 | 814b9a47 | ths | break;
|
461 | 814b9a47 | ths | } |
462 | 814b9a47 | ths | } |
463 | 814b9a47 | ths | |
464 | 9c2149c8 | ths | env->CP0_Index |= 0x80000000;
|
465 | 6af0bf9c | bellard | } |
466 | 6af0bf9c | bellard | } |
467 | 6af0bf9c | bellard | |
468 | 29929e34 | ths | void r4k_do_tlbr (void) |
469 | 6af0bf9c | bellard | { |
470 | 29929e34 | ths | r4k_tlb_t *tlb; |
471 | 09c56b84 | pbrook | uint8_t ASID; |
472 | 6af0bf9c | bellard | |
473 | 09c56b84 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
|
474 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb]; |
475 | 4ad40f36 | bellard | |
476 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
|
477 | 814b9a47 | ths | if (ASID != tlb->ASID)
|
478 | 814b9a47 | ths | cpu_mips_tlb_flush (env, 1);
|
479 | 814b9a47 | ths | |
480 | ead9360e | ths | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
481 | 4ad40f36 | bellard | |
482 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
483 | 3b1c8be4 | ths | env->CP0_PageMask = tlb->PageMask; |
484 | 7495fd0f | ths | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
485 | 7495fd0f | ths | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
486 | 7495fd0f | ths | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
487 | 7495fd0f | ths | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
488 | 6af0bf9c | bellard | } |
489 | 6af0bf9c | bellard | |
490 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
491 | 048f6b4d | bellard | |
492 | c570fd16 | ths | void dump_ldst (const unsigned char *func) |
493 | 6af0bf9c | bellard | { |
494 | 6af0bf9c | bellard | if (loglevel)
|
495 | 3594c774 | ths | fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1); |
496 | 6af0bf9c | bellard | } |
497 | 6af0bf9c | bellard | |
498 | 6af0bf9c | bellard | void dump_sc (void) |
499 | 6af0bf9c | bellard | { |
500 | 6af0bf9c | bellard | if (loglevel) {
|
501 | 3594c774 | ths | fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__, |
502 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
503 | 6af0bf9c | bellard | } |
504 | 6af0bf9c | bellard | } |
505 | 6af0bf9c | bellard | |
506 | f41c52f1 | ths | void debug_pre_eret (void) |
507 | 6af0bf9c | bellard | { |
508 | f41c52f1 | ths | fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
509 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
510 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
511 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
512 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
513 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
514 | f41c52f1 | ths | fputs("\n", logfile);
|
515 | f41c52f1 | ths | } |
516 | f41c52f1 | ths | |
517 | f41c52f1 | ths | void debug_post_eret (void) |
518 | f41c52f1 | ths | { |
519 | 744e0915 | ths | fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
520 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
521 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
522 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
523 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
524 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
525 | 623a930e | ths | switch (env->hflags & MIPS_HFLAG_KSU) {
|
526 | 623a930e | ths | case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break; |
527 | 623a930e | ths | case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break; |
528 | 623a930e | ths | case MIPS_HFLAG_KM: fputs("\n", logfile); break; |
529 | 623a930e | ths | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
530 | 623a930e | ths | } |
531 | 6af0bf9c | bellard | } |
532 | 6af0bf9c | bellard | |
533 | 6af0bf9c | bellard | void do_pmon (int function) |
534 | 6af0bf9c | bellard | { |
535 | 6af0bf9c | bellard | function /= 2;
|
536 | 6af0bf9c | bellard | switch (function) {
|
537 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
538 | ead9360e | ths | if (env->gpr[4][env->current_tc] == 0) |
539 | ead9360e | ths | env->gpr[2][env->current_tc] = -1; |
540 | 6af0bf9c | bellard | /* Fall through */
|
541 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
542 | ead9360e | ths | env->gpr[2][env->current_tc] = -1; |
543 | 6af0bf9c | bellard | break;
|
544 | 6af0bf9c | bellard | case 3: |
545 | 6af0bf9c | bellard | case 12: |
546 | ead9360e | ths | printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF)); |
547 | 6af0bf9c | bellard | break;
|
548 | 6af0bf9c | bellard | case 17: |
549 | 6af0bf9c | bellard | break;
|
550 | 6af0bf9c | bellard | case 158: |
551 | 6af0bf9c | bellard | { |
552 | ead9360e | ths | unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc]; |
553 | 6af0bf9c | bellard | printf("%s", fmt);
|
554 | 6af0bf9c | bellard | } |
555 | 6af0bf9c | bellard | break;
|
556 | 6af0bf9c | bellard | } |
557 | 6af0bf9c | bellard | } |
558 | e37e863f | bellard | |
559 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
560 | e37e863f | bellard | |
561 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
562 | 4ad40f36 | bellard | |
563 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
564 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
565 | e37e863f | bellard | |
566 | e37e863f | bellard | #define SHIFT 0 |
567 | e37e863f | bellard | #include "softmmu_template.h" |
568 | e37e863f | bellard | |
569 | e37e863f | bellard | #define SHIFT 1 |
570 | e37e863f | bellard | #include "softmmu_template.h" |
571 | e37e863f | bellard | |
572 | e37e863f | bellard | #define SHIFT 2 |
573 | e37e863f | bellard | #include "softmmu_template.h" |
574 | e37e863f | bellard | |
575 | e37e863f | bellard | #define SHIFT 3 |
576 | e37e863f | bellard | #include "softmmu_template.h" |
577 | e37e863f | bellard | |
578 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
579 | 4ad40f36 | bellard | { |
580 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
581 | 4ad40f36 | bellard | do_restore_state (retaddr); |
582 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
583 | 4ad40f36 | bellard | } |
584 | 4ad40f36 | bellard | |
585 | 6ebbf390 | j_mayer | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
586 | e37e863f | bellard | { |
587 | e37e863f | bellard | TranslationBlock *tb; |
588 | e37e863f | bellard | CPUState *saved_env; |
589 | e37e863f | bellard | unsigned long pc; |
590 | e37e863f | bellard | int ret;
|
591 | e37e863f | bellard | |
592 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
593 | e37e863f | bellard | generated code */
|
594 | e37e863f | bellard | saved_env = env; |
595 | e37e863f | bellard | env = cpu_single_env; |
596 | 6ebbf390 | j_mayer | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
597 | e37e863f | bellard | if (ret) {
|
598 | e37e863f | bellard | if (retaddr) {
|
599 | e37e863f | bellard | /* now we have a real cpu fault */
|
600 | e37e863f | bellard | pc = (unsigned long)retaddr; |
601 | e37e863f | bellard | tb = tb_find_pc(pc); |
602 | e37e863f | bellard | if (tb) {
|
603 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
604 | e37e863f | bellard | a virtual CPU fault */
|
605 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
606 | e37e863f | bellard | } |
607 | e37e863f | bellard | } |
608 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
609 | e37e863f | bellard | } |
610 | e37e863f | bellard | env = saved_env; |
611 | e37e863f | bellard | } |
612 | e37e863f | bellard | |
613 | 647de6ca | ths | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
614 | 647de6ca | ths | int unused)
|
615 | 647de6ca | ths | { |
616 | 647de6ca | ths | if (is_exec)
|
617 | 647de6ca | ths | do_raise_exception(EXCP_IBE); |
618 | 647de6ca | ths | else
|
619 | 647de6ca | ths | do_raise_exception(EXCP_DBE); |
620 | 647de6ca | ths | } |
621 | e37e863f | bellard | #endif
|
622 | fd4a04eb | ths | |
623 | fd4a04eb | ths | /* Complex FPU operations which may need stack space. */
|
624 | fd4a04eb | ths | |
625 | 8dfdb87c | ths | #define FLOAT_SIGN32 (1 << 31) |
626 | 8dfdb87c | ths | #define FLOAT_SIGN64 (1ULL << 63) |
627 | 8dfdb87c | ths | #define FLOAT_ONE32 (0x3f8 << 20) |
628 | 8dfdb87c | ths | #define FLOAT_ONE64 (0x3ffULL << 52) |
629 | 8dfdb87c | ths | #define FLOAT_TWO32 (1 << 30) |
630 | 8dfdb87c | ths | #define FLOAT_TWO64 (1ULL << 62) |
631 | 54454097 | ths | #define FLOAT_QNAN32 0x7fbfffff |
632 | 54454097 | ths | #define FLOAT_QNAN64 0x7ff7ffffffffffffULL |
633 | 54454097 | ths | #define FLOAT_SNAN32 0x7fffffff |
634 | 54454097 | ths | #define FLOAT_SNAN64 0x7fffffffffffffffULL |
635 | 8dfdb87c | ths | |
636 | fd4a04eb | ths | /* convert MIPS rounding mode in FCR31 to IEEE library */
|
637 | fd4a04eb | ths | unsigned int ieee_rm[] = { |
638 | fd4a04eb | ths | float_round_nearest_even, |
639 | fd4a04eb | ths | float_round_to_zero, |
640 | fd4a04eb | ths | float_round_up, |
641 | fd4a04eb | ths | float_round_down |
642 | fd4a04eb | ths | }; |
643 | fd4a04eb | ths | |
644 | fd4a04eb | ths | #define RESTORE_ROUNDING_MODE \
|
645 | ead9360e | ths | set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
|
646 | fd4a04eb | ths | |
647 | ead9360e | ths | void do_cfc1 (int reg) |
648 | fd4a04eb | ths | { |
649 | ead9360e | ths | switch (reg) {
|
650 | ead9360e | ths | case 0: |
651 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr0; |
652 | ead9360e | ths | break;
|
653 | ead9360e | ths | case 25: |
654 | ead9360e | ths | T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); |
655 | ead9360e | ths | break;
|
656 | ead9360e | ths | case 26: |
657 | ead9360e | ths | T0 = env->fpu->fcr31 & 0x0003f07c;
|
658 | ead9360e | ths | break;
|
659 | ead9360e | ths | case 28: |
660 | ead9360e | ths | T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); |
661 | ead9360e | ths | break;
|
662 | ead9360e | ths | default:
|
663 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr31; |
664 | ead9360e | ths | break;
|
665 | ead9360e | ths | } |
666 | ead9360e | ths | } |
667 | ead9360e | ths | |
668 | ead9360e | ths | void do_ctc1 (int reg) |
669 | ead9360e | ths | { |
670 | ead9360e | ths | switch(reg) {
|
671 | fd4a04eb | ths | case 25: |
672 | fd4a04eb | ths | if (T0 & 0xffffff00) |
673 | fd4a04eb | ths | return;
|
674 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) | |
675 | fd4a04eb | ths | ((T0 & 0x1) << 23); |
676 | fd4a04eb | ths | break;
|
677 | fd4a04eb | ths | case 26: |
678 | fd4a04eb | ths | if (T0 & 0x007c0000) |
679 | fd4a04eb | ths | return;
|
680 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c); |
681 | fd4a04eb | ths | break;
|
682 | fd4a04eb | ths | case 28: |
683 | fd4a04eb | ths | if (T0 & 0x007c0000) |
684 | fd4a04eb | ths | return;
|
685 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) | |
686 | fd4a04eb | ths | ((T0 & 0x4) << 22); |
687 | fd4a04eb | ths | break;
|
688 | fd4a04eb | ths | case 31: |
689 | fd4a04eb | ths | if (T0 & 0x007c0000) |
690 | fd4a04eb | ths | return;
|
691 | ead9360e | ths | env->fpu->fcr31 = T0; |
692 | fd4a04eb | ths | break;
|
693 | fd4a04eb | ths | default:
|
694 | fd4a04eb | ths | return;
|
695 | fd4a04eb | ths | } |
696 | fd4a04eb | ths | /* set rounding mode */
|
697 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
698 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
699 | ead9360e | ths | if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31)) |
700 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
701 | fd4a04eb | ths | } |
702 | fd4a04eb | ths | |
703 | aa343735 | ths | static always_inline char ieee_ex_to_mips(char xcpt) |
704 | fd4a04eb | ths | { |
705 | fd4a04eb | ths | return (xcpt & float_flag_inexact) >> 5 | |
706 | fd4a04eb | ths | (xcpt & float_flag_underflow) >> 3 |
|
707 | fd4a04eb | ths | (xcpt & float_flag_overflow) >> 1 |
|
708 | fd4a04eb | ths | (xcpt & float_flag_divbyzero) << 1 |
|
709 | fd4a04eb | ths | (xcpt & float_flag_invalid) << 4;
|
710 | fd4a04eb | ths | } |
711 | fd4a04eb | ths | |
712 | aa343735 | ths | static always_inline char mips_ex_to_ieee(char xcpt) |
713 | fd4a04eb | ths | { |
714 | fd4a04eb | ths | return (xcpt & FP_INEXACT) << 5 | |
715 | fd4a04eb | ths | (xcpt & FP_UNDERFLOW) << 3 |
|
716 | fd4a04eb | ths | (xcpt & FP_OVERFLOW) << 1 |
|
717 | fd4a04eb | ths | (xcpt & FP_DIV0) >> 1 |
|
718 | fd4a04eb | ths | (xcpt & FP_INVALID) >> 4;
|
719 | fd4a04eb | ths | } |
720 | fd4a04eb | ths | |
721 | aa343735 | ths | static always_inline void update_fcr31(void) |
722 | fd4a04eb | ths | { |
723 | ead9360e | ths | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
|
724 | fd4a04eb | ths | |
725 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, tmp); |
726 | ead9360e | ths | if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
|
727 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
728 | fd4a04eb | ths | else
|
729 | ead9360e | ths | UPDATE_FP_FLAGS(env->fpu->fcr31, tmp); |
730 | fd4a04eb | ths | } |
731 | fd4a04eb | ths | |
732 | fd4a04eb | ths | #define FLOAT_OP(name, p) void do_float_##name##_##p(void) |
733 | fd4a04eb | ths | |
734 | fd4a04eb | ths | FLOAT_OP(cvtd, s) |
735 | fd4a04eb | ths | { |
736 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
737 | ead9360e | ths | FDT2 = float32_to_float64(FST0, &env->fpu->fp_status); |
738 | fd4a04eb | ths | update_fcr31(); |
739 | fd4a04eb | ths | } |
740 | fd4a04eb | ths | FLOAT_OP(cvtd, w) |
741 | fd4a04eb | ths | { |
742 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
743 | ead9360e | ths | FDT2 = int32_to_float64(WT0, &env->fpu->fp_status); |
744 | fd4a04eb | ths | update_fcr31(); |
745 | fd4a04eb | ths | } |
746 | fd4a04eb | ths | FLOAT_OP(cvtd, l) |
747 | fd4a04eb | ths | { |
748 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
749 | ead9360e | ths | FDT2 = int64_to_float64(DT0, &env->fpu->fp_status); |
750 | fd4a04eb | ths | update_fcr31(); |
751 | fd4a04eb | ths | } |
752 | fd4a04eb | ths | FLOAT_OP(cvtl, d) |
753 | fd4a04eb | ths | { |
754 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
755 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
756 | fd4a04eb | ths | update_fcr31(); |
757 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
758 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
759 | fd4a04eb | ths | } |
760 | fd4a04eb | ths | FLOAT_OP(cvtl, s) |
761 | fd4a04eb | ths | { |
762 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
763 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
764 | fd4a04eb | ths | update_fcr31(); |
765 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
766 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
767 | fd4a04eb | ths | } |
768 | fd4a04eb | ths | |
769 | fd4a04eb | ths | FLOAT_OP(cvtps, pw) |
770 | fd4a04eb | ths | { |
771 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
772 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
773 | ead9360e | ths | FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status); |
774 | fd4a04eb | ths | update_fcr31(); |
775 | fd4a04eb | ths | } |
776 | fd4a04eb | ths | FLOAT_OP(cvtpw, ps) |
777 | fd4a04eb | ths | { |
778 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
779 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
780 | ead9360e | ths | WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status); |
781 | fd4a04eb | ths | update_fcr31(); |
782 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
783 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
784 | fd4a04eb | ths | } |
785 | fd4a04eb | ths | FLOAT_OP(cvts, d) |
786 | fd4a04eb | ths | { |
787 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
788 | ead9360e | ths | FST2 = float64_to_float32(FDT0, &env->fpu->fp_status); |
789 | fd4a04eb | ths | update_fcr31(); |
790 | fd4a04eb | ths | } |
791 | fd4a04eb | ths | FLOAT_OP(cvts, w) |
792 | fd4a04eb | ths | { |
793 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
794 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
795 | fd4a04eb | ths | update_fcr31(); |
796 | fd4a04eb | ths | } |
797 | fd4a04eb | ths | FLOAT_OP(cvts, l) |
798 | fd4a04eb | ths | { |
799 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
800 | ead9360e | ths | FST2 = int64_to_float32(DT0, &env->fpu->fp_status); |
801 | fd4a04eb | ths | update_fcr31(); |
802 | fd4a04eb | ths | } |
803 | fd4a04eb | ths | FLOAT_OP(cvts, pl) |
804 | fd4a04eb | ths | { |
805 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
806 | fd4a04eb | ths | WT2 = WT0; |
807 | fd4a04eb | ths | update_fcr31(); |
808 | fd4a04eb | ths | } |
809 | fd4a04eb | ths | FLOAT_OP(cvts, pu) |
810 | fd4a04eb | ths | { |
811 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
812 | fd4a04eb | ths | WT2 = WTH0; |
813 | fd4a04eb | ths | update_fcr31(); |
814 | fd4a04eb | ths | } |
815 | fd4a04eb | ths | FLOAT_OP(cvtw, s) |
816 | fd4a04eb | ths | { |
817 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
818 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
819 | fd4a04eb | ths | update_fcr31(); |
820 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
821 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
822 | fd4a04eb | ths | } |
823 | fd4a04eb | ths | FLOAT_OP(cvtw, d) |
824 | fd4a04eb | ths | { |
825 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
826 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
827 | fd4a04eb | ths | update_fcr31(); |
828 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
829 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
830 | fd4a04eb | ths | } |
831 | fd4a04eb | ths | |
832 | fd4a04eb | ths | FLOAT_OP(roundl, d) |
833 | fd4a04eb | ths | { |
834 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
835 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
836 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
837 | fd4a04eb | ths | update_fcr31(); |
838 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
839 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
840 | fd4a04eb | ths | } |
841 | fd4a04eb | ths | FLOAT_OP(roundl, s) |
842 | fd4a04eb | ths | { |
843 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
844 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
845 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
846 | fd4a04eb | ths | update_fcr31(); |
847 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
848 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
849 | fd4a04eb | ths | } |
850 | fd4a04eb | ths | FLOAT_OP(roundw, d) |
851 | fd4a04eb | ths | { |
852 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
853 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
854 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
855 | fd4a04eb | ths | update_fcr31(); |
856 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
857 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
858 | fd4a04eb | ths | } |
859 | fd4a04eb | ths | FLOAT_OP(roundw, s) |
860 | fd4a04eb | ths | { |
861 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
862 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
863 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
864 | fd4a04eb | ths | update_fcr31(); |
865 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
866 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
867 | fd4a04eb | ths | } |
868 | fd4a04eb | ths | |
869 | fd4a04eb | ths | FLOAT_OP(truncl, d) |
870 | fd4a04eb | ths | { |
871 | ead9360e | ths | DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status); |
872 | fd4a04eb | ths | update_fcr31(); |
873 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
874 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
875 | fd4a04eb | ths | } |
876 | fd4a04eb | ths | FLOAT_OP(truncl, s) |
877 | fd4a04eb | ths | { |
878 | ead9360e | ths | DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status); |
879 | fd4a04eb | ths | update_fcr31(); |
880 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
881 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
882 | fd4a04eb | ths | } |
883 | fd4a04eb | ths | FLOAT_OP(truncw, d) |
884 | fd4a04eb | ths | { |
885 | ead9360e | ths | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status); |
886 | fd4a04eb | ths | update_fcr31(); |
887 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
888 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
889 | fd4a04eb | ths | } |
890 | fd4a04eb | ths | FLOAT_OP(truncw, s) |
891 | fd4a04eb | ths | { |
892 | ead9360e | ths | WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status); |
893 | fd4a04eb | ths | update_fcr31(); |
894 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
895 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
896 | fd4a04eb | ths | } |
897 | fd4a04eb | ths | |
898 | fd4a04eb | ths | FLOAT_OP(ceill, d) |
899 | fd4a04eb | ths | { |
900 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
901 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
902 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
903 | fd4a04eb | ths | update_fcr31(); |
904 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
905 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
906 | fd4a04eb | ths | } |
907 | fd4a04eb | ths | FLOAT_OP(ceill, s) |
908 | fd4a04eb | ths | { |
909 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
910 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
911 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
912 | fd4a04eb | ths | update_fcr31(); |
913 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
914 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
915 | fd4a04eb | ths | } |
916 | fd4a04eb | ths | FLOAT_OP(ceilw, d) |
917 | fd4a04eb | ths | { |
918 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
919 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
920 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
921 | fd4a04eb | ths | update_fcr31(); |
922 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
923 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
924 | fd4a04eb | ths | } |
925 | fd4a04eb | ths | FLOAT_OP(ceilw, s) |
926 | fd4a04eb | ths | { |
927 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
928 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
929 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
930 | fd4a04eb | ths | update_fcr31(); |
931 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
932 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
933 | fd4a04eb | ths | } |
934 | fd4a04eb | ths | |
935 | fd4a04eb | ths | FLOAT_OP(floorl, d) |
936 | fd4a04eb | ths | { |
937 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
938 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
939 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
940 | fd4a04eb | ths | update_fcr31(); |
941 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
942 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
943 | fd4a04eb | ths | } |
944 | fd4a04eb | ths | FLOAT_OP(floorl, s) |
945 | fd4a04eb | ths | { |
946 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
947 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
948 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
949 | fd4a04eb | ths | update_fcr31(); |
950 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
951 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
952 | fd4a04eb | ths | } |
953 | fd4a04eb | ths | FLOAT_OP(floorw, d) |
954 | fd4a04eb | ths | { |
955 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
956 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
957 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
958 | fd4a04eb | ths | update_fcr31(); |
959 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
960 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
961 | fd4a04eb | ths | } |
962 | fd4a04eb | ths | FLOAT_OP(floorw, s) |
963 | fd4a04eb | ths | { |
964 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
965 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
966 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
967 | fd4a04eb | ths | update_fcr31(); |
968 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
969 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
970 | fd4a04eb | ths | } |
971 | fd4a04eb | ths | |
972 | 8dfdb87c | ths | /* MIPS specific unary operations */
|
973 | 8dfdb87c | ths | FLOAT_OP(recip, d) |
974 | 8dfdb87c | ths | { |
975 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
976 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
977 | 8dfdb87c | ths | update_fcr31(); |
978 | 8dfdb87c | ths | } |
979 | 8dfdb87c | ths | FLOAT_OP(recip, s) |
980 | 8dfdb87c | ths | { |
981 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
982 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
983 | 8dfdb87c | ths | update_fcr31(); |
984 | 57fa1fb3 | ths | } |
985 | 57fa1fb3 | ths | |
986 | 8dfdb87c | ths | FLOAT_OP(rsqrt, d) |
987 | 8dfdb87c | ths | { |
988 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
989 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
990 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
991 | 8dfdb87c | ths | update_fcr31(); |
992 | 8dfdb87c | ths | } |
993 | 8dfdb87c | ths | FLOAT_OP(rsqrt, s) |
994 | 8dfdb87c | ths | { |
995 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
996 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
997 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
998 | 8dfdb87c | ths | update_fcr31(); |
999 | 8dfdb87c | ths | } |
1000 | 8dfdb87c | ths | |
1001 | 8dfdb87c | ths | FLOAT_OP(recip1, d) |
1002 | 8dfdb87c | ths | { |
1003 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1004 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
1005 | 8dfdb87c | ths | update_fcr31(); |
1006 | 8dfdb87c | ths | } |
1007 | 8dfdb87c | ths | FLOAT_OP(recip1, s) |
1008 | 8dfdb87c | ths | { |
1009 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1010 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1011 | 8dfdb87c | ths | update_fcr31(); |
1012 | 8dfdb87c | ths | } |
1013 | 8dfdb87c | ths | FLOAT_OP(recip1, ps) |
1014 | 8dfdb87c | ths | { |
1015 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1016 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1017 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status); |
1018 | 8dfdb87c | ths | update_fcr31(); |
1019 | 8dfdb87c | ths | } |
1020 | 8dfdb87c | ths | |
1021 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, d) |
1022 | 8dfdb87c | ths | { |
1023 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1024 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
1025 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
1026 | 8dfdb87c | ths | update_fcr31(); |
1027 | 8dfdb87c | ths | } |
1028 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, s) |
1029 | 8dfdb87c | ths | { |
1030 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1031 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1032 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1033 | 8dfdb87c | ths | update_fcr31(); |
1034 | 8dfdb87c | ths | } |
1035 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, ps) |
1036 | 8dfdb87c | ths | { |
1037 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1038 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1039 | ead9360e | ths | FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status); |
1040 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1041 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status); |
1042 | 8dfdb87c | ths | update_fcr31(); |
1043 | 57fa1fb3 | ths | } |
1044 | 57fa1fb3 | ths | |
1045 | fd4a04eb | ths | /* binary operations */
|
1046 | fd4a04eb | ths | #define FLOAT_BINOP(name) \
|
1047 | fd4a04eb | ths | FLOAT_OP(name, d) \ |
1048 | fd4a04eb | ths | { \ |
1049 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1050 | ead9360e | ths | FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \ |
1051 | ead9360e | ths | update_fcr31(); \ |
1052 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1053 | 54454097 | ths | FDT2 = FLOAT_QNAN64; \ |
1054 | fd4a04eb | ths | } \ |
1055 | fd4a04eb | ths | FLOAT_OP(name, s) \ |
1056 | fd4a04eb | ths | { \ |
1057 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1058 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1059 | ead9360e | ths | update_fcr31(); \ |
1060 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1061 | 54454097 | ths | FST2 = FLOAT_QNAN32; \ |
1062 | fd4a04eb | ths | } \ |
1063 | fd4a04eb | ths | FLOAT_OP(name, ps) \ |
1064 | fd4a04eb | ths | { \ |
1065 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1066 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1067 | ead9360e | ths | FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \ |
1068 | fd4a04eb | ths | update_fcr31(); \ |
1069 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
|
1070 | 54454097 | ths | FST2 = FLOAT_QNAN32; \ |
1071 | 54454097 | ths | FSTH2 = FLOAT_QNAN32; \ |
1072 | 3a5b360d | ths | } \ |
1073 | fd4a04eb | ths | } |
1074 | fd4a04eb | ths | FLOAT_BINOP(add) |
1075 | fd4a04eb | ths | FLOAT_BINOP(sub) |
1076 | fd4a04eb | ths | FLOAT_BINOP(mul) |
1077 | fd4a04eb | ths | FLOAT_BINOP(div) |
1078 | fd4a04eb | ths | #undef FLOAT_BINOP
|
1079 | fd4a04eb | ths | |
1080 | 8dfdb87c | ths | /* MIPS specific binary operations */
|
1081 | 8dfdb87c | ths | FLOAT_OP(recip2, d) |
1082 | 8dfdb87c | ths | { |
1083 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1084 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1085 | ead9360e | ths | FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64; |
1086 | 8dfdb87c | ths | update_fcr31(); |
1087 | 8dfdb87c | ths | } |
1088 | 8dfdb87c | ths | FLOAT_OP(recip2, s) |
1089 | 8dfdb87c | ths | { |
1090 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1091 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1092 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1093 | 8dfdb87c | ths | update_fcr31(); |
1094 | 8dfdb87c | ths | } |
1095 | 8dfdb87c | ths | FLOAT_OP(recip2, ps) |
1096 | 8dfdb87c | ths | { |
1097 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1098 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1099 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1100 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1101 | ead9360e | ths | FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1102 | 8dfdb87c | ths | update_fcr31(); |
1103 | 8dfdb87c | ths | } |
1104 | 8dfdb87c | ths | |
1105 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, d) |
1106 | 8dfdb87c | ths | { |
1107 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1108 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1109 | ead9360e | ths | FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status); |
1110 | ead9360e | ths | FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64; |
1111 | 8dfdb87c | ths | update_fcr31(); |
1112 | 8dfdb87c | ths | } |
1113 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, s) |
1114 | 8dfdb87c | ths | { |
1115 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1116 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1117 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1118 | ead9360e | ths | FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1119 | 8dfdb87c | ths | update_fcr31(); |
1120 | 8dfdb87c | ths | } |
1121 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, ps) |
1122 | 8dfdb87c | ths | { |
1123 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1124 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1125 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1126 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1127 | ead9360e | ths | FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status); |
1128 | ead9360e | ths | FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1129 | ead9360e | ths | FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1130 | 8dfdb87c | ths | update_fcr31(); |
1131 | 57fa1fb3 | ths | } |
1132 | 57fa1fb3 | ths | |
1133 | fd4a04eb | ths | FLOAT_OP(addr, ps) |
1134 | fd4a04eb | ths | { |
1135 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1136 | ead9360e | ths | FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status); |
1137 | ead9360e | ths | FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status); |
1138 | fd4a04eb | ths | update_fcr31(); |
1139 | fd4a04eb | ths | } |
1140 | fd4a04eb | ths | |
1141 | 57fa1fb3 | ths | FLOAT_OP(mulr, ps) |
1142 | 57fa1fb3 | ths | { |
1143 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1144 | ead9360e | ths | FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status); |
1145 | ead9360e | ths | FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status); |
1146 | 57fa1fb3 | ths | update_fcr31(); |
1147 | 57fa1fb3 | ths | } |
1148 | 57fa1fb3 | ths | |
1149 | 8dfdb87c | ths | /* compare operations */
|
1150 | fd4a04eb | ths | #define FOP_COND_D(op, cond) \
|
1151 | fd4a04eb | ths | void do_cmp_d_ ## op (long cc) \ |
1152 | fd4a04eb | ths | { \ |
1153 | fd4a04eb | ths | int c = cond; \
|
1154 | fd4a04eb | ths | update_fcr31(); \ |
1155 | fd4a04eb | ths | if (c) \
|
1156 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1157 | fd4a04eb | ths | else \
|
1158 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1159 | fd4a04eb | ths | } \ |
1160 | fd4a04eb | ths | void do_cmpabs_d_ ## op (long cc) \ |
1161 | fd4a04eb | ths | { \ |
1162 | fd4a04eb | ths | int c; \
|
1163 | 8dfdb87c | ths | FDT0 &= ~FLOAT_SIGN64; \ |
1164 | 8dfdb87c | ths | FDT1 &= ~FLOAT_SIGN64; \ |
1165 | fd4a04eb | ths | c = cond; \ |
1166 | fd4a04eb | ths | update_fcr31(); \ |
1167 | fd4a04eb | ths | if (c) \
|
1168 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1169 | fd4a04eb | ths | else \
|
1170 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1171 | fd4a04eb | ths | } |
1172 | fd4a04eb | ths | |
1173 | fd4a04eb | ths | int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
1174 | fd4a04eb | ths | { |
1175 | fd4a04eb | ths | if (float64_is_signaling_nan(a) ||
|
1176 | fd4a04eb | ths | float64_is_signaling_nan(b) || |
1177 | fd4a04eb | ths | (sig && (float64_is_nan(a) || float64_is_nan(b)))) { |
1178 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1179 | fd4a04eb | ths | return 1; |
1180 | fd4a04eb | ths | } else if (float64_is_nan(a) || float64_is_nan(b)) { |
1181 | fd4a04eb | ths | return 1; |
1182 | fd4a04eb | ths | } else {
|
1183 | fd4a04eb | ths | return 0; |
1184 | fd4a04eb | ths | } |
1185 | fd4a04eb | ths | } |
1186 | fd4a04eb | ths | |
1187 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1188 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1189 | ead9360e | ths | FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1190 | ead9360e | ths | FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
|
1191 | ead9360e | ths | FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1192 | ead9360e | ths | FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1193 | ead9360e | ths | FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1194 | ead9360e | ths | FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1195 | ead9360e | ths | FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1196 | ead9360e | ths | FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1197 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1198 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1199 | ead9360e | ths | FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1200 | ead9360e | ths | FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
|
1201 | ead9360e | ths | FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1202 | ead9360e | ths | FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1203 | ead9360e | ths | FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1204 | ead9360e | ths | FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1205 | ead9360e | ths | FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1206 | ead9360e | ths | FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1207 | fd4a04eb | ths | |
1208 | fd4a04eb | ths | #define FOP_COND_S(op, cond) \
|
1209 | fd4a04eb | ths | void do_cmp_s_ ## op (long cc) \ |
1210 | fd4a04eb | ths | { \ |
1211 | fd4a04eb | ths | int c = cond; \
|
1212 | fd4a04eb | ths | update_fcr31(); \ |
1213 | fd4a04eb | ths | if (c) \
|
1214 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1215 | fd4a04eb | ths | else \
|
1216 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1217 | fd4a04eb | ths | } \ |
1218 | fd4a04eb | ths | void do_cmpabs_s_ ## op (long cc) \ |
1219 | fd4a04eb | ths | { \ |
1220 | fd4a04eb | ths | int c; \
|
1221 | 8dfdb87c | ths | FST0 &= ~FLOAT_SIGN32; \ |
1222 | 8dfdb87c | ths | FST1 &= ~FLOAT_SIGN32; \ |
1223 | fd4a04eb | ths | c = cond; \ |
1224 | fd4a04eb | ths | update_fcr31(); \ |
1225 | fd4a04eb | ths | if (c) \
|
1226 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1227 | fd4a04eb | ths | else \
|
1228 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1229 | fd4a04eb | ths | } |
1230 | fd4a04eb | ths | |
1231 | fd4a04eb | ths | flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
|
1232 | fd4a04eb | ths | { |
1233 | fd4a04eb | ths | if (float32_is_signaling_nan(a) ||
|
1234 | fd4a04eb | ths | float32_is_signaling_nan(b) || |
1235 | fd4a04eb | ths | (sig && (float32_is_nan(a) || float32_is_nan(b)))) { |
1236 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1237 | fd4a04eb | ths | return 1; |
1238 | fd4a04eb | ths | } else if (float32_is_nan(a) || float32_is_nan(b)) { |
1239 | fd4a04eb | ths | return 1; |
1240 | fd4a04eb | ths | } else {
|
1241 | fd4a04eb | ths | return 0; |
1242 | fd4a04eb | ths | } |
1243 | fd4a04eb | ths | } |
1244 | fd4a04eb | ths | |
1245 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1246 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1247 | ead9360e | ths | FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0)) |
1248 | ead9360e | ths | FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
|
1249 | ead9360e | ths | FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1250 | ead9360e | ths | FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1251 | ead9360e | ths | FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1252 | ead9360e | ths | FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1253 | ead9360e | ths | FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1254 | ead9360e | ths | FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1255 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1256 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1257 | ead9360e | ths | FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0)) |
1258 | ead9360e | ths | FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
|
1259 | ead9360e | ths | FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1260 | ead9360e | ths | FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1261 | ead9360e | ths | FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1262 | ead9360e | ths | FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1263 | ead9360e | ths | FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1264 | ead9360e | ths | FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1265 | fd4a04eb | ths | |
1266 | fd4a04eb | ths | #define FOP_COND_PS(op, condl, condh) \
|
1267 | fd4a04eb | ths | void do_cmp_ps_ ## op (long cc) \ |
1268 | fd4a04eb | ths | { \ |
1269 | fd4a04eb | ths | int cl = condl; \
|
1270 | fd4a04eb | ths | int ch = condh; \
|
1271 | fd4a04eb | ths | update_fcr31(); \ |
1272 | fd4a04eb | ths | if (cl) \
|
1273 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1274 | fd4a04eb | ths | else \
|
1275 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1276 | fd4a04eb | ths | if (ch) \
|
1277 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
|
1278 | fd4a04eb | ths | else \
|
1279 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
|
1280 | fd4a04eb | ths | } \ |
1281 | fd4a04eb | ths | void do_cmpabs_ps_ ## op (long cc) \ |
1282 | fd4a04eb | ths | { \ |
1283 | fd4a04eb | ths | int cl, ch; \
|
1284 | 8dfdb87c | ths | FST0 &= ~FLOAT_SIGN32; \ |
1285 | 8dfdb87c | ths | FSTH0 &= ~FLOAT_SIGN32; \ |
1286 | 8dfdb87c | ths | FST1 &= ~FLOAT_SIGN32; \ |
1287 | 8dfdb87c | ths | FSTH1 &= ~FLOAT_SIGN32; \ |
1288 | fd4a04eb | ths | cl = condl; \ |
1289 | fd4a04eb | ths | ch = condh; \ |
1290 | fd4a04eb | ths | update_fcr31(); \ |
1291 | fd4a04eb | ths | if (cl) \
|
1292 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1293 | fd4a04eb | ths | else \
|
1294 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1295 | fd4a04eb | ths | if (ch) \
|
1296 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
|
1297 | fd4a04eb | ths | else \
|
1298 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
|
1299 | fd4a04eb | ths | } |
1300 | fd4a04eb | ths | |
1301 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1302 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1303 | ead9360e | ths | FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0), |
1304 | ead9360e | ths | (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1305 | ead9360e | ths | FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
|
1306 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
|
1307 | ead9360e | ths | FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1308 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1309 | ead9360e | ths | FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1310 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1311 | ead9360e | ths | FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1312 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1313 | ead9360e | ths | FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1314 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1315 | ead9360e | ths | FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
1316 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1317 | ead9360e | ths | FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
1318 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1319 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1320 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1321 | ead9360e | ths | FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0), |
1322 | ead9360e | ths | (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1323 | ead9360e | ths | FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
|
1324 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
|
1325 | ead9360e | ths | FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1326 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1327 | ead9360e | ths | FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1328 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1329 | ead9360e | ths | FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1330 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1331 | ead9360e | ths | FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1332 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1333 | ead9360e | ths | FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
1334 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1335 | ead9360e | ths | FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
1336 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status)) |